rockchip: clk: rk3399: 24MHz is not a power of 2

The clock driver for the RK3399 mistakenly used (24 * 2^20) where it
should have used (24 * 10^6) in a few calculations.

This commits fixes this.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 1ac4ff4b2b22e5559900399bdb8336fa8c744d49..ff3cc37af33842f534b0f0cbeaf426ae269e4738 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -667,7 +667,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
 
        if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
                        == CLK_EMMC_PLL_SEL_24M)
-               return DIV_TO_RATE(24*1024*1024, div);
+               return DIV_TO_RATE(24*1000*1000, div);
        else
                return DIV_TO_RATE(GPLL_HZ, div);
 }
@@ -685,7 +685,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
 
                if (src_clk_div > 127) {
                        /* use 24MHz source for 400KHz clock */
-                       src_clk_div = 24*1024*1024 / set_rate;
+                       src_clk_div = 24*1000*1000 / set_rate;
                        rk_clrsetreg(&cru->clksel_con[16],
                                     CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
                                     CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |