spl/mpc85xx: rename cpu_init_nand.c to spl_minimal.c
authorScott Wood <scottwood@freescale.com>
Thu, 20 Sep 2012 21:35:21 +0000 (16:35 -0500)
committerScott Wood <scottwood@freescale.com>
Mon, 26 Nov 2012 21:41:24 +0000 (15:41 -0600)
There is nothing really NAND-specific about this file.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c [deleted file]
arch/powerpc/cpu/mpc85xx/spl_minimal.c [new file with mode: 0644]
nand_spl/board/freescale/mpc8536ds/Makefile
nand_spl/board/freescale/mpc8569mds/Makefile
nand_spl/board/freescale/mpc8572ds/Makefile
nand_spl/board/freescale/p1010rdb/Makefile
nand_spl/board/freescale/p1023rds/Makefile
nand_spl/board/freescale/p1_p2_rdb/Makefile
nand_spl/board/freescale/p1_p2_rdb_pc/Makefile

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
deleted file mode 100644 (file)
index 0589497..0000000
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/global_data.h>
-#include <asm/fsl_ifc.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void cpu_init_f(void)
-{
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
-       ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
-
-       out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
-
-       /* set MBECCDIS=1, SBECCDIS=1 */
-       out_be32(&l2cache->l2errdis,
-               (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
-
-       /* set L2E=1 & L2SRAM=001 */
-       out_be32(&l2cache->l2ctl,
-               (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
-#endif
-}
-
-#ifndef CONFIG_SYS_FSL_TBCLK_DIV
-#define CONFIG_SYS_FSL_TBCLK_DIV 8
-#endif
-
-void udelay(unsigned long usec)
-{
-       u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
-       u32 ticks = ticks_per_usec * usec;
-       u32 s = mfspr(SPRN_TBRL);
-
-       while ((mfspr(SPRN_TBRL) - s) < ticks);
-}
diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
new file mode 100644 (file)
index 0000000..0589497
--- /dev/null
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/global_data.h>
+#include <asm/fsl_ifc.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void cpu_init_f(void)
+{
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+       ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+
+       out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
+
+       /* set MBECCDIS=1, SBECCDIS=1 */
+       out_be32(&l2cache->l2errdis,
+               (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
+
+       /* set L2E=1 & L2SRAM=001 */
+       out_be32(&l2cache->l2ctl,
+               (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
+#endif
+}
+
+#ifndef CONFIG_SYS_FSL_TBCLK_DIV
+#define CONFIG_SYS_FSL_TBCLK_DIV 8
+#endif
+
+void udelay(unsigned long usec)
+{
+       u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
+       u32 ticks = ticks_per_usec * usec;
+       u32 s = mfspr(SPRN_TBRL);
+
+       while ((mfspr(SPRN_TBRL) - s) < ticks);
+}
index bc3ba354460fc7e83167a7442f21e9b2742f6b81..9c778261b6f7e8fa19d8c7dc7a0274b8d7a4074f 100644 (file)
@@ -39,7 +39,7 @@ AFLAGS        += -DCONFIG_NAND_SPL
 CFLAGS += -DCONFIG_NAND_SPL
 
 SOBJS  = start.o resetvec.o
-COBJS  = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS  = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
          nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
 SRCS   := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@@ -80,9 +80,9 @@ $(obj)cpu_init_early.c:
        @rm -f $(obj)cpu_init_early.c
        ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
 
-$(obj)cpu_init_nand.c:
-       @rm -f $(obj)cpu_init_nand.c
-       ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+       @rm -f $(obj)spl_minimal.c
+       ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
 
 $(obj)fsl_law.c:
        @rm -f $(obj)fsl_law.c
index bc3ba354460fc7e83167a7442f21e9b2742f6b81..9c778261b6f7e8fa19d8c7dc7a0274b8d7a4074f 100644 (file)
@@ -39,7 +39,7 @@ AFLAGS        += -DCONFIG_NAND_SPL
 CFLAGS += -DCONFIG_NAND_SPL
 
 SOBJS  = start.o resetvec.o
-COBJS  = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS  = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
          nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
 SRCS   := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@@ -80,9 +80,9 @@ $(obj)cpu_init_early.c:
        @rm -f $(obj)cpu_init_early.c
        ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
 
-$(obj)cpu_init_nand.c:
-       @rm -f $(obj)cpu_init_nand.c
-       ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+       @rm -f $(obj)spl_minimal.c
+       ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
 
 $(obj)fsl_law.c:
        @rm -f $(obj)fsl_law.c
index bc3ba354460fc7e83167a7442f21e9b2742f6b81..9c778261b6f7e8fa19d8c7dc7a0274b8d7a4074f 100644 (file)
@@ -39,7 +39,7 @@ AFLAGS        += -DCONFIG_NAND_SPL
 CFLAGS += -DCONFIG_NAND_SPL
 
 SOBJS  = start.o resetvec.o
-COBJS  = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS  = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
          nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
 SRCS   := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@@ -80,9 +80,9 @@ $(obj)cpu_init_early.c:
        @rm -f $(obj)cpu_init_early.c
        ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
 
-$(obj)cpu_init_nand.c:
-       @rm -f $(obj)cpu_init_nand.c
-       ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+       @rm -f $(obj)spl_minimal.c
+       ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
 
 $(obj)fsl_law.c:
        @rm -f $(obj)fsl_law.c
index acf7577d5c9b9a35ca704a8168dd752c29315edd..c3495ec0dff7dcb72fedaa09d6cf7b14850d482a 100644 (file)
@@ -39,7 +39,7 @@ AFLAGS        += -DCONFIG_NAND_SPL
 CFLAGS += -DCONFIG_NAND_SPL
 
 SOBJS  = start.o resetvec.o ticks.o
-COBJS  = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS  = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
          nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
 
 SRCS   := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@@ -80,9 +80,9 @@ $(obj)cpu_init_early.c:
        @rm -f $(obj)cpu_init_early.c
        ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
 
-$(obj)cpu_init_nand.c:
-       @rm -f $(obj)cpu_init_nand.c
-       ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+       @rm -f $(obj)spl_minimal.c
+       ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
 
 $(obj)fsl_law.c:
        @rm -f $(obj)fsl_law.c
index 9500ac894c72755522101300c980a69fc2e322a7..9b2c0d7f35711b81fcef00fc19bfb9cf64299370 100644 (file)
@@ -34,7 +34,7 @@ AFLAGS        += -DCONFIG_NAND_SPL
 CFLAGS += -DCONFIG_NAND_SPL
 
 SOBJS  = start.o resetvec.o
-COBJS  = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS  = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
          nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
 SRCS   := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@@ -75,9 +75,9 @@ $(obj)cpu_init_early.c:
        @rm -f $(obj)cpu_init_early.c
        ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
 
-$(obj)cpu_init_nand.c:
-       @rm -f $(obj)cpu_init_nand.c
-       ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+       @rm -f $(obj)spl_minimal.c
+       ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
 
 $(obj)fsl_law.c:
        @rm -f $(obj)fsl_law.c
index bc3ba354460fc7e83167a7442f21e9b2742f6b81..9c778261b6f7e8fa19d8c7dc7a0274b8d7a4074f 100644 (file)
@@ -39,7 +39,7 @@ AFLAGS        += -DCONFIG_NAND_SPL
 CFLAGS += -DCONFIG_NAND_SPL
 
 SOBJS  = start.o resetvec.o
-COBJS  = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS  = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
          nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
 SRCS   := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@@ -80,9 +80,9 @@ $(obj)cpu_init_early.c:
        @rm -f $(obj)cpu_init_early.c
        ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
 
-$(obj)cpu_init_nand.c:
-       @rm -f $(obj)cpu_init_nand.c
-       ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+       @rm -f $(obj)spl_minimal.c
+       ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
 
 $(obj)fsl_law.c:
        @rm -f $(obj)fsl_law.c
index 98d3ad03ac93b6ad3d0c871d7dd9ab92d8ca2713..797a80030cd7716687c4e4ff03dbbeba07c19dac 100644 (file)
@@ -39,7 +39,7 @@ AFLAGS        += -DCONFIG_NAND_SPL
 CFLAGS += -DCONFIG_NAND_SPL
 
 SOBJS  = start.o resetvec.o
-COBJS  = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS  = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
          nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
 
 SRCS   := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@@ -79,9 +79,9 @@ $(obj)cpu_init_early.c:
        @rm -f $(obj)cpu_init_early.c
        ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
 
-$(obj)cpu_init_nand.c:
-       @rm -f $(obj)cpu_init_nand.c
-       ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+       @rm -f $(obj)spl_minimal.c
+       ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
 
 $(obj)fsl_law.c:
        @rm -f $(obj)fsl_law.c