#define MPC85xx_PMUXCR_QE10 0x00000020
#define MPC85xx_PMUXCR_QE11 0x00000010
#define MPC85xx_PMUXCR_QE12 0x00000008
+#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
+#define MPC85xx_PMUXCR_TDM 0x00014800
+#define MPC85xx_PMUXCR_SPI_MASK 0x00600000
+#define MPC85xx_PMUXCR_SPI 0x00000000
+#endif
u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
+#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f1000
+#define MPC85xx_PMUXCR2_USB 0x00150000
+#endif
u8 res6[8];
u32 devdisr; /* Device disable control */
#define MPC85xx_DEVDISR_PCI1 0x80000000
/* Choose the 11.2896Mhz codec reference clock */
#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
+/* Connect to USB2 */
+#define CONFIG_PIXIS_BRDCFG0_USB2 0x10
+/* Connect to TFM bus */
+#define CONFIG_PIXIS_BRDCFG1_TDM 0x0c
+/* Connect to SPI */
+#define CONFIG_PIXIS_BRDCFG0_SPI 0x80
+
int misc_init_r(void)
{
u8 temp;
const char *audclk;
size_t arglen;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* For DVI, enable the TFP410 Encoder. */
return -1;
debug("DVI Encoder Read: 0x%02x\n",temp);
+ /* Enable the USB2 in PMUXCR2 and FGPA */
+ if (hwconfig("usb2")) {
+ clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK,
+ MPC85xx_PMUXCR2_USB);
+ setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2);
+ }
+
+ /* tdm and audio can not enable simultaneous*/
+ if (hwconfig("tdm") && hwconfig("audclk")){
+ printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n");
+ return -1;
+ }
+
+ /* Enable the TDM in PMUXCR and FGPA */
+ if (hwconfig("tdm")) {
+ clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK,
+ MPC85xx_PMUXCR_TDM);
+ setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM);
+ /* TDM need some configration option by SPI */
+ clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK,
+ MPC85xx_PMUXCR_SPI);
+ setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI);
+ }
+
/*
* Enable the reference clock for the WM8776 codec, and route the MUX
* pins for SSI. The default is the 12.288 MHz clock
*/
- temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
- CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
- temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
-
- audclk = hwconfig_arg("audclk", &arglen);
- /* Check the first two chars only */
- if (audclk && (strncmp(audclk, "11", 2) == 0))
- temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
- else
- temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
- out_8(&pixis->brdcfg1, temp);
+ if (hwconfig("audclk")) {
+ temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
+ CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
+ temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
+
+ audclk = hwconfig_arg("audclk", &arglen);
+ /* Check the first two chars only */
+ if (audclk && (strncmp(audclk, "11", 2) == 0))
+ temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
+ else
+ temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
+ setbits_8(&pixis->brdcfg1, temp);
+ }
return 0;
}
--- /dev/null
+Overview
+--------
+P1022ds is a Low End Dual core platform supporting the P1022 processor
+of QorIQ series. P1022 is an e500 based dual core SOC.
+
+
+Pin Multiplex(hwconfig setting)
+-------------------------------
+Add the environment 'usb2', 'audclk' and 'tdm' to support pin multiplex
+via hwconfig, i.e:
+'setenv hwconfig usb2' to enable USB2 and disable eTsec2
+'setenv hwconfig tdm' to enable TDM and disable Audio
+'setenv hwconfig audclk:12' to enable Audio(codec clock sources is 12MHz)
+ and disable TDM
+'setenv hwconfig 'usb2;tdm' to enable USB2 and TDM, disable eTsec2 and Audio
+'setenv hwconfig 'usb2;audclk:11' to enable USB2 and Audio(codec clock sources
+ is 11MHz), disable eTsec2 and TDM
+
+Warning: TDM and AUDIO can not enable simultaneous !
+and AUDIO codec clock sources only setting as 11MHz or 12MHz !
+'setenv hwconfig 'audclk:12;tdm' --- error !
+'setenv hwconfig 'audclk:11;tdm' --- error !
+'setenv hwconfig 'audclk:10' --- error !
+