arm64: zero cntvoff_el2

Currently cntvoff_el2 is initialised with an arbitrary bag of bits
derived from the initial value of cnthctl_el2 on the current CPU. This is
somewhat odd and problematic as some of these bits are UNKNOWN at reset
and may differ across CPUs (which may cause an OS at EL1 to observe time
going backwards across CPUs).

This patch instead initialises cntvoff_el2 with xzr, giving the register
a consistent value of zero on all CPUs.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: David Feng <fenghua@phytium.com.cn>
Cc: Tom Rini <trini@ti.com>
Acked-by: David.Feng <fenghua@phytium.com.cn>

diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
index e0a59460091e04afd0e4abddb9d63cea03e35875..38dea5c51871eb4e20abf86f67aaf5bd9c4f6b10 100644 (file)
--- a/arch/arm/cpu/armv8/transition.S
+++ b/arch/arm/cpu/armv8/transition.S
@@ -43,7 +43,7 @@ ENTRY(armv8_switch_to_el1)
        mrs     x0, cnthctl_el2
        orr     x0, x0, #0x3            /* Enable EL1 access to timers */
        msr     cnthctl_el2, x0
-       msr     cntvoff_el2, x0
+       msr     cntvoff_el2, xzr
        mrs     x0, cntkctl_el1
        orr     x0, x0, #0x3            /* Enable EL0 access to timers */
        msr     cntkctl_el1, x0