ARM: Add workaround for Cortex-A9 errata 761320

Full cache line writes to the same memory region from at least two
processors might deadlock the processor. Exists on r1, r2, r3
revisions.

Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>

diff --git a/README b/README
index 00127a75ef76854d01062c90800c1c7cb7be7026..da85c8995c5fd18a4b48f55301a9fe6018c9577e 100644 (file)
--- a/README
+++ b/README
@@ -567,6 +567,7 @@ The following options need to be configured:
                CONFIG_ARM_ERRATA_743622
                CONFIG_ARM_ERRATA_751472
                CONFIG_ARM_ERRATA_794072
+               CONFIG_ARM_ERRATA_761320
 
                If set, the workarounds for these ARM errata are applied early
                during U-Boot startup. Note that these options force the

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index f3830c847161a0dc891cd3ef1fc0a6226347be18..27be451a89d5d39eed7e9809c04853954661b9dc 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15)
        orr     r0, r0, #1 << 11        @ set bit #11
        mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_761320
+       mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
+       orr     r0, r0, #1 << 21        @ set bit #21
+       mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
+#endif
 
        mov     pc, lr                  @ back to my caller
 ENDPROC(cpu_init_cp15)