ARM: Fix start.S when used with SPL in arm1136
authorStefano Babic <sbabic@denx.de>
Wed, 10 Oct 2012 21:11:41 +0000 (21:11 +0000)
committerStefano Babic <sbabic@denx.de>
Fri, 26 Oct 2012 14:27:58 +0000 (16:27 +0200)
This patch modifies start.S for the arm1136 to make it
conform to start.S  in armv7 architecture, to make it
usable if the SPL framework is used.

Signed-off-by: Stefano Babic <sbabic@denx.de>
arch/arm/cpu/arm1136/start.S
board/freescale/mx31ads/u-boot.lds
nand_spl/board/freescale/mx31pdk/u-boot.lds

index 3752af9ddd15bb91953f833a7c8698a082992de2..5d3b4c2299ef05659066c2f259205274a5c4710e 100644 (file)
@@ -100,6 +100,10 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
+.global        _image_copy_end_ofs
+_image_copy_end_ofs:
+       .word   __image_copy_end - _start
+
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end__ - _start
@@ -193,7 +197,7 @@ stack_setup:
        moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
        beq     clear_bss               /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _bss_start_ofs
+       ldr     r3, _image_copy_end_ofs
        add     r2, r0, r3              /* r2 <- source end address         */
 
 copy_loop:
@@ -241,15 +245,28 @@ fixnext:
        add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
        cmp     r2, r3
        blo     fixloop
+       b       clear_bss
+
+_rel_dyn_start_ofs:
+       .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+       .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+       .word __dynsym_start - _start
 #endif
 
 clear_bss:
-#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_BUILD
+       /* No relocation for SPL */
+       ldr     r0, =__bss_start
+       ldr     r1, =__bss_end__
+#else
        ldr     r0, _bss_start_ofs
        ldr     r1, _bss_end_ofs
        mov     r4, r6                  /* reloc addr */
        add     r0, r0, r4
        add     r1, r1, r4
+#endif
        mov     r2, #0x00000000         /* clear                            */
 
 clbss_l:cmp    r0, r1                  /* clear loop... */
@@ -258,7 +275,6 @@ clbss_l:cmp r0, r1                  /* clear loop... */
        add     r0, r0, #4
        b       clbss_l
 clbss_e:
-#endif /* #ifndef CONFIG_SPL_BUILD */
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -273,7 +289,7 @@ _nand_boot_ofs:
 #else
 jump_2_ram:
        ldr     r0, _board_init_r_ofs
-       ldr     r1, _TEXT_BASE
+       adr     r1, _start
        add     lr, r0, r1
        add     lr, lr, r9
        /* setup parameters for board_init_r */
@@ -286,13 +302,6 @@ _board_init_r_ofs:
        .word board_init_r - _start
 #endif
 
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
 /*
  *************************************************************************
  *
index 79eb7aca387b10a66281f5c51a71508237e4a0ec..91ffdbefd1310729cae71094b1c12b875fc1389e 100644 (file)
@@ -63,6 +63,8 @@ SECTIONS
 
        . = ALIGN(4);
 
+       __image_copy_end = .;
+
        .rel.dyn : {
                __rel_dyn_start = .;
                *(.rel*)
index d2b08f60c59c7597299ebab1c3002e02ebbdf6e8..a130a1f9df7374a372f1baa29f6a9dfdd9371e56 100644 (file)
@@ -52,6 +52,8 @@ SECTIONS
 
        . = ALIGN(4);
 
+       __image_copy_end = .;
+
        .rel.dyn : {
                __rel_dyn_start = .;
                *(.rel*)