powerpc/mpc85xx: Add T4160 SoC

T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 6776c85e4998b5db946ef3d9bc9511aea49e0edc..6e5aec26e03191d024c8da70f1b9df5ff6f49131 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -83,6 +83,7 @@ COBJS-$(CONFIG_PPC_P4080)     += ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5020)      += ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5040)      += ddr-gen3.o
 COBJS-$(CONFIG_PPC_T4240)      += ddr-gen3.o
+COBJS-$(CONFIG_PPC_T4160)      += ddr-gen3.o
 COBJS-$(CONFIG_PPC_B4420)      += ddr-gen3.o
 COBJS-$(CONFIG_PPC_B4860)      += ddr-gen3.o
 COBJS-$(CONFIG_BSC9131)                += ddr-gen3.o
@@ -102,6 +103,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
 COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
 COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o
+COBJS-$(CONFIG_PPC_T4160) += t4240_ids.o
 COBJS-$(CONFIG_PPC_B4420) += b4860_ids.o
 COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o
 
@@ -137,6 +139,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
 COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
 COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
+COBJS-$(CONFIG_PPC_T4160) += t4240_serdes.o
 COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o
 COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
 COBJS-$(CONFIG_BSC9132) += bsc9132_serdes.o

diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index 1316ed9e31fdca9fa8d310488f93a0ddd12cd174..c001780ca969c5cacd06d734e252d666f48627ea 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -31,6 +31,7 @@ struct serdes_config {
        u8 lanes[SRDS_MAX_LANES];
 };
 
+#ifdef CONFIG_PPC_T4240
 static const struct serdes_config serdes1_cfg_tbl[] = {
        /* SerDes 1 */
        {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
@@ -187,6 +188,137 @@ static const struct serdes_config serdes4_cfg_tbl[] = {
        {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
        {}
 };
+#elif defined(CONFIG_PPC_T4160)
+static const struct serdes_config serdes1_cfg_tbl[] = {
+       /* SerDes 1 */
+       {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+               XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+               XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+               XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
+       {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+               HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+               HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
+               HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
+       {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+               HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+               HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
+               HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
+       {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+       {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+       {38, {NONE, NONE, QSGMII_FM1_B, NONE,
+               NONE, NONE, QSGMII_FM1_A, NONE} },
+       {}
+};
+static const struct serdes_config serdes2_cfg_tbl[] = {
+       /* SerDes 2 */
+       {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               NONE, NONE} },
+       {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {38, {NONE, NONE, QSGMII_FM2_B, NONE,
+               NONE, QSGMII_FM1_A, NONE, NONE} },
+       {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, QSGMII_FM1_A, NONE, NONE} },
+       {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, QSGMII_FM1_A, NONE, NONE} },
+       {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, QSGMII_FM1_A, NONE, NONE} },
+       {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               NONE, NONE, NONE, NONE} },
+       {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               NONE, NONE, NONE, NONE} },
+       {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               NONE, NONE, NONE, NONE} },
+       {56, {NONE, XFI_FM1_MAC10,
+               XFI_FM2_MAC10, NONE,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+       {57, {NONE, XFI_FM1_MAC10,
+               XFI_FM2_MAC10, NONE,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               NONE, NONE} },
+       {}
+};
+static const struct serdes_config serdes3_cfg_tbl[] = {
+       /* SerDes 3 */
+       {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
+       {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
+       {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+       {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
+       {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
+       {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
+       {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               PCIE2, PCIE2, PCIE2, PCIE2} },
+       {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               PCIE2, PCIE2, PCIE2, PCIE2} },
+       {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               SRIO1, SRIO1, SRIO1, SRIO1} },
+       {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               SRIO1, SRIO1, SRIO1, SRIO1} },
+       {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               SRIO1, SRIO1, SRIO1, SRIO1} },
+       {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+                       NONE, NONE, NONE, NONE} },
+       {}
+};
+static const struct serdes_config serdes4_cfg_tbl[] = {
+       /* SerDes 4 */
+       {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
+       {6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+       {8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+       {10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
+       {12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
+       {14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
+       {16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
+       {18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
+       {}
+}
+;
+#else
+#error "Need to define SerDes protocol"
+#endif
 static const struct serdes_config *serdes_cfg_tbl[] = {
        serdes1_cfg_tbl,
        serdes2_cfg_tbl,

diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 39525fb29d55ed6163a2c748b594a7160b959117..0087cd029fe9a810d0880be2740bfe24d4842644 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -77,6 +77,7 @@ static struct cpu_type cpu_type_list[] = {
        CPU_TYPE_ENTRY(P5040, P5040, 4),
        CPU_TYPE_ENTRY(T4240, T4240, 0),
        CPU_TYPE_ENTRY(T4120, T4120, 0),
+       CPU_TYPE_ENTRY(T4160, T4160, 0),
        CPU_TYPE_ENTRY(B4860, B4860, 0),
        CPU_TYPE_ENTRY(G4860, G4860, 0),
        CPU_TYPE_ENTRY(G4060, G4060, 0),

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 6c02033f7138ef4fbbe0393674c9f1f071c7a7f9..75719414009d6951f9c1903d901d139cfee690ea 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -544,6 +544,39 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
 
+#elif defined(CONFIG_PPC_T4160)
+#define CONFIG_SYS_PPC64               /* 64-bit core */
+#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
+#define CONFIG_MAX_CPUS                        8
+#define CONFIG_SYS_FSL_NUM_CC_PLLS     5
+#define CONFIG_SYS_FSL_NUM_LAWS                32
+#define CONFIG_SYS_FSL_SRDS_3
+#define CONFIG_SYS_FSL_SRDS_4
+#define CONFIG_SYS_FSL_SEC_COMPAT      4
+#define CONFIG_SYS_NUM_FMAN            2
+#define CONFIG_SYS_NUM_FM1_DTSEC       7
+#define CONFIG_SYS_NUM_FM1_10GEC       1
+#define CONFIG_SYS_NUM_FM2_DTSEC       7
+#define CONFIG_SYS_NUM_FM2_10GEC       1
+#define CONFIG_NUM_DDR_CONTROLLERS     2
+#define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_7
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE       0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV       16
+#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v3.0"
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_A004468
+#define CONFIG_SYS_FSL_ERRATUM_A_004934
+#define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
+#define CONFIG_SYS_FSL_PCI_VER_3_X
+
 #elif defined(CONFIG_PPC_B4420)
 #define CONFIG_SYS_PPC64               /* 64-bit core */
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 74cc94be325a15c5e437d226fe5adff8db6d29f8..28fe1d22cb8f61e21f2f53dd54597fb85622c01e 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1830,7 +1830,7 @@ typedef struct ccsr_gur {
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT   16
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK    0x3f
-#if defined(CONFIG_PPC_T4240)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xfc000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  26
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL                0x00fe0000
@@ -1898,7 +1898,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII          0x00100000
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE         0x00180000
 #endif
-#if defined(CONFIG_PPC_T4240)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
 #define FSL_CORENET_RCWSR13_EC1                        0x60000000 /* bits 417..418 */
 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII       0x00000000
 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO               0x40000000

diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 1ecf266b467d9ac8fc16b5c59c4d982ea78f508c..5c0c438e603a35eaa0ffd627a4bc4bff1c1ecc45 100644 (file)
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1109,6 +1109,7 @@
 #define SVR_P5040      0x820400
 #define SVR_T4240      0x824000
 #define SVR_T4120      0x824001
+#define SVR_T4160      0x824100
 #define SVR_B4860      0X868000
 #define SVR_G4860      0x868001
 #define SVR_G4060      0x868003

diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index f191c79a25c26a84dc1c835795b9c4ffbff92ea0..9aaa82853579dd3b9e9ccae58b0eeb269a83ac8a 100644 (file)
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -46,6 +46,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080.o
 COBJS-$(CONFIG_PPC_P5020) += p5020.o
 COBJS-$(CONFIG_PPC_P5040) += p5040.o
 COBJS-$(CONFIG_PPC_T4240) += t4240.o
+COBJS-$(CONFIG_PPC_T4160) += t4240.o
 COBJS-$(CONFIG_PPC_B4420) += b4860.o
 COBJS-$(CONFIG_PPC_B4860) += b4860.o
 endif