powerpc/T4QDS: add two stage boot of nand/sd
authorShaohui Xie <Shaohui.Xie@freescale.com>
Tue, 22 Apr 2014 07:10:44 +0000 (15:10 +0800)
committerYork Sun <yorksun@freescale.com>
Wed, 23 Apr 2014 00:58:53 +0000 (17:58 -0700)
Add support of 2 stage NAND/SD boot loader using SPL framework.
PBL initialise the internal SRAM and copy SPL, this further
initialise DDR using SPD and environment and copy u-boot from
NAND/SD to DDR, finally SPL transfer control to u-boot.
NOR uses CS1 instead of CS2 when NAND boot, fix it.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
board/freescale/t4qds/Makefile
board/freescale/t4qds/ddr.c
board/freescale/t4qds/spl.c [new file with mode: 0644]
board/freescale/t4qds/tlb.c
boards.cfg
doc/README.t4240qds
include/configs/T4240QDS.h
include/configs/t4qds.h

index 2b1f7aa3019d313ea4448ce09d9dc6fcc2a79ba5..4e8e5cb8e9ae0168c58f05977d074b116eb65cc8 100644 (file)
@@ -4,10 +4,14 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
 obj-$(CONFIG_T4240QDS) += t4240qds.o
 obj-$(CONFIG_T4240EMU) += t4240emu.o
-obj-y  += ddr.o
 obj-$(CONFIG_T4240QDS)+= eth.o
 obj-$(CONFIG_PCI)      += pci.o
+endif
+obj-y  += ddr.o
 obj-y  += law.o
 obj-y  += tlb.o
index 7586cc3c4bda640e0e07ee786fdd6490bee8e2e4..7abd38def1af6c5751eacfa24d81dab2fd213997 100644 (file)
@@ -117,11 +117,15 @@ phys_size_t initdram(int board_type)
 
        puts("Initializing....using SPD\n");
 
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
        dram_size = fsl_ddr_sdram();
 
        dram_size = setup_ddr_tlbs(dram_size / 0x100000);
        dram_size *= 0x100000;
 
-       puts("    DDR: ");
+#else
+       /* DDR has been initialised by first stage boot loader */
+       dram_size = fsl_ddr_sdram_size();
+#endif
        return dram_size;
 }
diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c
new file mode 100644 (file)
index 0000000..0c6156e
--- /dev/null
@@ -0,0 +1,141 @@
+/* Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/spl.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include "../common/qixis.h"
+#include "t4240qds_qixis.h"
+
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK       0xFF800000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+       return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+       u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+       switch (sysclk_conf & 0x0F) {
+       case QIXIS_SYSCLK_83:
+               return 83333333;
+       case QIXIS_SYSCLK_100:
+               return 100000000;
+       case QIXIS_SYSCLK_125:
+               return 125000000;
+       case QIXIS_SYSCLK_133:
+               return 133333333;
+       case QIXIS_SYSCLK_150:
+               return 150000000;
+       case QIXIS_SYSCLK_160:
+               return 160000000;
+       case QIXIS_SYSCLK_166:
+               return 166666666;
+       }
+       return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+       u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+       switch ((ddrclk_conf & 0x30) >> 4) {
+       case QIXIS_DDRCLK_100:
+               return 100000000;
+       case QIXIS_DDRCLK_125:
+               return 125000000;
+       case QIXIS_DDRCLK_133:
+               return 133333333;
+       }
+       return 66666666;
+}
+
+void board_init_f(ulong bootflag)
+{
+       u32 plat_ratio, sys_clk, ccb_clk;
+       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#ifdef CONFIG_SPL_NAND_BOOT
+       u32 porsr1, pinctl;
+#endif
+
+#ifdef CONFIG_SPL_NAND_BOOT
+       porsr1 = in_be32(&gur->porsr1);
+       pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
+       out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
+#endif
+       /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+       memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+       /* Update GD pointer */
+       gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+       /* compiler optimization barrier needed for GCC >= 3.4 */
+       __asm__ __volatile__("" : : : "memory");
+
+       console_init_f();
+
+       /* initialize selected port with appropriate baud rate */
+       sys_clk = get_board_sys_clk();
+       plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+       ccb_clk = sys_clk * plat_ratio / 2;
+
+       NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+                    ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+       puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+       puts("\nNAND boot...\n");
+#endif
+       relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+       bd_t *bd;
+
+       bd = (bd_t *)(gd + sizeof(gd_t));
+       memset(bd, 0, sizeof(bd_t));
+       gd->bd = bd;
+       bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+       bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+       probecpu();
+       get_clocks();
+       mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+                       CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+       nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+                           (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+       mmc_initialize(bd);
+       mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+                          (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+       gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+       gd->env_valid = 1;
+
+       i2c_init_all();
+
+       gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+       mmc_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+       nand_boot();
+#endif
+}
index b701e7520938d0d98321ece92f7836af1d98fc3a..1e4d096f5f9716649a23a7eabb48f976bd10f1ef 100644 (file)
@@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
        SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
                      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
                      0, 2, BOOKE_PAGESZ_256M, 1),
-
+#ifndef CONFIG_SPL_BUILD
        /* *I*G* - PCI */
        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -105,6 +105,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 12, BOOKE_PAGESZ_16M, 1),
 #endif
+#endif
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
        SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -136,6 +137,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      0, 18, BOOKE_PAGESZ_1M, 1),
 #endif
 
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 19, BOOKE_PAGESZ_2G, 1)
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
index 7f91210f6f19b15af3c04f2f671d433d09bb1a9e..ad34aa72cb585fca7fe02ff86e9e2c2a49ae4c2d 100644 (file)
@@ -971,13 +971,14 @@ Active  powerpc     mpc85xx        -           freescale       t208xrdb
 Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SRIO_PCIE_BOOT              T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS                             T4240QDS:PPC_T4160                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SECURE_BOOT                 T4240QDS:PPC_T4160,SECURE_BOOT                                                                                                    Aneesh Bansal <aneesh.bansal@freescale.com>
-Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SDCARD                      T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
+Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_NAND                        T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND                                                                    -
+Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SDCARD                      T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD                                                                    -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SPIFLASH                    T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4240EMU                             T4240EMU:PPC_T4240                                                                                                                York Sun <yorksun@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS                             T4240QDS:PPC_T4240                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_SECURE_BOOT                 T4240QDS:PPC_T4240,SECURE_BOOT                                                                                                    Aneesh Bansal <aneesh.bansal@freescale.com>
-Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_NAND                        T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
-Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_SDCARD                      T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
+Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_NAND                       T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND                                                                      -
+Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_SDCARD                      T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD                                                                    -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_SPIFLASH                    T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4240QDS_SRIO_PCIE_BOOT              T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       qemu-ppce500        qemu-ppce500                         -                                                                                                                                 Alexander Graf <agraf@suse.de>
index a9841fb5f74c76f558141041cee35cb8c731d171..ef8c75f3b2c853e219649fb6acb42079a72b04cd 100644 (file)
@@ -120,3 +120,56 @@ The override voltage takes effect when booting.
 Note: voltage adjustment needs to be done step by step. Changing voltage too
 rapidly may cause current surge. The voltage stepping is done by software.
 Users can set the final voltage directly.
+
+2-stage NAND/SD boot loader
+-------------------------------
+PBL initializes the internal SRAM and copy SPL(160K) in SRAM.
+SPL further initialise DDR using SPD and environment variables
+and copy u-boot(768 KB) from NAND/SD device to DDR.
+Finally SPL transers control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area          | Address                       |
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000        (32KB)          |
+-------------------------------------------------
+|GD, BD                | 0xFFFC8000    (4KB)           |
+-------------------------------------------------
+|ENV           | 0xFFFC9000    (8KB)           |
+-------------------------------------------------
+|HEAP          | 0xFFFCB000    (50KB)          |
+-------------------------------------------------
+|STACK         | 0xFFFD8000    (22KB)          |
+-------------------------------------------------
+|U-boot SPL    | 0xFFFD8000    (160KB)         |
+-------------------------------------------------
+
+NAND Flash memory Map on T4QDS
+--------------------------------------------------------------
+Start          End             Definition      Size
+0x000000       0x0FFFFF        u-boot img      1MB
+0x140000       0x15FFFF        u-boot env      128KB
+0x160000       0x17FFFF        FMAN Ucode      128KB
+
+Micro SD Card memory Map on T4QDS
+----------------------------------------------------
+Block          #blocks         Definition      Size
+0x008          2048            u-boot img      1MB
+0x800          0016            u-boot env      8KB
+0x820          0128            FMAN ucode      64KB
+
+Switch Settings: (ON is 1, OFF is 0)
+===============
+NAND boot SW setting:
+SW1[1:8] = 10000010
+SW2[1.1] = 0
+SW6[1:4] = 1001
+
+SD boot SW setting:
+SW1[1:8] = 00100000
+SW2[1.1] = 0
index 1b98cfda3eca732696e4034c2bda8d1d5f50ea69..e4eb30fbeb5d217d1fc19f53f2a4d9a8fa12a283 100644 (file)
 #define CONFIG_ICS307_REFCLK_HZ                25000000  /* ICS307 ref clk freq */
 
 #ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE       CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS    0xfffffffc
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg
+#if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
+#define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
+#else
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE           0x00201000
+#define CONFIG_SPL_TEXT_BASE           0xFFFD8000
+#define CONFIG_SPL_PAD_TO              0x40000
+#define CONFIG_SPL_MAX_SIZE            0x28000
+#define RESET_VECTOR_OFFSET            0x27FFC
+#define BOOT_PAGE_OFFSET               0x27000
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE    (768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST     0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START   0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    (256 << 10)
+#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#endif
+
+#ifdef CONFIG_SDCARD
+#define        CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST      0x00200000
+#define CONFIG_SYS_MMC_U_BOOT_START    0x00200000
+#define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
+#ifndef CONFIG_SPL_BUILD
+#define        CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+
 #endif
+#endif /* CONFIG_RAMBOOT_PBL */
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV          0
 #define CONFIG_ENV_SIZE                        0x2000
-#define CONFIG_ENV_OFFSET              (512 * 1658)
+#define CONFIG_ENV_OFFSET              (512 * 0x800)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE                        CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET              (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_SIZE                        0x2000
+#define CONFIG_ENV_OFFSET              (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_IS_IN_REMOTE
 #define CONFIG_ENV_ADDR                0xffe20000
@@ -244,8 +297,16 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS0_FTIM1           CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS0_FTIM2           CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS0_FTIM3           CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT           CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2               CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_CSPR1_EXT           CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1               CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1              CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1               CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0           CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1           CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2           CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3           CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT           CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2               CONFIG_SYS_NOR1_CSPR
 #define CONFIG_SYS_AMASK2              CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR2               CONFIG_SYS_NOR_CSOR
 #define CONFIG_SYS_CS2_FTIM0           CONFIG_SYS_NOR_FTIM0
@@ -261,6 +322,14 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS0_FTIM1           CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2           CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3           CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT           CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1               CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1              CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1               CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0           CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1           CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2           CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3           CONFIG_SYS_NOR_FTIM3
 #define CONFIG_SYS_CSPR2_EXT           CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR2               CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK2              CONFIG_SYS_NAND_AMASK
@@ -270,14 +339,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS2_FTIM2           CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3           CONFIG_SYS_NAND_FTIM3
 #endif
-#define CONFIG_SYS_CSPR1_EXT           CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR1               CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1              CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1               CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0           CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1           CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2           CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3           CONFIG_SYS_NOR_FTIM3
 
 #if defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_SYS_RAMBOOT
@@ -379,14 +440,14 @@ unsigned long get_board_ddr_clk(void);
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_FMAN_FW_ADDR        (512 * 1680)
+#define CONFIG_SYS_FMAN_FW_ADDR        (512 * 0x820)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_FMAN_FW_ADDR        (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR        (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
index f8de43943d75e1604b8c23e4be6e8f5e3ef52797..36bc5294ef4df7b107e521100e5721f32db99f70 100644 (file)
 /*
  *  Config the L3 Cache as L3 SRAM
  */
-#define CONFIG_SYS_INIT_L3_ADDR                CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR                0xFFFC0000
+#define CONFIG_SYS_L3_SIZE             (512 << 10)
+#define CONFIG_SPL_GD_ADDR             (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR                        (CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR   (CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE   (50 << 10)
+#define CONFIG_SPL_RELOC_STACK         (CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE    (22 << 10)
 
 #define CONFIG_SYS_DCSRBAR             0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS                0xf00000000ull
 #define CONFIG_SYS_FLASH_BASE_PHYS     (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 
 
-#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE        CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE    /* start of monitor */
+#endif
 
 #define CONFIG_BOARD_EARLY_INIT_R      /* call board_early_init_r function */
 #define CONFIG_MISC_INIT_R