Some changes of TLB entry setting for MPC8572DS
authorHaiying Wang <Haiying.Wang@freescale.com>
Tue, 13 Jan 2009 21:29:28 +0000 (16:29 -0500)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Tue, 13 Jan 2009 22:58:46 +0000 (16:58 -0600)
- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)

- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
board/freescale/mpc8572ds/tlb.c
include/configs/MPC8572DS.h

index 8d1f646fac7f94355e6b99e92461e34f9038d98c..829896ac0604ef1d7683a3bb7f1ba7971dce5584 100644 (file)
@@ -41,10 +41,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
                      0, 0, BOOKE_PAGESZ_4K, 0),
 
-       SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE,
-                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 0, BOOKE_PAGESZ_4K, 0),
-
        /* TLB 1 */
        /* *I*** - Covers boot page */
        SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
@@ -86,6 +82,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 7, BOOKE_PAGESZ_1M, 1),
 
+       SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 8, BOOKE_PAGESZ_4K, 1),
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
index 37c3f4200be5836907ea880ce9d74a3dc500d08a..6c7a364545ce7a113bb9aeee27fe09869c607e35 100644 (file)
@@ -92,6 +92,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
 
 /* DDR Setup */
+#define CONFIG_SYS_DDR_TLB_START 9
 #define CONFIG_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for DDR setup */