ifneq ($(CONFIG_LS1012A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
endif
+
+ifneq ($(CONFIG_LS1046A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
+endif
1. LS1043A
2. LS2080A
3. LS1012A
+ 4. LS1046A
LS1043A
---------
- Two WatchDog timers
- ARM generic timer
- QorIQ platform's trust architecture 2.1
+
+LS1046A
+--------
+The LS1046A integrated multicore processor combines four ARM Cortex-A72
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1046A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A72 CPUs
+ - 2 MB unified L2 Cache
+ - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
+ support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+ the following functions:
+ - Packet parsing, classification, and distribution (FMan)
+ - Queue management for scheduling, packet sequencing, and congestion
+ management (QMan)
+ - Hardware buffer management for buffer allocation and de-allocation (BMan)
+ - Cryptography acceleration (SEC)
+ - Two Configurable x4 SerDes
+ - Two PLLs per four-lane SerDes
+ - Support for 10G operation
+ - Ethernet interfaces by FMan
+ - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
+ - Up to 1 x QSGMII (MAC 5, 6, 10, 1)
+ - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
+ - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
+ - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4)
+ - High-speed peripheral interfaces
+ - Three PCIe 3.0 controllers, one supporting x4 operation
+ - One serial ATA (SATA 3.0) controllers
+ - Additional peripheral interfaces
+ - Three high-speed USB 3.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (eSDXC/eMMC)
+ - Quad Serial Peripheral Interface (QSPI) Controller
+ - Serial peripheral interface (SPI) controller
+ - Four I2C controllers
+ - Two DUARTs
+ - Integrated flash controller (IFC) supporting NAND and NOR flash
+ - QorIQ platform's trust architecture 2.1
case 3:
sys_info->freq_fman[0] = freq_c_pll[0] / 3;
break;
+ case 4:
+ sys_info->freq_fman[0] = freq_c_pll[0] / 4;
+ break;
+ case 5:
+ sys_info->freq_fman[0] = sys_info->freq_systembus;
+ break;
case 6:
sys_info->freq_fman[0] = freq_c_pll[1] / 2;
break;
#ifdef CONFIG_FSL_ESDHC
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
rcw_tmp = in_be32(&gur->rcwsr[15]);
- rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
- sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
+ switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
+ case 1:
+ sys_info->freq_sdhc = freq_c_pll[1];
+ break;
+ case 2:
+ sys_info->freq_sdhc = freq_c_pll[1] / 2;
+ break;
+ case 3:
+ sys_info->freq_sdhc = freq_c_pll[1] / 3;
+ break;
+ case 6:
+ sys_info->freq_sdhc = freq_c_pll[0] / 2;
+ break;
+ default:
+ printf("Error: Unknown ESDHC clock select!\n");
+ break;
+ }
#else
sys_info->freq_sdhc = sys_info->freq_systembus;
#endif
--- /dev/null
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/immap_lsch2.h>
+
+struct serdes_config {
+ u32 protocol;
+ u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6} },
+ {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6} },
+ {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6} },
+ {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6} },
+ {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE} },
+ {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE} },
+ {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6} },
+ {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1,
+ SGMII_FM1_DTSEC6} },
+ {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1,
+ SGMII_FM1_DTSEC6} },
+ {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
+ SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {}
+};
+
+static struct serdes_config serdes2_cfg_tbl[] = {
+ /* SerDes 2 */
+ {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1} },
+ {0x5559, {PCIE1, PCIE2, PCIE3, SATA1} },
+ {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3} },
+ {0x5506, {PCIE1, PCIE2, NONE, PCIE3} },
+ {0x0506, {NONE, PCIE2, NONE, PCIE3} },
+ {0x0559, {NONE, PCIE2, PCIE3, SATA1} },
+ {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA1} },
+ {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3} },
+ {}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+ serdes1_cfg_tbl,
+ serdes2_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == cfg)
+ return ptr->lanes[lane];
+ ptr++;
+ }
+
+ return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+ int i;
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == prtcl)
+ break;
+ ptr++;
+ }
+
+ if (!ptr->protocol)
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (ptr->lanes[i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
+#elif defined(CONFIG_LS1046A)
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 8
+#define CONFIG_SYS_NUM_FM1_10GEC 2
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
+#define CONFIG_SYS_FSL_DDR_BE
+#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_SFP_VER_3_2
+#define CONFIG_SYS_FSL_SNVS_LE
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SRK_LE
+#define CONFIG_KEY_REVOCATION
+
+/* SMMU Defintions */
+#define SMMU_BASE 0x09000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0x01410000
+#define GICC_BASE 0x01420000
+
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined
#endif
CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
+ CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
+ CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
};
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
-#ifdef CONFIG_LS1043A
+#ifdef CONFIG_FSL_LSCH2
const char *serdes_clock_to_string(u32 clock);
int get_serdes_protocol(void);
#endif
#define SVR_LS1012A 0x870400
#define SVR_LS1043A 0x879200
#define SVR_LS1023A 0x879208
+#define SVR_LS1046A 0x870700
+#define SVR_LS1026A 0x870708
#define SVR_LS2045A 0x870120
#define SVR_LS2080A 0x870110
#define SVR_LS2085A 0x870100
projects / oweals / u-boot.git / commitdiff