ls102xa: dcu: Add platform support for DCU on LS1021ATWR board
authorWang Huan <b18965@freescale.com>
Fri, 5 Sep 2014 05:52:50 +0000 (13:52 +0800)
committerYork Sun <yorksun@freescale.com>
Mon, 8 Sep 2014 17:30:36 +0000 (10:30 -0700)
This patch adds the TWR_LCD_RGB card/HDMI options and the common
configuration for DCU on LS1021ATWR board.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
board/freescale/ls1021atwr/Makefile
board/freescale/ls1021atwr/dcu.c [new file with mode: 0644]
board/freescale/ls1021atwr/ls1021atwr.c
include/configs/ls1021atwr.h

index b5df668713f2eace9366b3150139e09a09a9da1d..01296c04b2931e60d044daf8631fe4df4399820c 100644 (file)
@@ -5,3 +5,4 @@
 #
 
 obj-y += ls1021atwr.o
+obj-$(CONFIG_FSL_DCU_FB) += dcu.o
diff --git a/board/freescale/ls1021atwr/dcu.c b/board/freescale/ls1021atwr/dcu.c
new file mode 100644 (file)
index 0000000..8fe4ccb
--- /dev/null
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include "div64.h"
+#include "../common/dcu_sii9022a.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+       unsigned long long div;
+
+       div = (unsigned long long)(gd->bus_clk / 1000);
+       div *= (unsigned long long)pixclock;
+       do_div(div, 1000000000);
+
+       return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+                     const char *port,
+                     struct fb_videomode *dcu_fb_videomode)
+{
+       const char *name;
+       unsigned int pixel_format;
+
+       if (strncmp(port, "twr_lcd", 4) == 0) {
+               name = "TWR_LCD_RGB card";
+       } else {
+               name = "HDMI";
+               dcu_set_dvi_encoder(dcu_fb_videomode);
+       }
+
+       printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
+
+       pixel_format = 32;
+       fsl_dcu_init(xres, yres, pixel_format);
+
+       return 0;
+}
index 92ad8cd9bd3fcc7290607fac84ea4644a6c2ab99..b522ff28e5eb8e7c87ffd6c10430beaa5798669b 100644 (file)
@@ -261,6 +261,12 @@ int board_early_init_f(void)
        init_early_memctl_regs();
 #endif
 
+#ifdef CONFIG_FSL_DCU_FB
+       out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
+       out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
+       out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
+#endif
+
        return 0;
 }
 
index cb6b4004250e01e06caf80f477afbc4faa479372..45b2272ff5bf6f7f390ee6935bc5908b402369eb 100644 (file)
 #define CONFIG_FSL_ESDHC
 #define CONFIG_GENERIC_MMC
 
+/*
+ * Video
+ */
+#define CONFIG_FSL_DCU_FB
+
+#ifdef CONFIG_FSL_DCU_FB
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+
+#define CONFIG_FSL_DCU_SII9022A
+#define CONFIG_SYS_I2C_DVI_BUS_NUM     1
+#define CONFIG_SYS_I2C_DVI_ADDR                0x39
+#endif
+
 /*
  * eTSEC
  */