imx: mx6q DDR3 init: Fix MR0.PPD

MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which
is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>

diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 51f8c359a5fe9558564e003380b3af336ba89990..d50858d1b79a9556c021d9137919a6b2f321e05c 100644 (file)
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -126,8 +126,8 @@ DATA 4 0x021b001c 0x00008033
 DATA 4 0x021b001c 0x0000803B
 DATA 4 0x021b001c 0x00428031
 DATA 4 0x021b001c 0x00428039
-DATA 4 0x021b001c 0x09408030
-DATA 4 0x021b001c 0x09408038
+DATA 4 0x021b001c 0x19408030
+DATA 4 0x021b001c 0x19408038
 
 DATA 4 0x021b001c 0x04008040
 DATA 4 0x021b001c 0x04008048