x86: Switch to use DM sysreset driver

This converts all x86 boards over to DM sysreset.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

diff --git a/arch/Kconfig b/arch/Kconfig
index dd5a8870017f458d8309194bff1c9623631eb4ca..cbeb9f67348f0b4602d7a22a2bca07332719d52c 100644 (file)
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -118,6 +118,8 @@ config X86
        imply DM_SPI_FLASH
        imply DM_USB
        imply DM_VIDEO
+       imply SYSRESET
+       imply SYSRESET_X86
        imply CMD_FPGA_LOADMK
        imply CMD_GETTIME
        imply CMD_IO

diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
index b7d481ac56c1d64fbfe5288d855917bcf66b8927..8882a76eae596f4c00cd7cf4858e6dce26709e95 100644 (file)
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -55,9 +55,3 @@ int arch_misc_init(void)
 
        return 0;
 }
-
-void reset_cpu(ulong addr)
-{
-       /* cold reset */
-       x86_full_reset();
-}

diff --git a/arch/x86/cpu/braswell/braswell.c b/arch/x86/cpu/braswell/braswell.c
index 32a6a5e5a8c5f45ea8a3ac3d6a1f7d53099c3676..7a83b0600580be66b6a6f2f2ce862bfbf808cd1f 100644 (file)
--- a/arch/x86/cpu/braswell/braswell.c
+++ b/arch/x86/cpu/braswell/braswell.c
@@ -27,9 +27,3 @@ int arch_misc_init(void)
 
        return 0;
 }
-
-void reset_cpu(ulong addr)
-{
-       /* cold reset */
-       x86_full_reset();
-}

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 6aefa12a7c52541e18df8e9aa0094df5adc1417a..37615d055a4d921282dd0b2bdd34233c9f049cec 100644 (file)
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -75,37 +75,11 @@ int x86_init_cache(void)
 }
 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
 
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-       printf("resetting ...\n");
-
-       /* wait 50 ms */
-       udelay(50000);
-       disable_interrupts();
-       reset_cpu(0);
-
-       /*NOTREACHED*/
-       return 0;
-}
-
 void  flush_cache(unsigned long dummy1, unsigned long dummy2)
 {
        asm("wbinvd\n");
 }
 
-__weak void reset_cpu(ulong addr)
-{
-       /* Do a hard reset through the chipset's reset control register */
-       outb(SYS_RST | RST_CPU, IO_PORT_RESET);
-       for (;;)
-               cpu_hlt();
-}
-
-void x86_full_reset(void)
-{
-       outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
-}
-
 /* Define these functions to allow ehch-hcd to function */
 void flush_dcache_range(unsigned long start, unsigned long stop)
 {

diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c
index 1a15229196fa03de0f3d02357e6facabe54a5fa4..219d5be39957a3d11802264a44f34c30f3ddb049 100644 (file)
--- a/arch/x86/cpu/ivybridge/early_me.c
+++ b/arch/x86/cpu/ivybridge/early_me.c
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
+#include <sysreset.h>
 #include <asm/pci.h>
 #include <asm/cpu.h>
 #include <asm/processor.h>
@@ -138,17 +139,17 @@ int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
        case ME_HFS_ACK_RESET:
                /* Non-power cycle reset */
                set_global_reset(dev, 0);
-               reset_cpu(0);
+               sysreset_walk_halt(SYSRESET_COLD);
                break;
        case ME_HFS_ACK_PWR_CYCLE:
                /* Power cycle reset */
                set_global_reset(dev, 0);
-               x86_full_reset();
+               sysreset_walk_halt(SYSRESET_COLD);
                break;
        case ME_HFS_ACK_GBL_RESET:
                /* Global reset */
                set_global_reset(dev, 1);
-               x86_full_reset();
+               sysreset_walk_halt(SYSRESET_COLD);
                break;
        case ME_HFS_ACK_S3:
        case ME_HFS_ACK_S4:

diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 2f253e813e6476188a8f5cfa34833a488a2521d6..8a58d0383d506e29f12773a6766fe3d998804df0 100644 (file)
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -18,6 +18,7 @@
 #include <spi.h>
 #include <spi_flash.h>
 #include <syscon.h>
+#include <sysreset.h>
 #include <asm/cpu.h>
 #include <asm/processor.h>
 #include <asm/gpio.h>
@@ -497,7 +498,7 @@ int dram_init(void)
        /* If MRC data is not found we cannot continue S3 resume. */
        if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
                debug("Giving up in sdram_initialize: No MRC data\n");
-               reset_cpu(0);
+               sysreset_walk_halt(SYSRESET_COLD);
        }
 
        /* Pass console handler in pei_data */

diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index ca4b3f083356ada9e3e2ff41fbe7d54350986699..5e8b4f068e1f5ecdc3dfb5d52ec791e8f40f619d 100644 (file)
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -156,12 +156,6 @@ int print_cpuinfo(void)
 }
 #endif
 
-void reset_cpu(ulong addr)
-{
-       /* cold reset */
-       x86_full_reset();
-}
-
 int arch_early_init_r(void)
 {
        qemu_chipset_init();

diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 4fd686424d95f4e92e9f2919858f0cc1f42bf3f2..d39edb2271b2d3d3baa0239cff0c786aed94a865 100644 (file)
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -270,12 +270,6 @@ int print_cpuinfo(void)
        return default_print_cpuinfo();
 }
 
-void reset_cpu(ulong addr)
-{
-       /* cold reset */
-       x86_full_reset();
-}
-
 static void quark_pcie_init(void)
 {
        u32 val;

diff --git a/arch/x86/cpu/tangier/tangier.c b/arch/x86/cpu/tangier/tangier.c
index 0a15e64344f0e7361ab0536be0fda458c17fce98..df2c600be334bbe2109f8fb0a7e6e88867f9908e 100644 (file)
--- a/arch/x86/cpu/tangier/tangier.c
+++ b/arch/x86/cpu/tangier/tangier.c
@@ -4,7 +4,6 @@
  */
 
 #include <common.h>
-#include <asm/scu.h>
 #include <asm/u-boot-x86.h>
 
 /*
@@ -24,8 +23,3 @@ int print_cpuinfo(void)
 {
        return default_print_cpuinfo();
 }
-
-void reset_cpu(ulong addr)
-{
-       scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
-}

diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 74291a8f0955d0ef3d779adb80372964c5122dce..9683c525a7fae746bdbc18b149f2b5c1f063f39b 100644 (file)
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -12,6 +12,7 @@
 /include/ "skeleton.dtsi"
 /include/ "keyboard.dtsi"
 /include/ "serial.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 /include/ "coreboot_fb.dtsi"

diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
index 36e6069b19d968d8acb8b47dc6f074ab19d81bd1..4e8a761ce87a1bfd3c6009fd32e6bc0c014a7876 100644 (file)
--- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts
+++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
@@ -12,6 +12,7 @@
 
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 

diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts
index 39661990853b32bea83095b2383cc9bdf602141b..ec691f136a7fcd7b215fdfacf6d1816cfa6084a8 100644 (file)
--- a/arch/x86/dts/broadwell_som-6896.dts
+++ b/arch/x86/dts/broadwell_som-6896.dts
@@ -2,6 +2,7 @@
 
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 /include/ "coreboot_fb.dtsi"

diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts
index 3e29683bd92dd29ca8993626991efea52001e488..39e2d2fa4b222feb43194b31b296edb90b5c84d0 100644 (file)
--- a/arch/x86/dts/cherryhill.dts
+++ b/arch/x86/dts/cherryhill.dts
@@ -10,6 +10,7 @@
 
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 26b9f85a5dae6a4c2e80d1bb1f8891df969b3f94..115a088a7afeed0ab6ef2847323fa556984d5f64 100644 (file)
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -5,6 +5,7 @@
 /include/ "skeleton.dtsi"
 /include/ "keyboard.dtsi"
 /include/ "serial.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 /include/ "coreboot_fb.dtsi"

diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
index 52a9ea66225a67a9077a46cfbf1fee67d3fa7326..9c48c9a3fa73cdd0f21a67ef529e9ab22da72235 100644 (file)
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -5,6 +5,7 @@
 /include/ "skeleton.dtsi"
 /include/ "keyboard.dtsi"
 /include/ "serial.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 /include/ "coreboot_fb.dtsi"

diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
index b25c9194f357b792cfd7772ec4f6178427f8622b..a72a85ef9c4242b0079c5b556671d5bfa332aa6b 100644 (file)
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -2,6 +2,7 @@
 
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 /include/ "coreboot_fb.dtsi"

diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index c3d15143cf45eea777799299f4730411d4b7dd25..5884dbc277d36e0507105d287e8d8d7dfaac4a05 100644 (file)
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -12,6 +12,7 @@
 
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 

diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts
index c1cda73d963a3987a6fedc26c9c2246270af526f..9801790083f9a9d54ef0c680d367ffacf70e4d1e 100644 (file)
--- a/arch/x86/dts/cougarcanyon2.dts
+++ b/arch/x86/dts/cougarcanyon2.dts
@@ -10,6 +10,7 @@
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
 /include/ "keyboard.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 

diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index d8faa9d5046dd4d42a0c93d735146682b008df20..2ffcc5f27eceaec5bb24bc9e1917cb6f34ab68b3 100644 (file)
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -10,6 +10,7 @@
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
 /include/ "keyboard.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 

diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi
index cb96fdf7e7b96f638ec90bf301e8723cc9274709..51d33e772fc8da8bee59b6127b32aeae7a5c50cf 100644 (file)
--- a/arch/x86/dts/dfi-bt700.dtsi
+++ b/arch/x86/dts/dfi-bt700.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/interrupt-router/intel-irq.h>
 
 #include "skeleton.dtsi"
+#include "reset.dtsi"
 #include "rtc.dtsi"
 #include "tsc_timer.dtsi"
 

diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts
index 903353229434d07e8b2586d466ec64459772b091..5c80f5c7fabea0e8fd4348bc8d55d89bb9183b5c 100644 (file)
--- a/arch/x86/dts/edison.dts
+++ b/arch/x86/dts/edison.dts
@@ -85,4 +85,9 @@
                compatible = "intel,scu-ipc";
                reg = <0xff009000 0x1000>;
        };
+
+       reset {
+               compatible = "intel,reset-tangier";
+               u-boot,dm-pre-reloc;
+       };
 };

diff --git a/arch/x86/dts/efi-x86_app.dts b/arch/x86/dts/efi-x86_app.dts
index e70e3516180d9d0421953b017c76101628c8b502..20150f6ede4e8e6881ff4be4614a61b736955fa8 100644 (file)
--- a/arch/x86/dts/efi-x86_app.dts
+++ b/arch/x86/dts/efi-x86_app.dts
@@ -23,4 +23,9 @@
        serial: serial {
                compatible = "efi,uart";
        };
+
+       reset {
+               compatible = "efi,reset";
+               u-boot,dm-pre-reloc;
+       };
 };

diff --git a/arch/x86/dts/efi-x86_payload.dts b/arch/x86/dts/efi-x86_payload.dts
index 148b5871aa2622b0ac2adcc233f8ed3b80964406..19f253064bca6a2f9299218707f2dc925a43aa8c 100644 (file)
--- a/arch/x86/dts/efi-x86_payload.dts
+++ b/arch/x86/dts/efi-x86_payload.dts
@@ -10,6 +10,7 @@
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
 /include/ "keyboard.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 

diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 3454abdd33cd5f997deb614ac50055119a21d931..3a5d168268d43e08dba0f7d5899898183e3ad3ef 100644 (file)
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -9,6 +9,7 @@
 #include <dt-bindings/interrupt-router/intel-irq.h>
 
 /include/ "skeleton.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 

diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 42ba0c7714064ad26b64b0a10dd36b281ff76e4a..02ab4c160ae230977bde714a858b0da067982ccd 100644 (file)
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -11,6 +11,7 @@
 
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 /include/ "coreboot_fb.dtsi"

diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
index 6565429867e949cf397a3d669633b1240361e548..2e5210d4ee6bf46601f3f5260ae8117a801e456e 100644 (file)
--- a/arch/x86/dts/qemu-x86_i440fx.dts
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -10,6 +10,7 @@
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
 /include/ "keyboard.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 

diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index f1c4cb9c037766b1663525946b76a06291fa08e2..e8f55b19a26291b5e51ebc70fbcd655fe0fd1693 100644 (file)
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -20,6 +20,7 @@
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
 /include/ "keyboard.dtsi"
+/include/ "reset.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 

diff --git a/arch/x86/dts/reset.dtsi b/arch/x86/dts/reset.dtsi
new file mode 100644 (file)
index 0000000..f979d83
--- /dev/null
+++ b/arch/x86/dts/reset.dtsi
@@ -0,0 +1,6 @@
+/ {
+       reset {
+               compatible = "x86,reset";
+               u-boot,dm-pre-reloc;
+       };
+};

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index dd957d2c1bb8b230e22640c7682cc6b41bf5365f..f1d9977bcb33218c2437f27840c8fe968968507d 100644 (file)
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -43,11 +43,6 @@ enum {
        FULL_RST        = 1 << 3,       /* full power cycle */
 };
 
-/**
- * x86_full_reset() - reset everything: perform a full power cycle
- */
-void x86_full_reset(void);
-
 static inline __attribute__((always_inline)) void cpu_hlt(void)
 {
        asm("hlt");

diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 2340ef83323d11a8fd4f7b6dab159acb10078915..670fcdc0093b5d7a2f56065d586dc405ec625443 100644 (file)
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -40,7 +40,6 @@ int x86_cleanup_before_linux(void);
 void x86_enable_caches(void);
 void x86_disable_caches(void);
 int x86_init_cache(void);
-void reset_cpu(ulong addr);
 ulong board_get_usable_ram_top(ulong total_size);
 int default_print_cpuinfo(void);
 

diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
index 59b6bd0dd1ee0ee044e01faee8f65de77ecad28c..9af2c4de8d7a2585a9fb84dc76fd0b7a329214d9 100644 (file)
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig
@@ -4,6 +4,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200