ARM64: zynqmp: Added clocks to DT
authorVNSL Durga <vnsl.durga.challa@xilinx.com>
Thu, 24 Mar 2016 17:15:12 +0000 (22:45 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Wed, 13 Apr 2016 16:29:04 +0000 (18:29 +0200)
ZynqMP DMA's main clock and apb clock are added
in zynqmp DT.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
arch/arm/dts/zynqmp.dtsi

index 48505fa6daff3d12ba1da74b37b8f3fa90ab6231..45209309c054bd0bc7b883d1c9e1656970bd5d74 100644 (file)
                        reg = <0x0 0xfd500000 0x1000>;
                        interrupt-parent = <&gic>;
                        interrupts = <0 124 4>;
+                       clock-names = "clk_main", "clk_apb";
                        xlnx,id = <0>;
                        xlnx,bus-width = <128>;
                        power-domains = <&pd_gdma>;
                        reg = <0x0 0xfd510000 0x1000>;
                        interrupt-parent = <&gic>;
                        interrupts = <0 125 4>;
+                       clock-names = "clk_main", "clk_apb";
                        xlnx,id = <1>;
                        xlnx,bus-width = <128>;
                        power-domains = <&pd_gdma>;
                        reg = <0x0 0xfd520000 0x1000>;
                        interrupt-parent = <&gic>;
                        interrupts = <0 126 4>;
+                       clock-names = "clk_main", "clk_apb";
                        xlnx,id = <2>;
                        xlnx,bus-width = <128>;
                        power-domains = <&pd_gdma>;
                        reg = <0x0 0xfd530000 0x1000>;
                        interrupt-parent = <&gic>;
                        interrupts = <0 127 4>;
+                       clock-names = "clk_main", "clk_apb";
                        xlnx,id = <3>;
                        xlnx,bus-width = <128>;
                        power-domains = <&pd_gdma>;
                        reg = <0x0 0xfd540000 0x1000>;
                        interrupt-parent = <&gic>;
                        interrupts = <0 128 4>;
+                       clock-names = "clk_main", "clk_apb";
                        xlnx,id = <4>;
                        xlnx,bus-width = <128>;
                        power-domains = <&pd_gdma>;
                        reg = <0x0 0xfd550000 0x1000>;
                        interrupt-parent = <&gic>;
                        interrupts = <0 129 4>;
+                       clock-names = "clk_main", "clk_apb";
                        xlnx,id = <5>;
                        xlnx,bus-width = <128>;
                        power-domains = <&pd_gdma>;
                        reg = <0x0 0xfd560000 0x1000>;
                        interrupt-parent = <&gic>;
                        interrupts = <0 130 4>;
+                       clock-names = "clk_main", "clk_apb";
                        xlnx,id = <6>;
                        xlnx,bus-width = <128>;
                        power-domains = <&pd_gdma>;
                        reg = <0x0 0xfd570000 0x1000>;
                        interrupt-parent = <&gic>;
                        interrupts = <0 131 4>;
+                       clock-names = "clk_main", "clk_apb";
                        xlnx,id = <7>;
                        xlnx,bus-width = <128>;
                        power-domains = <&pd_gdma>;