mpc83xx: add ELBC NAND support for the MPC837XEMDS boards

Though NAND chip is replaceable on the MPC837XE-MDS boards, the
current settings don't work with the default chip on the board.
Nevertheless Freescale's U-Boot sets the option register correctly,
so I just dumped the register from the working u-boot. My guess is
that the old settings were applicable for some pilot boards, not
found in the production.

This patch also enables FSL ELBC driver so that we could access
the NAND storage in the u-boot.

The NAND support costs about 45KB, so the u-boot no longer fits
into two 128KB NOR flash sectors, thus we also have to adjust
environment location: add another 128KB to the monitor length.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
It is due to hardware design and logic defect, that is the
I/O[0:7] of NAND chip is connected to LAD[7:0], so when
the NAND chip connected to nLCS3,  you have to set up the
OR3[BCTLD] = '1' for normal operation, otherwise it will have
bus contention due to the pin 48/25 of U60 is enabled.

Setup the OR3[BCTLD] = '1' , that meaning the LBCTL is not
asserted upon access to the NAND chip, keep the default state.

Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index c3431ee4cce7954a6e1775483e8fc78d05371d8c..1e46ce23c76aae9c0de61332d0a230e7b212efa4 100644 (file)
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -204,7 +204,7 @@
 #endif
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN         (384 * 1024) /* Reserve 384 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN          (512 * 1024) /* Reserved for malloc */
 
 /*
@@ -268,6 +268,12 @@
 /*
  * NAND Flash on the Local Bus
  */
+#define CONFIG_CMD_NAND                1
+#define CONFIG_MTD_NAND_VERIFY_WRITE   1
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define NAND_MAX_CHIPS         1
+#define CONFIG_NAND_FSL_ELBC   1
+
 #define CONFIG_SYS_NAND_BASE           0xE0600000      /* 0xE0600000 */
 #define CONFIG_SYS_BR3_PRELIM          ( CONFIG_SYS_NAND_BASE \
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
@@ -275,13 +281,14 @@
                                | BR_MS_FCM             /* MSEL = FCM */ \
                                | BR_V )                /* valid */
 #define CONFIG_SYS_OR3_PRELIM          ( 0xFFFF8000            /* length 32K */ \
-                               | OR_FCM_CSCT \
+                               | OR_FCM_BCTLD \
                                | OR_FCM_CST \
                                | OR_FCM_CHT \
                                | OR_FCM_SCY_1 \
+                               | OR_FCM_RST \
                                | OR_FCM_TRLX \
                                | OR_FCM_EHTR )
-                               /* 0xFFFF8396 */
+                               /* 0xFFFF919E */
 
 #define CONFIG_SYS_LBLAWBAR3_PRELIM    CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_LBLAWAR3_PRELIM     0x8000000E      /* 32KB  */