Add bit fields definitions for RST_RESET register in QC/A common register definition...

diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h
index e6a20af82f6a3fda3bfd30c70fb608b352a5f060..aed2120004ad9a232675571b9324c9354de20315 100644 (file)
--- a/u-boot/include/soc/qca_soc_common.h
+++ b/u-boot/include/soc/qca_soc_common.h
@@ -567,8 +567,8 @@
 #define QCA_PLL_PLL_DITHER_DITHER_EN_MASK                                      (1 << QCA_PLL_PLL_DITHER_DITHER_EN_SHIFT)
 
 /* ETHSW_CLOCK_CONTROL register (Ethernet switch clock control, AR933x only) */
-#define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLL_PWD_SHIFT                      3
-#define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLL_PWD_MASK                       (1 << QCA_PLL_ETHSW_CLK_CTRL_CORE_PLL_PWD_SHIFT)
+#define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT                       3
+#define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_MASK                                (1 << QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT)
 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT                      4
 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_MASK                       (1 << QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT)
 
@@ -605,8 +605,8 @@
 #define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_MASK                                    (1 << QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT)
 #define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT                          2
 #define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_MASK                           (1 << QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT)
-#define QCA_PLL_WLAN_CLK_CTRL_PLL_PWD_CTL_SHIFT                                3
-#define QCA_PLL_WLAN_CLK_CTRL_PLL_PWD_CTL_MASK                         (1 << QCA_PLL_WLAN_CLK_CTRL_PLL_PWD_CTL_SHIFT)
+#define QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_SHIFT                         3
+#define QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_MASK                          (1 << QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_SHIFT)
 #define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT                                4
 #define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_MASK                         (1 << QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT)
 #define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT           8
@@ -731,8 +731,8 @@
 /* DPLL2 (common for CPU, AUD, DDR and PCIE) */
 #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT                        13
 #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK                 BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 2)
-#define QCA_PLL_SRIF_DPLL2_PLL_PWD_SHIFT               16
-#define QCA_PLL_SRIF_DPLL2_PLL_PWD_MASK                        (1 << QCA_PLL_SRIF_DPLL2_PLL_PWD_SHIFT)
+#define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT                        16
+#define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK                 (1 << QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT)
 #define QCA_PLL_SRIF_DPLL2_KD_SHIFT                            19
 #define QCA_PLL_SRIF_DPLL2_KD_MASK                             BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 7)
 #define QCA_PLL_SRIF_DPLL2_KI_SHIFT                            26
@@ -806,6 +806,114 @@
        #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL             0
 #endif
 
+/* RST_RESET */
+#define QCA_RST_RESET_I2C_RST_SHIFT                                            0
+#define QCA_RST_RESET_I2C_RST_MASK                                             (1 << QCA_RST_RESET_I2C_RST_SHIFT)
+#define QCA_RST_RESET_MBOX_RST_SHIFT                                   1
+#define QCA_RST_RESET_MBOX_RST_MASK                                            (1 << QCA_RST_RESET_MBOX_RST_SHIFT)
+#define QCA_RST_RESET_LUT_RST_SHIFT                                            2
+#define QCA_RST_RESET_LUT_RST_MASK                                             (1 << QCA_RST_RESET_LUT_RST_SHIFT)
+#define QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_SHIFT              3
+#define QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_MASK               (1 << QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_SHIFT)
+#define QCA_RST_RESET_USB_PHY_RST_SHIFT                                        4
+#define QCA_RST_RESET_USB_PHY_RST_MASK                                 (1 << QCA_RST_RESET_USB_PHY_RST_SHIFT)
+#define QCA_RST_RESET_USB_HOST_RST_SHIFT                               5
+#define QCA_RST_RESET_USB_HOST_RST_MASK                                        (1 << QCA_RST_RESET_USB_HOST_RST_SHIFT)
+
+#if (SOC_TYPE == QCA_AR933X_SOC)
+       #define QCA_RST_RESET_SLIC_RST_SHIFT                            6
+       #define QCA_RST_RESET_SLIC_RST_MASK                                     (1 << QCA_RST_RESET_SLIC_RST_SHIFT)
+#else
+       #define QCA_RST_RESET_PCIE_RST_SHIFT                            6
+       #define QCA_RST_RESET_PCIE_RST_MASK                                     (1 << QCA_RST_RESET_PCIE_RST_SHIFT)
+       #define QCA_RST_RESET_SLIC_RST_SHIFT                            30
+       #define QCA_RST_RESET_SLIC_RST_MASK                                     (1 << QCA_RST_RESET_SLIC_RST_SHIFT)
+#endif
+
+#define QCA_RST_RESET_PCIE_PHY_RST_SHIFT                               7
+#define QCA_RST_RESET_PCIE_PHY_RST_MASK                                        (1 << QCA_RST_RESET_PCIE_PHY_RST_SHIFT)
+
+#if (SOC_TYPE == QCA_QCA9558_SOC)
+       #define QCA_RST_RESET_ETH_SGMII_RST_SHIFT                       8
+       #define QCA_RST_RESET_ETH_SGMII_RST_MASK                        (1 << QCA_RST_RESET_ETH_SGMII_RST_SHIFT)
+#else
+       #define QCA_RST_RESET_ETH_SWITCH_RST_SHIFT                      8
+       #define QCA_RST_RESET_ETH_SWITCH_RST_MASK                       (1 << QCA_RST_RESET_ETH_SWITCH_RST_SHIFT)
+#endif
+
+#define QCA_RST_RESET_GE0_MAC_RST_SHIFT                                        9
+#define QCA_RST_RESET_GE0_MAC_RST_MASK                                 (1 << QCA_RST_RESET_GE0_MAC_RST_SHIFT)
+#define QCA_RST_RESET_HOST_DMA_INT_SHIFT                               10
+#define QCA_RST_RESET_HOST_DMA_INT_MASK                                        (1 << QCA_RST_RESET_HOST_DMA_INT_SHIFT)
+
+#if (SOC_TYPE == QCA_AR933X_SOC)
+       #define QCA_RST_RESET_WLAN_RST_SHIFT                            11
+       #define QCA_RST_RESET_WLAN_RST_MASK                                     (1 << QCA_RST_RESET_WLAN_RST_SHIFT)
+#else
+       #define QCA_RST_RESET_USB_PHY_ARST_SHIFT                        11
+       #define QCA_RST_RESET_USB_PHY_ARST_MASK                         (1 << QCA_RST_RESET_USB_PHY_ARST_SHIFT)
+#endif
+
+#if (SOC_TYPE == QCA_AR933X_SOC)
+       #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT                     14
+       #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK                      (1 << QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT)
+#else
+       #if (SOC_TYPE == QCA_QCA9558_SOC)
+               #define QCA_RST_RESET_ETH_SGMII_ARST_SHIFT              12
+               #define QCA_RST_RESET_ETH_SGMII_ARST_MASK               (1 << QCA_RST_RESET_ETH_SGMII_ARST_SHIFT)
+       #else
+               #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT             12
+               #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK              (1 << QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT)
+       #endif
+
+       #define QCA_RST_RESET_NANDF_RST_SHIFT                           14
+       #define QCA_RST_RESET_NANDF_RST_MASK                            (1 << QCA_RST_RESET_NANDF_RST_SHIFT)
+#endif
+
+#define QCA_RST_RESET_GE1_MAC_RST_SHIFT                                        13
+#define QCA_RST_RESET_GE1_MAC_RST_MASK                                 (1 << QCA_RST_RESET_GE1_MAC_RST_SHIFT)
+#define QCA_RST_RESET_USB_PHY_PLLPWD_EXT_SHIFT                 15
+#define QCA_RST_RESET_USB_PHY_PLLPWD_EXT_MASK                  (1 << QCA_RST_RESET_USB_PHY_PLLPWD_EXT_SHIFT)
+#define QCA_RST_RESET_DDR_RST_SHIFT                                            16
+#define QCA_RST_RESET_DDR_RST_MASK                                             (1 << QCA_RST_RESET_DDR_RST_SHIFT)
+#define QCA_RST_RESET_HSUART_RST_SHIFT                                 17
+#define QCA_RST_RESET_HSUART_RST_MASK                                  (1 << QCA_RST_RESET_HSUART_RST_SHIFT)
+#define QCA_RST_RESET_PCIEEP_RST_SHIFT                                 18
+#define QCA_RST_RESET_PCIEEP_RST_MASK                                  (1 << QCA_RST_RESET_PCIEEP_RST_SHIFT)
+#define QCA_RST_RESET_HOST_DMA_RST_INT_SHIFT                   19
+#define QCA_RST_RESET_HOST_DMA_RST_INT_MASK                            (1 << QCA_RST_RESET_HOST_DMA_RST_INT_SHIFT)
+#define QCA_RST_RESET_CPU_COLD_RST_SHIFT                               20
+#define QCA_RST_RESET_CPU_COLD_RST_MASK                                        (1 << QCA_RST_RESET_CPU_COLD_RST_SHIFT)
+#define QCA_RST_RESET_CPU_NMI_SHIFT                                            21
+#define QCA_RST_RESET_CPU_NMI_MASK                                             (1 << QCA_RST_RESET_CPU_NMI_SHIFT)
+#define QCA_RST_RESET_GE0_MDIO_RST_SHIFT                               22
+#define QCA_RST_RESET_GE0_MDIO_RST_MASK                                        (1 << QCA_RST_RESET_GE0_MDIO_RST_SHIFT)
+#define QCA_RST_RESET_GE1_MDIO_RST_SHIFT                               23
+#define QCA_RST_RESET_GE1_MDIO_RST_MASK                                        (1 << QCA_RST_RESET_GE1_MDIO_RST_SHIFT)
+#define QCA_RST_RESET_FULL_CHIP_RST_SHIFT                              24
+#define QCA_RST_RESET_FULL_CHIP_RST_MASK                               (1 << QCA_RST_RESET_FULL_CHIP_RST_SHIFT)
+#define QCA_RST_RESET_CHECKSUM_ACC_RST_SHIFT                   25
+#define QCA_RST_RESET_CHECKSUM_ACC_RST_MASK                            (1 << QCA_RST_RESET_CHECKSUM_ACC_RST_SHIFT)
+#define QCA_RST_RESET_PCIEEP_RST_INT_SHIFT                             26
+#define QCA_RST_RESET_PCIEEP_RST_INT_MASK                              (1 << QCA_RST_RESET_PCIEEP_RST_INT_SHIFT)
+#define QCA_RST_RESET_RTC_RST_SHIFT                                            27
+#define QCA_RST_RESET_RTC_RST_MASK                                             (1 << QCA_RST_RESET_RTC_RST_SHIFT)
+#define QCA_RST_RESET_EXT_RST_SHIFT                                            28
+#define QCA_RST_RESET_EXT_RST_MASK                                             (1 << QCA_RST_RESET_EXT_RST_SHIFT)
+
+#if (SOC_TYPE == QCA_QCA9558_SOC || \
+        SOC_TYPE == QCA_AR9344_SOC  || \
+        SOC_TYPE == QCA_AR9341_SOC)
+       #define QCA_RST_RESET_HOST_DMA_RST_SHIFT                        29
+       #define QCA_RST_RESET_HOST_DMA_RST_MASK                         (1 << QCA_RST_RESET_HOST_DMA_RST_SHIFT)
+#else
+       #define QCA_RST_RESET_USB_EXT_PWR_SHIFT                         29
+       #define QCA_RST_RESET_USB_EXT_PWR_MASK                          (1 << QCA_RST_RESET_USB_EXT_PWR_SHIFT)
+#endif
+
+#define QCA_RST_RESET_HOST_DMA_RST_STATUS_SHIFT                        31
+#define QCA_RST_RESET_HOST_DMA_RST_STATUS_MASK                 (1 << QCA_RST_RESET_HOST_DMA_RST_STATUS_SHIFT)
+
 /* RST_REVISION_ID (Chip revision ID) */
 #define QCA_RST_REVISION_ID_MAJOR_SHIFT                                4
 #define QCA_RST_REVISION_ID_MAJOR_MASK                         BITS(QCA_RST_REVISION_ID_MAJOR_SHIFT, 12)
@@ -826,7 +934,6 @@
 #define QCA_RST_REVISION_ID_MAJOR_QCA953X_V2_VAL       0x0160
 #define QCA_RST_REVISION_ID_MAJOR_QCA9558_VAL          0x1130
 
-
 /*
  * SPI serial flash registers
  */
@@ -873,8 +980,8 @@
 inline u32 qca_xtal_is_40mhz(void);
 inline u32 qca_mem_type(void);
 void   qca_soc_name_rev(char *buf);
+void   qca_full_chip_reset(void);
 void   qca_sys_clocks(u32 *cpu_clk, u32 *ddr_clk, u32 *ahb_clk, u32 *spi_clk, u32 *ref_clk);
-void   qca_spi_flash_sector_erase(u32 address);
 #endif /* !__ASSEMBLY__ */
 
 /*