arm64: zynqmp: Sync gem clock nodes with mainline Linux

Just fixing indentation and update year in Copyright.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 998298cc9bee8a662bbf177497328f01bf93d7ae..8eacd22d7cdacc818f37879dffc1b385dc483643 100644 (file)
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -2,7 +2,7 @@
 /*
  * Clock specification for Xilinx ZynqMP
  *
- * (C) Copyright 2017, Xilinx, Inc.
+ * (C) Copyright 2017 - 2019, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
@@ -173,26 +173,30 @@
 };
 
 &gem0 {
-       clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>,
-                <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>;
+       clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
+                <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
+                <&zynqmp_clk GEM_TSU>;
        clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
 &gem1 {
-       clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>,
-                <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>;
+       clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
+                <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
+                <&zynqmp_clk GEM_TSU>;
        clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
 &gem2 {
-       clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>,
-                <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>;
+       clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
+                <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
+                <&zynqmp_clk GEM_TSU>;
        clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
 &gem3 {
-       clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>,
-                <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>;
+       clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
+                <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
+                <&zynqmp_clk GEM_TSU>;
        clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };