rockchip: px5: enable spl-fifo-mode for emmc for px5-evb

We need load some parts of ATF to sram, but rockchip
dwmmc controllers can't do dma to non-ddr addresses
space, so set the mmc controller into fifo mode in spl.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
index 002767a0330ea35bf4b0268a213bf056ca5ebb63..936ce5572756a9d479f4f052e805382a6dbbad56 100644 (file)
--- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
@@ -58,6 +58,8 @@
 };
 
 &emmc {
+       /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
+       u-boot,spl-fifo-mode;
        u-boot,dm-pre-reloc;
 };