arm64: versal: Enable memory mapping via DT
authorMichal Simek <michal.simek@xilinx.com>
Mon, 29 Apr 2019 16:39:09 +0000 (09:39 -0700)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 8 Oct 2019 07:11:14 +0000 (09:11 +0200)
Code reads DT and setup MMU table based on memory node. This will ensure
that only DT needs to be changed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/mach-versal/cpu.c
arch/arm/mach-versal/include/mach/sys_proto.h
board/xilinx/versal/board.c

index 70c1908ec4b22ad3f13c79019931cb7aad3b12fc..dc6a9205be0e7584251bdd5d72fd4d18589724b1 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct mm_region versal_mem_map[] = {
+#define VERSAL_MEM_MAP_USED    6
+
+#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
+
+/* +1 is end of list which needs to be empty */
+#define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + 1)
+
+static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
        {
-               .virt = 0x0UL,
-               .phys = 0x0UL,
-               .size = 0x80000000UL,
-               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-                        PTE_BLOCK_INNER_SHARE
-       }, {
                .virt = 0x80000000UL,
                .phys = 0x80000000UL,
                .size = 0x70000000UL,
@@ -59,12 +60,27 @@ static struct mm_region versal_mem_map[] = {
                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
                         PTE_BLOCK_NON_SHARE |
                         PTE_BLOCK_PXN | PTE_BLOCK_UXN
-       }, {
-               /* List terminator */
-               0,
        }
 };
 
+void mem_map_fill(void)
+{
+       int banks = VERSAL_MEM_MAP_USED;
+
+       for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+               /* Zero size means no more DDR that's this is end */
+               if (!gd->bd->bi_dram[i].size)
+                       break;
+
+               versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
+               versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
+               versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
+               versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                                             PTE_BLOCK_INNER_SHARE;
+               banks = banks + 1;
+       }
+}
+
 struct mm_region *mem_map = versal_mem_map;
 
 u64 get_page_table_size(void)
index 1dc7bf665690547af94fba82db9f2ed96808bef6..05934c28d67f9145fcb1dfbf5bb60134ad4e607a 100644 (file)
@@ -9,3 +9,4 @@ enum {
 };
 
 void tcm_init(u8 mode);
+void mem_map_fill(void);
index 2b4edd8738b4a4bc1b188a92356fcfa3fb978b85..5718e1aa7e47a4fdee7226dc59a95b3c070f139c 100644 (file)
@@ -9,6 +9,7 @@
 #include <malloc.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
 #include <dm/device.h>
 #include <dm/uclass.h>
 #include <versalpl.h>
@@ -194,7 +195,13 @@ int board_late_init(void)
 
 int dram_init_banksize(void)
 {
-       fdtdec_setup_memory_banksize();
+       int ret;
+
+       ret = fdtdec_setup_memory_banksize();
+       if (ret)
+               return ret;
+
+       mem_map_fill();
 
        return 0;
 }