Cosmetic: fix alphabetical order in config files

diff --git a/Makefile b/Makefile
index 0de734a51db3913fa448e2886439548f8f388c95..6d43108b4556a93e1bf7aa20741e25bf52fe9416 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -229,8 +229,8 @@ COMMON_ETHS27_TARGETS = \
        tp-link_tl-mr3420_v3 \
        tp-link_tl-mr6400_v1v2 \
        tp-link_tl-wa801nd_v2 \
-       tp-link_tl-wa850re_v2 \
        tp-link_tl-wa830re_v2 \
+       tp-link_tl-wa850re_v2 \
        tp-link_tl-wdr3500_v1 \
        tp-link_tl-wr802n_v1 \
        tp-link_tl-wr810n_v1 \

diff --git a/u-boot/include/configs/ap121.h b/u-boot/include/configs/ap121.h
index 5c2af1cb03864f08e5e2c9eb64e4531a6640b5c3..81a64eb4e782f882260c2415b392f7119fb566f2 100644 (file)
--- a/u-boot/include/configs/ap121.h
+++ b/u-boot/include/configs/ap121.h
@@ -56,13 +56,6 @@
                                                CONFIG_QCA_GPIO_MASK_LED_ACT_L
        #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
 
-#elif defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE)
-
-       #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO27
-       #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
-       #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
-       #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
-
 #elif defined(CONFIG_FOR_CREATCOMM_D3321)
 
        #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0  | GPIO13 | GPIO14 |\
@@ -92,6 +85,13 @@
        #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
        #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
 
+#elif defined(CONFIG_FOR_GLINET_6416)
+
+       #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0 | GPIO13
+       #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_H
+       #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
+       #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
+
 #elif defined(CONFIG_FOR_GLINET_GL_AR150)
 
        #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0 | GPIO13 | GPIO15
@@ -102,13 +102,6 @@
        #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO6
        #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
 
-#elif defined(CONFIG_FOR_GLINET_6416)
-
-       #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0 | GPIO13
-       #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_H
-       #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
-       #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
-
 #elif defined(CONFIG_FOR_GLINET_GL_USB150)
 
        #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0
@@ -210,6 +203,13 @@
        #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
        #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
 
+#elif defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE)
+
+       #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO27
+       #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
+       #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
+       #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
 #endif
 
 /*
@@ -235,12 +235,6 @@
                                "rootfstype=squashfs init=/sbin/init "\
                                "mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),6144k(rootfs),1600k(uImage),64k(NVRAM),64k(ART)"
 
-#elif defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE)
-
-       #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
-                               "rootfstype=squashfs init=/sbin/init "\
-                               "mtdparts=ar7240-nor0:128k(u-boot),64k(u-boot-env),16128k(firmware),64k(art)"
-
 #elif defined(CONFIG_FOR_CREATCOMM_D3321)
 
        #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:03 "\
@@ -260,13 +254,6 @@
                                "rootfstype=squashfs init=/sbin/init "\
                                "mtdparts=ar7240-nor0:192k(u-boot),64k(u-boot-env),16064k(firmware),64k(art)"
 
-#elif defined(CONFIG_FOR_GLINET_GL_AR150) ||\
-      defined(CONFIG_FOR_GLINET_GL_USB150)
-
-       #define CONFIG_BOOTARGS "console=ttyATH0,115200 board=domino root=31:03 "\
-                               "rootfstype=squashfs,jffs2 noinitrd "\
-                               "mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1280k(kernel),14656k(rootfs),64k(nvram),64k(art)ro,15936k@0x50000(firmware)"
-
 #elif defined(CONFIG_FOR_GLINET_6416)        ||\
       defined(CONFIG_FOR_TPLINK_MR10U_V1)    ||\
       defined(CONFIG_FOR_TPLINK_MR13U_V1)    ||\
@@ -281,6 +268,13 @@
                                "rootfstype=squashfs init=/sbin/init "\
                                "mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
 
+#elif defined(CONFIG_FOR_GLINET_GL_AR150) ||\
+      defined(CONFIG_FOR_GLINET_GL_USB150)
+
+       #define CONFIG_BOOTARGS "console=ttyATH0,115200 board=domino root=31:03 "\
+                               "rootfstype=squashfs,jffs2 noinitrd "\
+                               "mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1280k(kernel),14656k(rootfs),64k(nvram),64k(art)ro,15936k@0x50000(firmware)"
+
 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
 
        #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
@@ -293,6 +287,12 @@
                                "rootfstype=squashfs init=/sbin/init "\
                                "mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),6912k(rootfs),64k(config),64k(art)"
 
+#elif defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE)
+
+       #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
+                               "rootfstype=squashfs init=/sbin/init "\
+                               "mtdparts=ar7240-nor0:128k(u-boot),64k(u-boot-env),16128k(firmware),64k(art)"
+
 #endif
 
 /*
@@ -306,22 +306,36 @@
     defined(CONFIG_FOR_CREATCOMM_D3321)        ||\
     defined(CONFIG_FOR_GLINET_GL_AR150)        ||\
     defined(CONFIG_FOR_GLINET_GL_USB150)
+
        #define CFG_LOAD_ADDR   0x9F050000
-#elif defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE)
-       #define CFG_LOAD_ADDR   0x9F030000
+
 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
+
        #define CFG_LOAD_ADDR   0x9F080000
+
 #elif defined(CONFIG_FOR_DRAGINO_MS14) ||\
       defined(CONFIG_FOR_VILLAGE_TELCO_MP2)
+
        #define CFG_LOAD_ADDR   0x9F040000
+
+#elif defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE)
+
+       #define CFG_LOAD_ADDR   0x9F030000
+
 #else
+
        #define CFG_LOAD_ADDR   0x9F020000
+
 #endif
 
 #if defined(CONFIG_FOR_ALFA_NETWORK_HORNET_UB)
+
        #define CONFIG_BOOTCOMMAND      "bootm 0x9F050000 || bootm 0x9F650000 || bootm 0x9FE50000"
+
 #else
+
        #define CONFIG_BOOTCOMMAND      "bootm " MK_STR(CFG_LOAD_ADDR)
+
 #endif
 
 /*
@@ -334,29 +348,41 @@
     defined(CONFIG_FOR_CREATCOMM_D3321)        ||\
     defined(CONFIG_FOR_GLINET_GL_AR150)        ||\
     defined(CONFIG_FOR_GLINET_GL_USB150)
+
        #define CFG_ENV_ADDR            0x9F040000
        #define CFG_ENV_SIZE            0x8000
        #define CFG_ENV_SECT_SIZE       0x10000
+
 #elif defined(CONFIG_FOR_ALFA_NETWORK_AP121F)
+
        #define CFG_ENV_ADDR            0x9F030000
        #define CFG_ENV_SIZE            0x10000
-#elif defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE)
-       #define CFG_ENV_ADDR            0x9F020000
-       #define CFG_ENV_SIZE            0x8000
-       #define CFG_ENV_SECT_SIZE       0x10000
+
 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
+
        #define CFG_ENV_ADDR            0x9F028000
        #define CFG_ENV_SIZE            0x7C00
        #define CFG_ENV_SECT_SIZE       0x10000
+
 #elif defined(CONFIG_FOR_DRAGINO_MS14) ||\
       defined(CONFIG_FOR_VILLAGE_TELCO_MP2)
+
        #define CFG_ENV_ADDR            0x9F030000
        #define CFG_ENV_SIZE            0x8000
        #define CFG_ENV_SECT_SIZE       0x10000
+
+#elif defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE)
+
+       #define CFG_ENV_ADDR            0x9F020000
+       #define CFG_ENV_SIZE            0x8000
+       #define CFG_ENV_SECT_SIZE       0x10000
+
 #else
+
        #define CFG_ENV_ADDR            0x9F01EC00
        #define CFG_ENV_SIZE            0x1000
        #define CFG_ENV_SECT_SIZE       0x10000
+
 #endif
 
 /*
@@ -380,21 +406,20 @@
     defined(CONFIG_FOR_CREATCOMM_D3321)        ||\
     defined(CONFIG_FOR_DRAGINO_MS14)           ||\
     defined(CONFIG_FOR_VILLAGE_TELCO_MP2)
+
        #define OFFSET_MAC_DATA_BLOCK           0xFF0000
        #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
        #define OFFSET_MAC_ADDRESS              0x000000
        #define OFFSET_MAC_ADDRESS2             0x000006
+
 #elif defined(CONFIG_FOR_ALFA_NETWORK_AP121F)
+
        #define OFFSET_MAC_DATA_BLOCK           0x40000
        #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x10000
        #define OFFSET_MAC_ADDRESS              0x00000
-#elif defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE) ||\
-      defined(CONFIG_FOR_GLINET_GL_AR150)             ||\
-      defined(CONFIG_FOR_GLINET_GL_USB150)
-       #define OFFSET_MAC_DATA_BLOCK           0xFF0000
-       #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
-       #define OFFSET_MAC_ADDRESS              0x000000
+
 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
+
        /*
         * DIR-505 has two MAC addresses inside dedicated MAC partition
         * They are stored in plain text...
@@ -404,36 +429,53 @@
         * #define OFFSET_MAC_ADDRESS           0x000004
         * #define OFFSET_MAC_ADDRESS2          0x000016
         */
+
+#elif defined(CONFIG_FOR_GLINET_GL_AR150)  ||\
+      defined(CONFIG_FOR_GLINET_GL_USB150) ||\
+      defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE)
+
+       #define OFFSET_MAC_DATA_BLOCK           0xFF0000
+       #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
+       #define OFFSET_MAC_ADDRESS              0x000000
+
 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
+
        #define OFFSET_MAC_DATA_BLOCK           0x010000
        #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
        #define OFFSET_MAC_ADDRESS              0x00FC00
+
 #else
+
        #define OFFSET_MAC_DATA_BLOCK           0x010000
        #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
        #define OFFSET_MAC_ADDRESS              0x00FC00
+
 #endif
 
 #if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)         &&\
     !defined(CONFIG_FOR_ALFA_NETWORK_AP121F)         &&\
     !defined(CONFIG_FOR_ALFA_NETWORK_HORNET_UB)      &&\
-    !defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE) &&\
     !defined(CONFIG_FOR_CREATCOMM_D3321)             &&\
     !defined(CONFIG_FOR_DLINK_DIR505_A1)             &&\
     !defined(CONFIG_FOR_DRAGINO_MS14)                &&\
-    !defined(CONFIG_FOR_GLINET_GL_AR150)             &&\
     !defined(CONFIG_FOR_GLINET_6416)                 &&\
+    !defined(CONFIG_FOR_GLINET_GL_AR150)             &&\
     !defined(CONFIG_FOR_GLINET_GL_USB150)            &&\
     !defined(CONFIG_FOR_GS_OOLITE_V1_DEV)            &&\
+    !defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE) &&\
     !defined(CONFIG_FOR_VILLAGE_TELCO_MP2)
+
        #define OFFSET_ROUTER_MODEL     0xFD00
+
 #endif
 
 #if defined(CONFIG_FOR_TPLINK_MR3020_V1) ||\
     defined(CONFIG_FOR_TPLINK_MR3220_V2) ||\
     defined(CONFIG_FOR_TPLINK_WR710N_V1) ||\
     defined(CONFIG_FOR_TPLINK_WR740N_V4)
+
        #define OFFSET_PIN_NUMBER       0xFE00
+
 #endif
 
 /*
@@ -444,27 +486,35 @@
 
 /* Dragino MS14 uses different IP addresses */
 #if defined(CONFIG_FOR_DRAGINO_MS14)
+
        #undef  CONFIG_IPADDR
        #define CONFIG_IPADDR   192.168.255.1
 
        #undef  CONFIG_SERVERIP
        #define CONFIG_SERVERIP 192.168.255.2
+
 #endif
 
 /* Dragino MS14 and Unwired One boards use different prompts */
 #if defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE)
+
        #undef  CFG_PROMPT
        #define CFG_PROMPT      "BSB> "
+
 #elif defined(CONFIG_FOR_DRAGINO_MS14) ||\
       defined(CONFIG_FOR_VILLAGE_TELCO_MP2)
+
        #undef  CFG_PROMPT
        #define CFG_PROMPT      "dr_boot> "
+
 #endif
 
 /* D-Link DIR-505 is limited to 64 KB only and doesn't use env */
 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
+
        #undef CONFIG_CMD_DHCP
        #undef CONFIG_CMD_LOADB
+
 #endif
 
 /*
@@ -475,32 +525,48 @@
 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS      CFG_LOAD_ADDR
 
 #if defined(CONFIG_FOR_ALFA_NETWORK_AP121F)
+
        #define WEBFAILSAFE_UPLOAD_ART_ADDRESS  (CFG_FLASH_BASE + 0x40000)
+
 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
+
        #define WEBFAILSAFE_UPLOAD_ART_ADDRESS  (CFG_FLASH_BASE + 0x10000)
+
 #endif
 
 /* Firmware size limit */
 #if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) ||\
     defined(CONFIG_FOR_GLINET_GL_AR150)     ||\
     defined(CONFIG_FOR_GLINET_GL_USB150)
+
        #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (384 * 1024)
+
 #elif defined(CONFIG_FOR_ALFA_NETWORK_AP121F) ||\
       defined(CONFIG_FOR_DRAGINO_MS14)        ||\
       defined(CONFIG_FOR_VILLAGE_TELCO_MP2)
+
        #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (320 * 1024)
+
 #elif defined(CONFIG_FOR_ALFA_NETWORK_HORNET_UB)
+
        #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (448 * 1024)
-#elif defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE)
-       #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (256 * 1024)
+
 #elif defined(CONFIG_FOR_CREATCOMM_D3321)
+
        #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (1856 * 1024)
+
 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
+
        #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (512 * 1024)
-#elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
-       #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
+
+#elif defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE)
+
+       #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (256 * 1024)
+
 #else
+
        #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
+
 #endif
 
 /*
@@ -520,8 +586,8 @@
        #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x40000
        #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 
-#elif defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE) ||\
-      defined(CONFIG_FOR_DLINK_DIR505_A1)
+#elif defined(CONFIG_FOR_DLINK_DIR505_A1) ||\
+      defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE)
 
        #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x20000
        #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
@@ -547,14 +613,16 @@
 #if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)         &&\
     !defined(CONFIG_FOR_ALFA_NETWORK_AP121F)         &&\
     !defined(CONFIG_FOR_ALFA_NETWORK_HORNET_UB)      &&\
-    !defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE) &&\
     !defined(CONFIG_FOR_CREATCOMM_D3321)             &&\
     !defined(CONFIG_FOR_DLINK_DIR505_A1)             &&\
     !defined(CONFIG_FOR_DRAGINO_MS14)                &&\
     !defined(CONFIG_FOR_GLINET_GL_AR150)             &&\
     !defined(CONFIG_FOR_GLINET_GL_USB150)            &&\
+    !defined(CONFIG_FOR_UNWIRED_DEVICES_UNWIRED_ONE) &&\
     !defined(CONFIG_FOR_VILLAGE_TELCO_MP2)
+
        #define CONFIG_UPG_SCRIPTS_UBOOT_SIZE_BCKP_HEX  0x20000
+
 #endif
 
 #endif /* _AP121_H */

diff --git a/u-boot/include/configs/ap143.h b/u-boot/include/configs/ap143.h
index f03c6b9e1439772b46bae785adb4f077e8b9a53e..6e3c40241ee7aa6337e0dd1e9acf002167b09dd0 100644 (file)
--- a/u-boot/include/configs/ap143.h
+++ b/u-boot/include/configs/ap143.h
@@ -73,6 +73,15 @@
        #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO11 |\
                                                CONFIG_QCA_GPIO_MASK_LED_ACT_L
 
+#elif defined(CONFIG_FOR_TPLINK_MR3420_V3)
+
+       #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO1  | GPIO3  | GPIO4  |\
+                                               GPIO11 | GPIO13 | GPIO14 |\
+                                               GPIO15 | GPIO16
+       #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
+       #define CONFIG_QCA_GPIO_MASK_IN         GPIO12 | GPIO17
+       #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
 #elif defined(CONFIG_FOR_TPLINK_MR6400_V1V2)
 
        #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0  | GPIO1 | GPIO3 |\
@@ -94,6 +103,14 @@
        #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO15 |\
                                                CONFIG_QCA_GPIO_MASK_LED_ACT_L
 
+#elif defined(CONFIG_FOR_TPLINK_WR802N_V1) ||\
+      defined(CONFIG_FOR_TPLINK_WR820N_V1_CN)
+
+       #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13
+       #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
+       #define CONFIG_QCA_GPIO_MASK_IN         GPIO12
+       #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
 #elif defined(CONFIG_FOR_TPLINK_WR810N_V1)
 
        #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13
@@ -103,23 +120,6 @@
        #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO11 |\
                                                CONFIG_QCA_GPIO_MASK_LED_ACT_L
 
-#elif defined(CONFIG_FOR_TPLINK_WR820N_V1_CN) ||\
-      defined(CONFIG_FOR_TPLINK_WR802N_V1)
-
-       #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13
-       #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
-       #define CONFIG_QCA_GPIO_MASK_IN         GPIO12
-       #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
-
-#elif defined(CONFIG_FOR_TPLINK_MR3420_V3)
-
-       #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO1  | GPIO3  | GPIO4  |\
-                                               GPIO11 | GPIO13 | GPIO14 |\
-                                               GPIO15 | GPIO16
-       #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
-       #define CONFIG_QCA_GPIO_MASK_IN         GPIO12 | GPIO17
-       #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
-
 #elif defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
       defined(CONFIG_FOR_TPLINK_WR841N_V9)
 
@@ -233,23 +233,23 @@
                                "rootfstype=squashfs init=/sbin/init "\
                                "mtdparts=ath-nor0:128k(u-boot),1024k(kernel),6912k(rootfs),64k(config),64k(art)"
 
-#elif defined(CONFIG_FOR_TPLINK_WR820N_V1_CN)
-
-       #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
-                               "rootfstype=squashfs init=/sbin/init "\
-                               "mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(art)"
-
-#elif defined(CONFIG_FOR_TPLINK_MR3420_V3) ||\
+#elif defined(CONFIG_FOR_TPLINK_MR3420_V3)  ||\
       defined(CONFIG_FOR_TPLINK_WA850RE_V2) ||\
+      defined(CONFIG_FOR_TPLINK_WR802N_V1)  ||\
       defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
       defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
-      defined(CONFIG_FOR_TPLINK_WR841N_V9)  ||\
-      defined(CONFIG_FOR_TPLINK_WR802N_V1)
+      defined(CONFIG_FOR_TPLINK_WR841N_V9)
 
        #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
                                "rootfstype=squashfs init=/sbin/init "\
                                "mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
 
+#elif defined(CONFIG_FOR_TPLINK_WR820N_V1_CN)
+
+       #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
+                               "rootfstype=squashfs init=/sbin/init "\
+                               "mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(art)"
+
 #elif defined(CONFIG_FOR_TPLINK_WR842N_V3) ||\
       defined(CONFIG_FOR_TPLINK_WR902AC_V1)
 
@@ -286,14 +286,18 @@
     defined(CONFIG_FOR_TPLINK_WR841N_V9)    ||\
     defined(CONFIG_FOR_TPLINK_WR842N_V3)    ||\
     defined(CONFIG_FOR_TPLINK_WR902AC_V1)
+
        #define CFG_LOAD_ADDR   0x9F020000
+
 #elif defined(CONFIG_FOR_P2W_CPE505N)    ||\
       defined(CONFIG_FOR_P2W_R602N)      ||\
       defined(CONFIG_FOR_WALLYS_DR531)   ||\
       defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
       defined(CONFIG_FOR_YUNCORE_CPE830) ||\
       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+
        #define CFG_LOAD_ADDR   0x9F050000
+
 #endif
 
 #if defined(CONFIG_FOR_P2W_CPE505N)    ||\
@@ -301,9 +305,13 @@
     defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
     defined(CONFIG_FOR_YUNCORE_CPE830) ||\
     defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+
        #define CONFIG_BOOTCOMMAND      "bootm 0x9F050000 || bootm 0x9FE80000"
+
 #else
+
        #define CONFIG_BOOTCOMMAND      "bootm " MK_STR(CFG_LOAD_ADDR)
+
 #endif
 
 /*
@@ -315,17 +323,21 @@
     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
     defined(CONFIG_FOR_COMFAST_CF_E530N)
+
        #define CFG_ENV_ADDR            0x9F018000
        #define CFG_ENV_SIZE            0x7C00
        #define CFG_ENV_SECT_SIZE       0x10000
+
 #elif defined(CONFIG_FOR_P2W_CPE505N)    ||\
       defined(CONFIG_FOR_P2W_R602N)      ||\
       defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
       defined(CONFIG_FOR_YUNCORE_CPE830) ||\
       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+
        #define CFG_ENV_ADDR            0x9F040000
        #define CFG_ENV_SIZE            0xFC00
        #define CFG_ENV_SECT_SIZE       0x10000
+
 #elif defined(CONFIG_FOR_TPLINK_MR22U_V1)     ||\
       defined(CONFIG_FOR_TPLINK_MR3420_V3)    ||\
       defined(CONFIG_FOR_TPLINK_MR6400_V1V2)  ||\
@@ -338,13 +350,17 @@
       defined(CONFIG_FOR_TPLINK_WR841N_V9)    ||\
       defined(CONFIG_FOR_TPLINK_WR842N_V3)    ||\
       defined(CONFIG_FOR_TPLINK_WR902AC_V1)
+
        #define CFG_ENV_ADDR            0x9F01EC00
        #define CFG_ENV_SIZE            0x1000
        #define CFG_ENV_SECT_SIZE       0x10000
+
 #elif defined(CONFIG_FOR_WALLYS_DR531)
+
        #define CFG_ENV_ADDR            0x9F030000
        #define CFG_ENV_SIZE            0xF800
        #define CFG_ENV_SECT_SIZE       0x10000
+
 #endif
 
 /*
@@ -365,21 +381,21 @@
     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
     defined(CONFIG_FOR_COMFAST_CF_E530N)
+
        #define OFFSET_MAC_DATA_BLOCK           0x10000
        #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x10000
        #define OFFSET_MAC_ADDRESS              0x00000
+
 #elif defined(CONFIG_FOR_P2W_CPE505N)    ||\
       defined(CONFIG_FOR_P2W_R602N)      ||\
       defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
       defined(CONFIG_FOR_YUNCORE_CPE830) ||\
       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+
        #define OFFSET_MAC_DATA_BLOCK           0xFF0000
        #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
        #define OFFSET_MAC_ADDRESS              0x000000
-#elif defined(CONFIG_FOR_TPLINK_WA850RE_V2)
-       #define OFFSET_MAC_DATA_BLOCK           0x3c0000
-       #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
-       #define OFFSET_MAC_ADDRESS              0x000008
+
 #elif defined(CONFIG_FOR_TPLINK_MR22U_V1)     ||\
       defined(CONFIG_FOR_TPLINK_MR3420_V3)    ||\
       defined(CONFIG_FOR_TPLINK_MR6400_V1V2)  ||\
@@ -390,19 +406,31 @@
       defined(CONFIG_FOR_TPLINK_WR841N_V11)   ||\
       defined(CONFIG_FOR_TPLINK_WR841N_V9)    ||\
       defined(CONFIG_FOR_TPLINK_WR842N_V3)
+
        #define OFFSET_MAC_DATA_BLOCK           0x010000
        #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
        #define OFFSET_MAC_ADDRESS              0x00FC00
        #define OFFSET_ROUTER_MODEL             0x00FD00
        #define OFFSET_PIN_NUMBER               0x00FE00
+
+#elif defined(CONFIG_FOR_TPLINK_WA850RE_V2)
+
+       #define OFFSET_MAC_DATA_BLOCK           0x3c0000
+       #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
+       #define OFFSET_MAC_ADDRESS              0x000008
+
 #elif defined(CONFIG_FOR_TPLINK_WR902AC_V1)
+
        #define OFFSET_MAC_DATA_BLOCK           0x750000
        #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
        #define OFFSET_MAC_ADDRESS              0x000008
+
 #elif defined(CONFIG_FOR_WALLYS_DR531)
+
        #define OFFSET_MAC_DATA_BLOCK           0x030000
        #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
        #define OFFSET_MAC_ADDRESS              0x00F810
+
 #endif
 
 /*
@@ -419,10 +447,12 @@
     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
     defined(CONFIG_FOR_COMFAST_CF_E530N)
+
        #undef CONFIG_CMD_DHCP
        #undef CONFIG_CMD_LOADB
        #undef CONFIG_CMD_SNTP
        #undef CONFIG_UPG_SCRIPTS_UBOOT
+
 #endif
 
 /*
@@ -436,7 +466,9 @@
     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
     defined(CONFIG_FOR_COMFAST_CF_E530N)
+
        #define WEBFAILSAFE_UPLOAD_ART_ADDRESS  (CFG_FLASH_BASE + 0x10000)
+
 #endif
 
 /* Firmware size limit */
@@ -454,18 +486,26 @@
     defined(CONFIG_FOR_TPLINK_WR841N_V11)   ||\
     defined(CONFIG_FOR_TPLINK_WR841N_V9)    ||\
     defined(CONFIG_FOR_TPLINK_WR842N_V3)
+
        #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
-#elif defined(CONFIG_FOR_TPLINK_WA850RE_V2)
-       #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (448 * 1024)
-#elif defined(CONFIG_FOR_TPLINK_WR902AC_V1)
-       #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (832 * 1024)
+
 #elif defined(CONFIG_FOR_P2W_CPE505N)    ||\
       defined(CONFIG_FOR_P2W_R602N)      ||\
       defined(CONFIG_FOR_WALLYS_DR531)   ||\
       defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
       defined(CONFIG_FOR_YUNCORE_CPE830) ||\
       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+
        #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (384 * 1024)
+
+#elif defined(CONFIG_FOR_TPLINK_WA850RE_V2)
+
+       #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (448 * 1024)
+
+#elif defined(CONFIG_FOR_TPLINK_WR902AC_V1)
+
+       #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (832 * 1024)
+
 #endif
 
 /*
@@ -478,9 +518,13 @@
     defined(CONFIG_FOR_TPLINK_WR802N_V1)    ||\
     defined(CONFIG_FOR_TPLINK_WR820N_V1_CN) ||\
     defined(CONFIG_FOR_TPLINK_WR841N_V9)
+
        #define CONFIG_QCA_PLL  QCA_PLL_PRESET_550_400_200
+
 #else
+
        #define CONFIG_QCA_PLL  QCA_PLL_PRESET_650_400_200
+
 #endif
 
 #if defined(CONFIG_FOR_COMFAST_CF_E314N)    ||\
@@ -534,7 +578,9 @@
     !defined(CONFIG_FOR_YUNCORE_AP90Q)       &&\
     !defined(CONFIG_FOR_YUNCORE_CPE830)      &&\
     !defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+
        #define CONFIG_UPG_UBOOT_SIZE_BACKUP_HEX        0x20000
+
 #endif
 
 #if defined(CONFIG_FOR_P2W_CPE505N)    ||\
@@ -542,7 +588,9 @@
     defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
     defined(CONFIG_FOR_YUNCORE_CPE830) ||\
     defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+
        #define CONFIG_UPG_SCRIPTS_FW_ADDR_HEX  0x9F050000
+
 #endif
 
 /*

diff --git a/u-boot/include/configs/db12x.h b/u-boot/include/configs/db12x.h
index 8aead8f9f7cd51c1d08a5dc836df9c8bbcbf9fa3..6c1f4f3b18de511a2cb3c23dd1d0999f8a42e46b 100644 (file)
--- a/u-boot/include/configs/db12x.h
+++ b/u-boot/include/configs/db12x.h
@@ -36,17 +36,26 @@
        #define CONFIG_QCA_GPIO_MASK_IN         GPIO16
        #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
 
-#elif defined(CONFIG_FOR_TPLINK_WDR3600_V1) ||\
-      defined(CONFIG_FOR_TPLINK_WDR43X0_V1)
+#elif defined(CONFIG_FOR_TPLINK_MR3420_V2)
 
        #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11 | GPIO12 | GPIO13 |\
-                                               GPIO14 | GPIO15
-       #define CONFIG_QCA_GPIO_MASK_OUT        GPIO21 | GPIO22 |\
+                                               GPIO14 | GPIO15 | GPIO18 |\
+                                               GPIO19 | GPIO20 | GPIO21
+       #define CONFIG_QCA_GPIO_MASK_OUT        GPIO4 |\
                                                CONFIG_QCA_GPIO_MASK_LED_ACT_L
        #define CONFIG_QCA_GPIO_MASK_IN         GPIO16 | GPIO17
-       #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO21 | GPIO22 |\
+       #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO4 |\
                                                CONFIG_QCA_GPIO_MASK_LED_ACT_L
 
+#elif defined(CONFIG_FOR_TPLINK_WA801ND_V2) ||\
+      defined(CONFIG_FOR_TPLINK_WA830RE_V2)
+
+       #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13 | GPIO14 | GPIO15 |\
+                                               GPIO18
+       #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
+       #define CONFIG_QCA_GPIO_MASK_IN         GPIO16 | GPIO17
+       #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
 #elif defined(CONFIG_FOR_TPLINK_WDR3500_V1)
 
        #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11 | GPIO13 | GPIO14 |\
@@ -58,6 +67,17 @@
        #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO12 |\
                                                CONFIG_QCA_GPIO_MASK_LED_ACT_L
 
+#elif defined(CONFIG_FOR_TPLINK_WDR3600_V1) ||\
+      defined(CONFIG_FOR_TPLINK_WDR43X0_V1)
+
+       #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11 | GPIO12 | GPIO13 |\
+                                               GPIO14 | GPIO15
+       #define CONFIG_QCA_GPIO_MASK_OUT        GPIO21 | GPIO22 |\
+                                               CONFIG_QCA_GPIO_MASK_LED_ACT_L
+       #define CONFIG_QCA_GPIO_MASK_IN         GPIO16 | GPIO17
+       #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO21 | GPIO22 |\
+                                               CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
 #elif defined(CONFIG_FOR_TPLINK_WR1041N_V2)
 
        #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11 | GPIO12 | GPIO13
@@ -65,17 +85,6 @@
        #define CONFIG_QCA_GPIO_MASK_IN         GPIO14
        #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
 
-#elif defined(CONFIG_FOR_TPLINK_MR3420_V2)
-
-       #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11 | GPIO12 | GPIO13 |\
-                                               GPIO14 | GPIO15 | GPIO18 |\
-                                               GPIO19 | GPIO20 | GPIO21
-       #define CONFIG_QCA_GPIO_MASK_OUT        GPIO4 |\
-                                               CONFIG_QCA_GPIO_MASK_LED_ACT_L
-       #define CONFIG_QCA_GPIO_MASK_IN         GPIO16 | GPIO17
-       #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO4 |\
-                                               CONFIG_QCA_GPIO_MASK_LED_ACT_L
-
 #elif defined(CONFIG_FOR_TPLINK_WR841N_V8)
 
        #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO12 | GPIO13 | GPIO14 |\
@@ -85,15 +94,6 @@
        #define CONFIG_QCA_GPIO_MASK_IN         GPIO16 | GPIO17
        #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
 
-#elif defined(CONFIG_FOR_TPLINK_WA801ND_V2) ||\
-      defined(CONFIG_FOR_TPLINK_WA830RE_V2)
-
-       #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13 | GPIO14 | GPIO15 |\
-                                               GPIO18
-       #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
-       #define CONFIG_QCA_GPIO_MASK_IN         GPIO16 | GPIO17
-       #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
-
 #elif defined(CONFIG_FOR_YUNCORE_CPE870)
 
        #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO0 | GPIO1  | GPIO2  |\
@@ -151,13 +151,21 @@
  * =============================
  */
 #if defined(CONFIG_FOR_ENGENIUS_ENS202EXT)
+
        #define CFG_LOAD_ADDR           0x9F0A0000
+
 #elif defined(CONFIG_FOR_GLINET_GL_AR300)
+
        #define CFG_LOAD_ADDR           0x9F050000
+
 #elif defined(CONFIG_FOR_YUNCORE_CPE870)
+
        #define CFG_LOAD_ADDR           0x9F680000
+
 #else
+
        #define CFG_LOAD_ADDR           0x9F020000
+
 #endif
 
 #define CONFIG_BOOTCOMMAND     "bootm " MK_STR(CFG_LOAD_ADDR)
@@ -168,21 +176,29 @@
  * =========================
  */
 #if defined(CONFIG_FOR_ENGENIUS_ENS202EXT)
+
        #define CFG_ENV_ADDR            0x9F040000
        #define CFG_ENV_SIZE            0x10000
        #define CFG_ENV_SECT_SIZE       0x10000
+
 #elif defined(CONFIG_FOR_GLINET_GL_AR300)
+
        #define CFG_ENV_ADDR            0x9F040000
        #define CFG_ENV_SIZE            0xFC00
        #define CFG_ENV_SECT_SIZE       0x10000
+
 #elif defined(CONFIG_FOR_YUNCORE_CPE870)
+
        #define CFG_ENV_ADDR            0x9F020000
        #define CFG_ENV_SIZE            0xFC00
        #define CFG_ENV_SECT_SIZE       0x10000
+
 #else
+
        #define CFG_ENV_ADDR            0x9F01EC00
        #define CFG_ENV_SIZE            0x1000
        #define CFG_ENV_SECT_SIZE       0x10000
+
 #endif
 
 /*
@@ -201,15 +217,19 @@
  */
 #if defined(CONFIG_FOR_GLINET_GL_AR300) ||\
     defined(CONFIG_FOR_YUNCORE_CPE870)
+
        #define OFFSET_MAC_DATA_BLOCK           0xFF0000
        #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
        #define OFFSET_MAC_ADDRESS              0x000000
+
 #else
+
        #define OFFSET_MAC_DATA_BLOCK           0x010000
        #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
        #define OFFSET_MAC_ADDRESS              0x00FC00
        #define OFFSET_ROUTER_MODEL             0x00FD00
        #define OFFSET_PIN_NUMBER               0x00FE00
+
 #endif
 
 /*
@@ -223,6 +243,7 @@
  * disable some commands
  */
 #if defined(CONFIG_FOR_YUNCORE_CPE870)
+
        #undef CONFIG_CMD_DHCP
        #undef CONFIG_CMD_IMI
        #undef CONFIG_CMD_LOADB
@@ -230,6 +251,7 @@
        #undef CONFIG_CMD_SNTP
        #undef CONFIG_UPG_SCRIPTS_FW
        #undef CONFIG_UPG_SCRIPTS_UBOOT
+
 #endif
 
 /*
@@ -238,20 +260,32 @@
  * ===========================
  */
 #if defined(CONFIG_FOR_YUNCORE_CPE870)
+
        #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS       CFG_FLASH_BASE + 0x20000
+
 #else
+
        #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS       CFG_LOAD_ADDR
+
 #endif
 
 /* Firmware size limit */
 #if defined(CONFIG_FOR_ENGENIUS_ENS202EXT)
+
        #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (2752 * 1024)
+
 #elif defined(CONFIG_FOR_GLINET_GL_AR300)
+
        #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (384 * 1024)
+
 #elif defined(CONFIG_FOR_YUNCORE_CPE870)
+
        #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (256 * 1024)
+
 #else
+
        #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
+
 #endif
 
 /*
@@ -269,9 +303,9 @@
 #elif defined(CONFIG_FOR_TPLINK_MR3420_V2)  ||\
       defined(CONFIG_FOR_TPLINK_WA801ND_V2) ||\
       defined(CONFIG_FOR_TPLINK_WA830RE_V2) ||\
+      defined(CONFIG_FOR_TPLINK_WDR3500_V1) ||\
       defined(CONFIG_FOR_TPLINK_WDR3600_V1) ||\
       defined(CONFIG_FOR_TPLINK_WDR43X0_V1) ||\
-      defined(CONFIG_FOR_TPLINK_WDR3500_V1) ||\
       defined(CONFIG_FOR_TPLINK_WR1041N_V2) ||\
       defined(CONFIG_FOR_TPLINK_WR841N_V8)  ||\
       defined(CONFIG_FOR_YUNCORE_CPE870)
@@ -289,11 +323,15 @@
 #if !defined(CONFIG_FOR_ENGENIUS_ENS202EXT) &&\
     !defined(CONFIG_FOR_GLINET_GL_AR300)    &&\
     !defined(CONFIG_FOR_YUNCORE_CPE870)
+
        #define CONFIG_UPG_UBOOT_SIZE_BACKUP_HEX        0x20000
+
 #endif
 
 #if defined(CONFIG_FOR_YUNCORE_CPE870)
+
        #define CONFIG_UPG_SCRIPTS_FW_ADDR_HEX  0x9F020000
+
 #endif
 
 /*