arm: amlogic: p212: Add support for Ethernet with Internal PHY
authorNeil Armstrong <narmstrong@baylibre.com>
Wed, 18 Oct 2017 08:02:12 +0000 (10:02 +0200)
committerTom Rini <trini@konsulko.com>
Fri, 17 Nov 2017 12:44:13 +0000 (07:44 -0500)
This patch adds support for the Internal RMII Ethernet PHY on the
Amlogic P212 Reference Board.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
board/amlogic/p212/p212.c
configs/p212_defconfig
include/configs/p212.h

index 1eeb7f26d8874fcc1ca86d963bb0469b6f24994e..ece8096c5cc2cf6e0ef0e4de87abe157bb5c9fa0 100644 (file)
@@ -9,6 +9,13 @@
 #include <dm.h>
 #include <asm/io.h>
 #include <asm/arch/gxbb.h>
+#include <asm/arch/sm.h>
+#include <phy.h>
+
+#define EFUSE_SN_OFFSET                20
+#define EFUSE_SN_SIZE          16
+#define EFUSE_MAC_OFFSET       52
+#define EFUSE_MAC_SIZE         6
 
 int board_init(void)
 {
@@ -17,5 +24,35 @@ int board_init(void)
 
 int misc_init_r(void)
 {
-       return 0;
+       u8 mac_addr[EFUSE_MAC_SIZE];
+       char serial[EFUSE_SN_SIZE];
+       ssize_t len;
+
+       /* Set RMII mode */
+       out_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_INVERT_RMII_CLK |
+                                GXBB_ETH_REG_0_CLK_EN);
+
+       /* Use Internal PHY */
+       out_le32(GXBB_ETH_REG_2, 0x10110181);
+       out_le32(GXBB_ETH_REG_3, 0xe40908ff);
+
+       /* Enable power and clock gate */
+       setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
+       clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
+
+       if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+               len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+                                         mac_addr, EFUSE_MAC_SIZE);
+               if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+                       eth_env_set_enetaddr("ethaddr", mac_addr);
+       }
+
+       if (!env_get("serial#")) {
+               len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
+                       EFUSE_SN_SIZE);
+               if (len == EFUSE_SN_SIZE)
+                       env_set("serial#", serial);
+       }
+
+       return 0;
 }
index 3c576218a9de1bb8898b64c666042eabcb36e4e5..d4b534954ee0397f221eab096d7f600e5fb3673e 100644 (file)
@@ -20,6 +20,10 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_MESON_GX=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_MESON_GXL=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_MESON_GXL=y
 CONFIG_DEBUG_UART_MESON=y
index 04773843e40a7af2aa256874c5b28489a9970cde..793b556800375c65858f2601d5a18e3be70be51d 100644 (file)
@@ -12,6 +12,8 @@
 
 #define CONFIG_MISC_INIT_R
 
+#define CONFIG_PHY_ADDR                8
+
 /* Serial setup */
 #define CONFIG_CONS_INDEX              0