clk: imx: add i.IMXRT1020 clk driver

Add i.MXRT1020 clk driver support.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>

diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 059bc2fbb955b60aa246d7a7120a87f42027b827..96721bcbf3b0b74cdcce0b133b5515751b8c74a2 100644 (file)
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -69,6 +69,22 @@ config CLK_IMX8MP
        help
          This enables support clock driver for i.MX8MP platforms.
 
+config SPL_CLK_IMXRT1020
+       bool "SPL clock support for i.MXRT1020"
+       depends on ARCH_IMXRT && SPL
+       select SPL_CLK
+       select SPL_CLK_CCF
+       help
+         This enables SPL DM/DTS support for clock driver in i.MXRT1020
+
+config CLK_IMXRT1020
+       bool "Clock support for i.MXRT1020"
+       depends on ARCH_IMXRT
+       select CLK
+       select CLK_CCF
+       help
+         This enables support clock driver for i.MXRT1020 platforms.
+
 config SPL_CLK_IMXRT1050
        bool "SPL clock support for i.MXRT1050"
        depends on ARCH_IMXRT && SPL

diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 1e8a49d0f3309d0f48e4f48edbed0577a53f6cc4..01bbbdf3aea275294de8ec5d24a501b2f3d4c832 100644 (file)
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -17,4 +17,5 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \
 obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
                                clk-composite-8m.o
 
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
 obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o

diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c
new file mode 100644 (file)
index 0000000..840f783
--- /dev/null
+++ b/drivers/clk/imx/clk-imxrt1020.c
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2020
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <dt-bindings/clock/imxrt1020-clock.h>
+
+#include "clk.h"
+
+static ulong imxrt1020_clk_get_rate(struct clk *clk)
+{
+       struct clk *c;
+       int ret;
+
+       debug("%s(#%lu)\n", __func__, clk->id);
+
+       ret = clk_get_by_id(clk->id, &c);
+       if (ret)
+               return ret;
+
+       return clk_get_rate(c);
+}
+
+static ulong imxrt1020_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+       struct clk *c;
+       int ret;
+
+       debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+       ret = clk_get_by_id(clk->id, &c);
+       if (ret)
+               return ret;
+
+       return clk_set_rate(c, rate);
+}
+
+static int __imxrt1020_clk_enable(struct clk *clk, bool enable)
+{
+       struct clk *c;
+       int ret;
+
+       debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+       ret = clk_get_by_id(clk->id, &c);
+       if (ret)
+               return ret;
+
+       if (enable)
+               ret = clk_enable(c);
+       else
+               ret = clk_disable(c);
+
+       return ret;
+}
+
+static int imxrt1020_clk_disable(struct clk *clk)
+{
+       return __imxrt1020_clk_enable(clk, 0);
+}
+
+static int imxrt1020_clk_enable(struct clk *clk)
+{
+       return __imxrt1020_clk_enable(clk, 1);
+}
+
+static struct clk_ops imxrt1020_clk_ops = {
+       .set_rate = imxrt1020_clk_set_rate,
+       .get_rate = imxrt1020_clk_get_rate,
+       .enable = imxrt1020_clk_enable,
+       .disable = imxrt1020_clk_disable,
+};
+
+static const char * const pll2_bypass_sels[] = {"pll2_sys", "osc", };
+static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "osc", };
+
+static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd3_297m", "pll3_pfd3_454_74m", "arm_podf", };
+static const char *const periph_sels[] = { "pre_periph_sel", "todo", };
+static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
+static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
+static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", };
+static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
+
+static int imxrt1020_clk_probe(struct udevice *dev)
+{
+       void *base;
+
+       /* Anatop clocks */
+       base = (void *)ANATOP_BASE_ADDR;
+
+       clk_dm(IMXRT1020_CLK_PLL2_SYS,
+              imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
+                            base + 0x30, 0x1));
+       clk_dm(IMXRT1020_CLK_PLL3_USB_OTG,
+              imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
+                            base + 0x10, 0x1));
+
+       /* PLL bypass out */
+       clk_dm(IMXRT1020_CLK_PLL2_BYPASS,
+              imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
+                                pll2_bypass_sels,
+                                ARRAY_SIZE(pll2_bypass_sels),
+                                CLK_SET_RATE_PARENT));
+       clk_dm(IMXRT1020_CLK_PLL3_BYPASS,
+              imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
+                                pll3_bypass_sels,
+                                ARRAY_SIZE(pll3_bypass_sels),
+                                CLK_SET_RATE_PARENT));
+
+       clk_dm(IMXRT1020_CLK_PLL3_80M,
+              imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6));
+
+       clk_dm(IMXRT1020_CLK_PLL2_PFD0_352M,
+              imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
+       clk_dm(IMXRT1020_CLK_PLL2_PFD1_594M,
+              imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base + 0x100, 1));
+       clk_dm(IMXRT1020_CLK_PLL2_PFD2_396M,
+              imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base + 0x100, 2));
+       clk_dm(IMXRT1020_CLK_PLL2_PFD3_297M,
+              imx_clk_pfd("pll2_pfd3_297m", "pll2_sys", base + 0x100, 3));
+       clk_dm(IMXRT1020_CLK_PLL3_PFD1_664_62M,
+              imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base + 0xf0, 1));
+       clk_dm(IMXRT1020_CLK_PLL3_PFD3_454_74M,
+              imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base + 0xf0, 3));
+
+       /* CCM clocks */
+       base = dev_read_addr_ptr(dev);
+       if (base == (void *)FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       clk_dm(IMXRT1020_CLK_PRE_PERIPH_SEL,
+              imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
+                          pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
+       clk_dm(IMXRT1020_CLK_PERIPH_SEL,
+              imx_clk_mux("periph_sel", base + 0x14, 25, 1,
+                          periph_sels, ARRAY_SIZE(periph_sels)));
+       clk_dm(IMXRT1020_CLK_USDHC1_SEL,
+              imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
+                          usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+       clk_dm(IMXRT1020_CLK_USDHC2_SEL,
+              imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
+                          usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+       clk_dm(IMXRT1020_CLK_LPUART_SEL,
+              imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
+                          lpuart_sels, ARRAY_SIZE(lpuart_sels)));
+       clk_dm(IMXRT1020_CLK_SEMC_ALT_SEL,
+              imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
+                          semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
+       clk_dm(IMXRT1020_CLK_SEMC_SEL,
+              imx_clk_mux("semc_sel", base + 0x14, 6, 1,
+                          semc_sels, ARRAY_SIZE(semc_sels)));
+
+       clk_dm(IMXRT1020_CLK_AHB_PODF,
+              imx_clk_divider("ahb_podf", "periph_sel",
+                              base + 0x14, 10, 3));
+       clk_dm(IMXRT1020_CLK_USDHC1_PODF,
+              imx_clk_divider("usdhc1_podf", "usdhc1_sel",
+                              base + 0x24, 11, 3));
+       clk_dm(IMXRT1020_CLK_USDHC2_PODF,
+              imx_clk_divider("usdhc2_podf", "usdhc2_sel",
+                              base + 0x24, 16, 3));
+       clk_dm(IMXRT1020_CLK_LPUART_PODF,
+              imx_clk_divider("lpuart_podf", "lpuart_sel",
+                              base + 0x24, 0, 6));
+       clk_dm(IMXRT1020_CLK_SEMC_PODF,
+              imx_clk_divider("semc_podf", "semc_sel",
+                              base + 0x14, 16, 3));
+
+       clk_dm(IMXRT1020_CLK_USDHC1,
+              imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
+       clk_dm(IMXRT1020_CLK_USDHC2,
+              imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
+       clk_dm(IMXRT1020_CLK_LPUART1,
+              imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
+       clk_dm(IMXRT1020_CLK_SEMC,
+              imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
+
+#ifdef CONFIG_SPL_BUILD
+       struct clk *clk, *clk1;
+
+       clk_get_by_id(IMXRT1020_CLK_SEMC_SEL, &clk1);
+       clk_get_by_id(IMXRT1020_CLK_SEMC_ALT_SEL, &clk);
+       clk_set_parent(clk1, clk);
+
+       /* Configure PLL3_USB_OTG to 480MHz */
+       clk_get_by_id(IMXRT1020_CLK_PLL3_USB_OTG, &clk);
+       clk_enable(clk);
+       clk_set_rate(clk, 480000000UL);
+
+       clk_get_by_id(IMXRT1020_CLK_PLL3_BYPASS, &clk1);
+       clk_set_parent(clk1, clk);
+
+       clk_get_by_id(IMXRT1020_CLK_PLL2_PFD3_297M, &clk);
+       clk_set_rate(clk, 297000000UL);
+
+       clk_get_by_id(IMXRT1020_CLK_PLL2_SYS, &clk);
+       clk_enable(clk);
+       clk_set_rate(clk, 528000000UL);
+
+       clk_get_by_id(IMXRT1020_CLK_PLL2_BYPASS, &clk1);
+       clk_set_parent(clk1, clk);
+
+#endif
+
+       return 0;
+}
+
+static const struct udevice_id imxrt1020_clk_ids[] = {
+       { .compatible = "fsl,imxrt1020-ccm" },
+       { },
+};
+
+U_BOOT_DRIVER(imxrt1020_clk) = {
+       .name = "clk_imxrt1020",
+       .id = UCLASS_CLK,
+       .of_match = imxrt1020_clk_ids,
+       .ops = &imxrt1020_clk_ops,
+       .probe = imxrt1020_clk_probe,
+       .flags = DM_FLAG_PRE_RELOC,
+};

diff --git a/include/dt-bindings/clock/imxrt1020-clock.h b/include/dt-bindings/clock/imxrt1020-clock.h
new file mode 100644 (file)
index 0000000..8362443
--- /dev/null
+++ b/include/dt-bindings/clock/imxrt1020-clock.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2020
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMXRT1020_H
+#define __DT_BINDINGS_CLOCK_IMXRT1020_H
+
+#define IMXRT1020_CLK_DUMMY                    0
+#define IMXRT1020_CLK_CKIL                     1
+#define IMXRT1020_CLK_CKIH                     2
+#define IMXRT1020_CLK_OSC                      3
+#define IMXRT1020_CLK_PLL2_PFD0_352M           4
+#define IMXRT1020_CLK_PLL2_PFD1_594M           5
+#define IMXRT1020_CLK_PLL2_PFD2_396M           6
+#define IMXRT1020_CLK_PLL2_PFD3_297M           7
+#define IMXRT1020_CLK_PLL3_PFD0_720M           8
+#define IMXRT1020_CLK_PLL3_PFD1_664_62M                9
+#define IMXRT1020_CLK_PLL3_PFD2_508_24M                10
+#define IMXRT1020_CLK_PLL3_PFD3_454_74M                11
+#define IMXRT1020_CLK_PLL2_198M                        12
+#define IMXRT1020_CLK_PLL3_120M                        13
+#define IMXRT1020_CLK_PLL3_80M                 14
+#define IMXRT1020_CLK_PLL3_60M                 15
+#define IMXRT1020_CLK_PLL2_BYPASS              16
+#define IMXRT1020_CLK_PLL3_BYPASS              17
+#define IMXRT1020_CLK_PLL6_BYPASS              18
+#define IMXRT1020_CLK_PRE_PERIPH_SEL           19
+#define IMXRT1020_CLK_PERIPH_SEL               20
+#define IMXRT1020_CLK_SEMC_ALT_SEL             21
+#define IMXRT1020_CLK_SEMC_SEL                 22
+#define IMXRT1020_CLK_USDHC1_SEL               23
+#define IMXRT1020_CLK_USDHC2_SEL               24
+#define IMXRT1020_CLK_LPUART_SEL               25
+#define IMXRT1020_CLK_ARM_PODF                 26
+#define IMXRT1020_CLK_LPUART_PODF              27
+#define IMXRT1020_CLK_USDHC1_PODF              28
+#define IMXRT1020_CLK_USDHC2_PODF              29
+#define IMXRT1020_CLK_SEMC_PODF                        30
+#define IMXRT1020_CLK_AHB_PODF                 31
+#define IMXRT1020_CLK_USDHC1                   32
+#define IMXRT1020_CLK_USDHC2                   33
+#define IMXRT1020_CLK_LPUART1                  34
+#define IMXRT1020_CLK_SEMC                     35
+#define IMXRT1020_CLK_PLL2_SYS                 36
+#define IMXRT1020_CLK_PLL3_USB_OTG             37
+#define IMXRT1020_CLK_PLL4_AUDIO               38
+#define IMXRT1020_CLK_PLL6_ENET                        39
+#define IMXRT1020_CLK_END                      40
+
+#endif /* __DT_BINDINGS_CLOCK_IMXRT1020_H */