m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
authorAnton Staaf <robotboy@chromium.org>
Mon, 17 Oct 2011 23:46:04 +0000 (16:46 -0700)
committerWolfgang Denk <wd@denx.de>
Sun, 23 Oct 2011 18:50:42 +0000 (20:50 +0200)
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Jason Jin <jason.jin@freescale.com>
arch/m68k/include/asm/cache.h

index 7c84e4847119be2665fb8ba418f17f54b8c070b7..5c9bb308356b397075eb2cf22470468e68cb42e8 100644 (file)
@@ -207,4 +207,14 @@ void dcache_invalid(void);
 
 #endif
 
+/*
+ * m68k uses 16 byte L1 data cache line sizes.  Use this for DMA buffer
+ * alignment unless the board configuration has specified a new value.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN      CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN      16
+#endif
+
 #endif                         /* __CACHE_H */