Move DDR_RD_DATA_THIS_CYCLE reg setup in new AR933x dram init code before timing...

diff --git a/u-boot/cpu/mips/ar7240/ar933x_dram.c b/u-boot/cpu/mips/ar7240/ar933x_dram.c
index 7d0ecbda2b39f8ad3101dda225c19672bfaf50d2..05fbc3ecc0ce3bda104d0e4d07af8e6d52fa00ec 100644 (file)
--- a/u-boot/cpu/mips/ar7240/ar933x_dram.c
+++ b/u-boot/cpu/mips/ar7240/ar933x_dram.c
@@ -153,6 +153,9 @@ void qca_dram_init(void)
 {
        u32 mem_type = qca_dram_type();
 
+       /* AR933x supports only 16-bit memory */
+       qca_soc_reg_write(QCA_DDR_RD_DATA_THIS_CYCLE_REG, 0xFF);
+
        /* DDR timings (if not defined, use values from old SDK code) */
 #ifdef CONFIG_QCA_DDR_CFG_REG_VAL
        qca_soc_reg_write(QCA_DDR_CFG_REG, CONFIG_QCA_DDR_CFG_REG_VAL);
@@ -178,9 +181,6 @@ void qca_dram_init(void)
                                          _qca_ddr_cfg2_reg_val(0, 1, 0, 1, 6, 14, 8, 14, 7, 1));
 #endif
 
-       /* AR933x supports only 16-bit memory */
-       qca_soc_reg_write(QCA_DDR_RD_DATA_THIS_CYCLE_REG, 0xFF);
-
        if (mem_type == RAM_MEMORY_TYPE_SDR) {
                /* Enable SDR */
                qca_soc_reg_write(QCA_SDR_CFG_REG, 1);