powerpc/c29xpcie: add support for C29XPCIE board
authorMingkai Hu <Mingkai.Hu@freescale.com>
Thu, 4 Jul 2013 09:33:43 +0000 (17:33 +0800)
committerYork Sun <yorksun@freescale.com>
Fri, 9 Aug 2013 19:41:42 +0000 (12:41 -0700)
C29XPCIE board is a series of Freescale PCIe add-in cards to perform
as public key crypto accelerator or secure key management module. It
includes C293PCIE board, C293PCIE board and C291PCIE board.

 - 512KB platform SRAM in addition to 512K L2 Cache/SRAM
 - 512MB soldered DDR3 32bit memory
 - CPLD System Logic
 - 64MB x16 NOR flash and 4GB x8 NAND flash
 - 16MB SPI flash

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Singed-off-by: Po Liu <Po.Liu@freescale.com>
[yorksun: Fixup include/configs/C29XPCIE.h]
Signed-off-by: York Sun <yorksun@freescale.com>
MAINTAINERS
board/freescale/c29xpcie/Makefile [new file with mode: 0644]
board/freescale/c29xpcie/c29xpcie.c [new file with mode: 0644]
board/freescale/c29xpcie/cpld.c [new file with mode: 0644]
board/freescale/c29xpcie/cpld.h [new file with mode: 0644]
board/freescale/c29xpcie/ddr.c [new file with mode: 0644]
board/freescale/c29xpcie/law.c [new file with mode: 0644]
board/freescale/c29xpcie/tlb.c [new file with mode: 0644]
boards.cfg
include/configs/C29XPCIE.h [new file with mode: 0644]

index 2798f1379f412255f62aee94109a9add71758a18..23a17c30fa20d23e4ac81e5d3f77c6a904654b8d 100644 (file)
@@ -543,6 +543,10 @@ Detlev Zundel <dzu@denx.de>
 
        inka4x0         MPC5200
 
+Po Liu <po.liu@freescale.com>
+
+       C29XPCIE        C29X
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
new file mode 100644 (file)
index 0000000..15bef9a
--- /dev/null
@@ -0,0 +1,34 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS-y        += $(BOARD).o
+COBJS-y        += cpld.o
+COBJS-y        += ddr.o
+COBJS-y        += law.o
+COBJS-y        += tlb.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
new file mode 100644 (file)
index 0000000..acc59d2
--- /dev/null
@@ -0,0 +1,151 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <pci.h>
+#include <asm/fsl_ifc.h>
+#include <asm/fsl_pci.h>
+
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+       struct cpu_type *cpu = gd->arch.cpu;
+       struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+       printf("Board: %sPCIe, ", cpu->name);
+       printf("CPLD Ver: 0x%02x\n", in_8(&cpld_data->cpldver));
+
+       return 0;
+}
+
+int board_early_init_f(void)
+{
+       struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+
+       /* Clock configuration to access CPLD using IFC(GPCM) */
+       setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+       return 0;
+}
+
+int board_early_init_r(void)
+{
+       const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
+       const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+       /*
+        * Remap Boot flash region to caching-inhibited
+        * so that flash can be erased properly.
+        */
+
+       /* Flush d-cache and invalidate i-cache of any FLASH data */
+       flush_dcache();
+       invalidate_icache();
+
+       /* invalidate existing TLB entry for flash */
+       disable_tlb(flash_esel);
+
+       set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, flash_esel, BOOKE_PAGESZ_64M, 1);
+
+       return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+       fsl_pcie_init_board(0);
+}
+#endif /* ifdef CONFIG_PCI */
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+       struct fsl_pq_mdio_info mdio_info;
+       struct tsec_info_struct tsec_info[2];
+       int num = 0;
+
+#ifdef CONFIG_TSEC1
+       SET_STD_TSEC_INFO(tsec_info[num], 1);
+       num++;
+#endif
+#ifdef CONFIG_TSEC2
+       SET_STD_TSEC_INFO(tsec_info[num], 2);
+       num++;
+#endif
+       if (!num) {
+               printf("No TSECs initialized\n");
+               return 0;
+       }
+
+       /* Register 1G MDIO bus */
+       mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+       mdio_info.name = DEFAULT_MII_NAME;
+
+       fsl_pq_mdio_init(bis, &mdio_info);
+
+       tsec_eth_init(bis, tsec_info, num);
+
+       return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void fdt_del_sec(void *blob, int offset)
+{
+       int nodeoff = 0;
+
+       while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
+                       CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
+                       + offset * 0x20000)) >= 0) {
+               fdt_del_node(blob, nodeoff);
+               offset++;
+       }
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+       phys_addr_t base;
+       phys_size_t size;
+       struct cpu_type *cpu;
+
+       cpu = gd->arch.cpu;
+
+       ft_cpu_setup(blob, bd);
+
+       base = getenv_bootm_low();
+       size = getenv_bootm_size();
+
+#if defined(CONFIG_PCI)
+       FT_FSL_PCI_SETUP;
+#endif
+
+       fdt_fixup_memory(blob, (u64)base, (u64)size);
+       if (cpu->soc_ver == SVR_C291)
+               fdt_del_sec(blob, 1);
+       else if (cpu->soc_ver == SVR_C292)
+               fdt_del_sec(blob, 2);
+}
+#endif
diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c
new file mode 100644 (file)
index 0000000..b17a7ba
--- /dev/null
@@ -0,0 +1,134 @@
+/**
+ * Copyright 2013 Freescale Semiconductor
+ * Author: Mingkai Hu <Mingkai.hu@freescale.com>
+ *         Po Liu <Po.Liu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This file provides support for the board-specific CPLD used on some Freescale
+ * reference boards.
+ *
+ * The following macros need to be defined:
+ *
+ * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
+ * CPLD register map
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include "cpld.h"
+/**
+ * Set the boot bank to the alternate bank
+ */
+void cpld_set_altbank(u8 banksel)
+{
+       struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+       u8 reg11;
+
+       reg11 = in_8(&cpld_data->flhcsr);
+
+       switch (banksel) {
+       case 1:
+               out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+                       | CPLD_BANKSEL_EN | CPLD_SELECT_BANK1);
+               break;
+       case 2:
+               out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+                       | CPLD_BANKSEL_EN | CPLD_SELECT_BANK2);
+               break;
+       case 3:
+               out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+                       | CPLD_BANKSEL_EN | CPLD_SELECT_BANK3);
+               break;
+       case 4:
+               out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+                       | CPLD_BANKSEL_EN | CPLD_SELECT_BANK4);
+               break;
+       default:
+               printf("Invalid value! [1-4]\n");
+               return;
+       }
+
+       udelay(100);
+       do_reset(NULL, 0, 0, NULL);
+}
+
+/**
+ * Set the boot bank to the default bank
+ */
+void cpld_set_defbank(void)
+{
+       cpld_set_altbank(4);
+}
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+       struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+       printf("chipid1         = 0x%02x\n", in_8(&cpld_data->chipid1));
+       printf("chipid2         = 0x%02x\n", in_8(&cpld_data->chipid2));
+       printf("hwver           = 0x%02x\n", in_8(&cpld_data->hwver));
+       printf("cpldver         = 0x%02x\n", in_8(&cpld_data->cpldver));
+       printf("rstcon          = 0x%02x\n", in_8(&cpld_data->rstcon));
+       printf("flhcsr          = 0x%02x\n", in_8(&cpld_data->flhcsr));
+       printf("wdcsr           = 0x%02x\n", in_8(&cpld_data->wdcsr));
+       printf("wdkick          = 0x%02x\n", in_8(&cpld_data->wdkick));
+       printf("fancsr          = 0x%02x\n", in_8(&cpld_data->fancsr));
+       printf("ledcsr          = 0x%02x\n", in_8(&cpld_data->ledcsr));
+       printf("misc            = 0x%02x\n", in_8(&cpld_data->misccsr));
+       printf("bootor          = 0x%02x\n", in_8(&cpld_data->bootor));
+       printf("bootcfg1        = 0x%02x\n", in_8(&cpld_data->bootcfg1));
+       printf("bootcfg2        = 0x%02x\n", in_8(&cpld_data->bootcfg2));
+       printf("bootcfg3        = 0x%02x\n", in_8(&cpld_data->bootcfg3));
+       printf("bootcfg4        = 0x%02x\n", in_8(&cpld_data->bootcfg4));
+       putc('\n');
+}
+#endif
+
+int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+       int rc = 0;
+       unsigned char value;
+
+       if (argc <= 1)
+               return cmd_usage(cmdtp);
+
+       if (strcmp(argv[1], "reset") == 0) {
+               if (!strcmp(argv[2], "altbank") && argv[3]) {
+                       value = (u8)simple_strtoul(argv[3], NULL, 16);
+                       cpld_set_altbank(value);
+               } else if (!argv[2])
+                       cpld_set_defbank();
+               else
+                       cmd_usage(cmdtp);
+#ifdef DEBUG
+       } else if (strcmp(argv[1], "dump") == 0) {
+               cpld_dump_regs();
+#endif
+       } else
+               rc = cmd_usage(cmdtp);
+
+       return rc;
+}
+
+U_BOOT_CMD(
+       cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
+       "Reset the board using the CPLD sequencer",
+       "reset - hard reset to default bank 4\n"
+       "cpld_cmd reset altbank [bank]- reset to alternate bank\n"
+       "       - [bank] bank value select 1-4\n"
+       "       - bank 1 on the flash 0x0000000~0x0ffffff\n"
+       "       - bank 2 on the flash 0x1000000~0x1ffffff\n"
+       "       - bank 3 on the flash 0x2000000~0x2ffffff\n"
+       "       - bank 4 on the flash 0x3000000~0x3ffffff\n"
+#ifdef DEBUG
+       "cpld_cmd dump - display the CPLD registers\n"
+#endif
+       );
diff --git a/board/freescale/c29xpcie/cpld.h b/board/freescale/c29xpcie/cpld.h
new file mode 100644 (file)
index 0000000..24093c4
--- /dev/null
@@ -0,0 +1,43 @@
+/**
+ * Copyright 2013 Freescale Semiconductor
+ * Author: Mingkai Hu <Mingkai.Hu@freescale.com>
+ *         Po Liu <Po.Liu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/*
+ * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
+ */
+struct cpld_data {
+       u8 chipid1;     /* 0x0 - CPLD Chip ID1 Register */
+       u8 chipid2;     /* 0x1 - CPLD Chip ID2 Register */
+       u8 hwver;       /* 0x2 - Hardware Version Register */
+       u8 cpldver;     /* 0x3 - Software Version Register */
+       u8 res[12];
+       u8 rstcon;      /* 0x10 - Reset control register */
+       u8 flhcsr;      /* 0x11 - Flash control and status Register */
+       u8 wdcsr;       /* 0x12 - Watchdog control and status Register */
+       u8 wdkick;      /* 0x13 - Watchdog kick Register */
+       u8 fancsr;      /* 0x14 - Fan control and status Register */
+       u8 ledcsr;      /* 0x15 - LED control and status Register */
+       u8 misccsr;     /* 0x16 - Misc control and status Register */
+       u8 bootor;      /* 0x17 - Boot configure override Register */
+       u8 bootcfg1;    /* 0x18 - Boot configure 1 Register */
+       u8 bootcfg2;    /* 0x19 - Boot configure 2 Register */
+       u8 bootcfg3;    /* 0x1a - Boot configure 3 Register */
+       u8 bootcfg4;    /* 0x1b - Boot configure 4 Register */
+};
+
+#define CPLD_BANKSEL_EN                0x02
+#define CPLD_BANKSEL_MASK      0x3f
+#define CPLD_SELECT_BANK1      0xc0
+#define CPLD_SELECT_BANK2      0x80
+#define CPLD_SELECT_BANK3      0x40
+#define CPLD_SELECT_BANK4      0x00
diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c
new file mode 100644 (file)
index 0000000..62476ca
--- /dev/null
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+/*
+ * Micron MT41J128M16HA-15E
+ * */
+dimm_params_t ddr_raw_timing = {
+       .n_ranks = 1,
+       .rank_density = 536870912u,
+       .capacity = 536870912u,
+       .primary_sdram_width = 32,
+       .ec_sdram_width = 8,
+       .registered_dimm = 0,
+       .mirrored_dimm = 0,
+       .n_row_addr = 14,
+       .n_col_addr = 10,
+       .n_banks_per_sdram_device = 8,
+       .edc_config = 2,
+       .burst_lengths_bitmask = 0x0c,
+
+       .tCKmin_X_ps = 1650,
+       .caslat_X = 0x7e << 4,  /* 5,6,7,8,9,10 */
+       .tAA_ps = 14050,
+       .tWR_ps = 15000,
+       .tRCD_ps = 13500,
+       .tRRD_ps = 75000,
+       .tRP_ps = 13500,
+       .tRAS_ps = 40000,
+       .tRC_ps = 49500,
+       .tRFC_ps = 160000,
+       .tWTR_ps = 75000,
+       .tRTP_ps = 75000,
+       .refresh_rate_ps = 7800000,
+       .tFAW_ps = 30000,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+               unsigned int controller_number,
+               unsigned int dimm_number)
+{
+       const char dimm_model[] = "Fixed DDR on board";
+
+       if ((controller_number == 0) && (dimm_number == 0)) {
+               memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+               memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+               memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+       }
+
+       return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+                               dimm_params_t *pdimm,
+                               unsigned int ctrl_num)
+{
+       int i;
+       popts->clk_adjust = 2;
+       popts->cpo_override = 0x1f;
+       popts->write_data_delay = 4;
+       popts->half_strength_driver_enable = 1;
+       popts->bstopre = 0x3cf;
+       popts->quad_rank_present = 1;
+       popts->rtt_override = 1;
+       popts->rtt_override_value = 1;
+       popts->dynamic_power = 1;
+       /* Write leveling override */
+       popts->wrlvl_en = 1;
+       popts->wrlvl_override = 1;
+       popts->wrlvl_sample = 0xf;
+       popts->wrlvl_start = 0x4;
+       popts->trwt_override = 1;
+       popts->trwt = 0;
+
+       for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+               popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+               popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+       }
+}
diff --git a/board/freescale/c29xpcie/law.c b/board/freescale/c29xpcie/law.c
new file mode 100644 (file)
index 0000000..10a2fbf
--- /dev/null
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+       SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
+       SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+       SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_16K, LAW_TRGT_IF_IFC),
+       SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K,
+                                       LAW_TRGT_IF_PLATFORM_SRAM),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
new file mode 100644 (file)
index 0000000..a175906
--- /dev/null
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+       /* TLB 0 - for temp stack in cache */
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+                       CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+                       CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+                       CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 0, BOOKE_PAGESZ_4K, 0),
+
+       /* TLB 1 */
+       SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 0, BOOKE_PAGESZ_1M, 1),
+
+       SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+                       MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+                       0, 1, BOOKE_PAGESZ_64M, 1),
+
+#ifdef CONFIG_PCI
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 2, BOOKE_PAGESZ_256M, 1),
+
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 3, BOOKE_PAGESZ_256K, 1),
+#endif
+
+       SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 4, BOOKE_PAGESZ_4K, 1),
+
+       SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 5, BOOKE_PAGESZ_16K, 1),
+
+       SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
+                       CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 6, BOOKE_PAGESZ_256K, 1),
+       SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000,
+                       CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 7, BOOKE_PAGESZ_256K, 1),
+
+#ifdef CONFIG_SYS_RAMBOOT
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
+                       CONFIG_SYS_DDR_SDRAM_BASE,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 8, BOOKE_PAGESZ_256M, 1),
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+                       CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 9, BOOKE_PAGESZ_256M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
index 619a754f4e4b9c4ac510d293f5c6e566306ff411..d6e29fa495ce696b4058ee0ba69943121b7459b3 100644 (file)
@@ -775,6 +775,8 @@ MPC8569MDS_NAND              powerpc     mpc85xx     mpc8569mds          freesca
 MPC8572DS                    powerpc     mpc85xx     mpc8572ds           freescale      -           MPC8572DS
 MPC8572DS_36BIT              powerpc     mpc85xx     mpc8572ds           freescale      -           MPC8572DS:36BIT
 MPC8572DS_NAND               powerpc     mpc85xx     mpc8572ds           freescale      -           MPC8572DS:NAND
+C29XPCIE                     powerpc     mpc85xx     c29xpcie            freescale      -           C29XPCIE:C29XPCIE,36BIT
+C29XPCIE_SPIFLASH            powerpc     mpc85xx     c29xpcie            freescale      -           C29XPCIE:C29XPCIE,36BIT,SPIFLASH
 P1010RDB_36BIT_NAND          powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB,36BIT,NAND
 P1010RDB_36BIT_NAND_SECBOOT  powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB,36BIT,NAND_SECBOOT,SECURE_BOOT
 P1010RDB_36BIT_NOR           powerpc     mpc85xx     p1010rdb            freescale      -           P1010RDB:P1010RDB,36BIT
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
new file mode 100644 (file)
index 0000000..0453688
--- /dev/null
@@ -0,0 +1,472 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * C29XPCIE board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_PHYS_64BIT
+
+#ifdef CONFIG_C29XPCIE
+#define CONFIG_PPC_C29X
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_TEXT_BASE           0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS    0x1107fffc
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE           0xeff80000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE                   /* BOOKE */
+#define CONFIG_E500                    /* BOOKE e500 family */
+#define CONFIG_MPC85xx
+#define CONFIG_FSL_IFC                 /* Enable IFC Support */
+#define CONFIG_SYS_HAS_SERDES          /* common SERDES init code */
+
+#define CONFIG_PCI                     /* Enable PCI/PCIE */
+#ifdef CONFIG_PCI
+#define CONFIG_PCIE1                   /* PCIE controler 1 (slot 1) */
+#define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_PCIE_RESET          /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI resources */
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+
+#define CONFIG_E1000
+
+/*
+ * PCI Windows
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME          "Slot 1"
+#define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000      /* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT       0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
+#define CONFIG_SYS_PCIE1_IO_PHYS       0xfffc00000ull
+
+#define CONFIG_PCI_PNP                 /* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_TSEC_ENET
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_DDR_CLK_FREQ    100000000
+#define CONFIG_SYS_CLK_FREQ    66666666
+
+#define CONFIG_HWCONFIG
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE                        /* toggle L2 cache */
+#define CONFIG_BTB                     /* toggle branch predition */
+
+#define CONFIG_ADDR_STREAMING          /* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP                        1
+#define CONFIG_SYS_NUM_ADDR_MAP                16      /* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START       0x00200000
+#define CONFIG_SYS_MEMTEST_END         0x00400000
+#define CONFIG_PANIC_HANG
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR3
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM         0
+#define SPD_EEPROM_ADDRESS             0x50
+#define CONFIG_SYS_DDR_RAW_TIMING
+
+/* DDR ECC Setup*/
+#define CONFIG_DDR_ECC
+#define CONFIG_MEM_INIT_VALUE          0xDeadBeef
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+
+#define CONFIG_SYS_SDRAM_SIZE          512
+#define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
+#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR     1
+#define CONFIG_CHIP_SELECTS_PER_CTRL   1
+
+#define CONFIG_SYS_CCSRBAR             0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
+
+/* Platform SRAM setting  */
+#define CONFIG_SYS_PLATFORM_SRAM_BASE  0xffb00000
+#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
+                       (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
+#define CONFIG_SYS_PLATFORM_SRAM_SIZE  (512 << 10)
+
+/*
+ * IFC Definitions
+ */
+/* NOR Flash on IFC */
+#define CONFIG_SYS_FLASH_BASE          0xec000000
+#define CONFIG_SYS_MAX_FLASH_SECT      512     /* 64M */
+
+#define CONFIG_SYS_FLASH_BASE_PHYS     (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE_PHYS }
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS     45
+#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* in ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* in ms */
+
+/* 16Bit NOR Flash - S29GL512S10TFI01 */
+#define CONFIG_SYS_NOR_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+                               CSPR_PORT_SIZE_16 | \
+                               CSPR_MSEL_NOR | \
+                               CSPR_V)
+#define CONFIG_SYS_NOR_AMASK   IFC_AMASK(64*1024*1024)
+#define CONFIG_SYS_NOR_CSOR    CSOR_NOR_ADM_SHIFT(4)
+#define CONFIG_SYS_NOR_FTIM0   (FTIM0_NOR_TACSE(0x4) | \
+                               FTIM0_NOR_TEADC(0x5) | \
+                               FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1   (FTIM1_NOR_TACO(0x1e) | \
+                               FTIM1_NOR_TRAD_NOR(0x0f) | \
+                               FTIM1_NOR_TSEQRAD_NOR(0x0f))
+#define CONFIG_SYS_NOR_FTIM2   (FTIM2_NOR_TCS(0x4) | \
+                               FTIM2_NOR_TCH(0x4) | \
+                               FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3   0x0
+
+/* CFI for NOR Flash */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE           0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS      0xfff800000ull
+
+#define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
+
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
+
+/* 8Bit NAND Flash - K9F1G08U0B */
+#define CONFIG_SYS_NAND_CSPR   (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+                               | CSPR_PORT_SIZE_8 \
+                               | CSPR_MSEL_NAND \
+                               | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK  IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+                               | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+                               | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+                               | CSOR_NAND_RAL_2       /* RAL = 2 Bytes */ \
+                               | CSOR_NAND_PGS_2K      /* Page Size = 2k */ \
+                               | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
+                               | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
+#define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x01) | \
+                               FTIM0_NAND_TWP(0x0c)   | \
+                               FTIM0_NAND_TWCHT(0x08) | \
+                               FTIM0_NAND_TWH(0x06))
+#define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x28) | \
+                               FTIM1_NAND_TWBE(0x1d)  | \
+                               FTIM1_NAND_TRR(0x08)   | \
+                               FTIM1_NAND_TRP(0x0c))
+#define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0c) | \
+                               FTIM2_NAND_TREH(0x0a) | \
+                               FTIM2_NAND_TWHRE(0x18))
+#define CONFIG_SYS_NAND_FTIM3  (FTIM3_NAND_TWW(0x04))
+
+#define CONFIG_SYS_NAND_DDR_LAW                11
+
+/* Set up IFC registers for boot location NOR/NAND */
+#define CONFIG_SYS_CSPR0               CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0              CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0               CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0           CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1           CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2           CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3           CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1               CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1              CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1               CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0           CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1           CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2           CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3           CONFIG_SYS_NAND_FTIM3
+
+/* CPLD on IFC, selected by CS2 */
+#define CONFIG_SYS_CPLD_BASE           0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS      (0xf00000000ull \
+                                       | CONFIG_SYS_CPLD_BASE)
+
+#define CONFIG_SYS_CSPR2       (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+                               | CSPR_PORT_SIZE_8 \
+                               | CSPR_MSEL_GPCM \
+                               | CSPR_V)
+#define CONFIG_SYS_AMASK2      IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2       0x0
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0   (FTIM0_GPCM_TACSE(0x0e) | \
+                               FTIM0_GPCM_TEADC(0x0e) | \
+                               FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1   (FTIM1_GPCM_TACO(0x0e) | \
+                               FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2   (FTIM2_GPCM_TCS(0x0e) | \
+                               FTIM2_GPCM_TCH(0x0) | \
+                               FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3   0x0
+
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR       0xffd00000
+#define CONFIG_SYS_INIT_RAM_END                0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END \
+                                               - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN         (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN          (1024 * 1024)
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX      1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK         get_bus_freq(0)
+
+#define CONFIG_SERIAL_MULTI            /* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_SYS_BAUDRATE_TABLE      \
+       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE     /* enable fit_format_{error,warning}() */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED       400000
+#define CONFIG_SYS_FSL_I2C2_SPEED      400000
+#define CONFIG_SYS_FSL_I2C_SLAVE       0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE      0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET      0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET     0x3100
+
+/* I2C EEPROM */
+/* enable read and write access to EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#define CONFIG_CMD_I2C
+
+/* eSPI - Enhanced SPI */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED                10000000
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_NET_MULTI
+#define CONFIG_MII                     /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC        1       /* Allow unregistered phys */
+#define CONFIG_TSEC1           1
+#define CONFIG_TSEC1_NAME      "eTSEC1"
+#define CONFIG_TSEC2           1
+#define CONFIG_TSEC2_NAME      "eTSEC2"
+
+/* Default mode is RGMII mode */
+#define TSEC1_PHY_ADDR         0
+#define TSEC2_PHY_ADDR         2
+
+#define TSEC1_FLAGS            (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS            (TSEC_GIGABIT | TSEC_REDUCED)
+
+#define CONFIG_ETHPRIME                "eTSEC1"
+
+#define CONFIG_PHY_GIGE
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS     0
+#define CONFIG_ENV_SPI_CS      0
+#define CONFIG_ENV_SPI_MAX_HZ  10000000
+#define CONFIG_ENV_SPI_MODE    0
+#define CONFIG_ENV_OFFSET      0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE   0x10000
+#define CONFIG_ENV_SIZE                0x2000
+#endif
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR        0xfff80000
+#else
+#define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SIZE                0x2000
+#define CONFIG_ENV_SECT_SIZE   0x20000
+#endif
+
+#define CONFIG_LOADS_ECHO
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING                 /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE                   /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
+#define CONFIG_SYS_PROMPT      "=> "           /* Monitor Command Prompt */
+
+#define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+                                               /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS     16              /* max number of command args */
+#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ          1000            /* dec freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ   (64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20) /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_ROOTPATH                "/opt/nfsroot"
+#define CONFIG_BOOTFILE                "uImage"
+#define CONFIG_UBOOTPATH       u-boot.bin/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR                1000000
+
+#define CONFIG_BOOTDELAY       -1      /* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE                115200
+
+#define        CONFIG_EXTRA_ENV_SETTINGS                               \
+       "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
+       "netdev=eth0\0"                                         \
+       "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
+       "loadaddr=1000000\0"                            \
+       "consoledev=ttyS0\0"                            \
+       "ramdiskaddr=2000000\0"                         \
+       "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
+       "fdtaddr=c00000\0"                              \
+       "fdtfile=name/of/device-tree.dtb\0"                     \
+       "othbootargs=ramdisk_size=600000\0"             \
+
+#define CONFIG_RAMBOOTCOMMAND                  \
+       "setenv bootargs root=/dev/ram rw "     \
+       "console=$consoledev,$baudrate $othbootargs; "  \
+       "tftp $ramdiskaddr $ramdiskfile;"       \
+       "tftp $loadaddr $bootfile;"             \
+       "tftp $fdtaddr $fdtfile;"               \
+       "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#endif /* __CONFIG_H */