fpga: arria10: Fix error in fpga pin configuration

Pin configuration of the FPGA devicetree block should be done
after core configuration in the arria10 fpga driver.  This fix
corrects the check of status, and ensures that the fpga pin mux
is configured on correct configuration of the core fpga image.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 285280e507fb5f9568fe68218b2b3ce943becc8f..5fb9d6a1911a1148ef5a634759ae5a8ca2d45783 100644 (file)
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -936,10 +936,11 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
        fpgamgr_program_write(rbf_data, rbf_size);
 
        status = fpgamgr_program_finish();
-       if (status) {
-               config_pins(gd->fdt_blob, "fpga");
-               puts("FPGA: Enter user mode.\n");
-       }
+       if (status)
+               return status;
+
+       config_pins(gd->fdt_blob, "fpga");
+       puts("FPGA: Enter user mode.\n");
 
        return status;
 }