ARMv8: Enable all asynchronous abort exceptions taken to EL3

Allow EL3 to handle all the External Abort and SError interrupt
exception occur in all exception levels.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>

diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index d5a7a8bb61cc418baadea9b5bf98200b1a22d158..bb33b4bc892bf2c13ad891fa43ab8e9e92b59599 100644 (file)
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -193,6 +193,10 @@ lr .req    x30
                        SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
                        SCR_EL3_NS_EN)
 #endif
+
+#ifdef CONFIG_ARMV8_EA_EL3_FIRST
+       orr     \tmp, \tmp, #SCR_EL3_EA_EN
+#endif
        msr     scr_el3, \tmp
 
        /* Return to the EL2_SP2 mode from EL3 */

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index c1f87f9caf57a774152243db2b9e75be386e8bc7..aed2e3c51ef4b1a66984794264f7de58af707768 100644 (file)
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -29,6 +29,7 @@
 #define SCR_EL3_HCE_EN         (1 << 8)  /* Hypervisor Call enable          */
 #define SCR_EL3_SMD_DIS                (1 << 7)  /* Secure Monitor Call disable     */
 #define SCR_EL3_RES1           (3 << 4)  /* Reserved, RES1                  */
+#define SCR_EL3_EA_EN          (1 << 3)  /* External aborts taken to EL3    */
 #define SCR_EL3_NS_EN          (1 << 0)  /* EL0 and EL1 in Non-scure state  */
 
 /*