MX5: Introduce a function for setting the chip select size
authorFabio Estevam <fabio.estevam@freescale.com>
Tue, 7 Jun 2011 07:02:52 +0000 (07:02 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Mon, 4 Jul 2011 08:55:26 +0000 (10:55 +0200)
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
arch/arm/cpu/armv7/mx5/soc.c
arch/arm/include/asm/arch-mx5/imx-regs.h
arch/arm/include/asm/arch-mx5/sys_proto.h

index 40b8b5640b3ee87b9abf3e18d246f7d7222eed15..c6106d5210651d1b25576c4b6c1144e3bbb1401b 100644 (file)
@@ -163,6 +163,36 @@ int cpu_mmc_init(bd_t *bis)
 #endif
 }
 
+void set_chipselect_size(int const cs_size)
+{
+       unsigned int reg;
+       struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+       reg = readl(&iomuxc_regs->gpr1);
+
+       switch (cs_size) {
+       case CS0_128:
+               reg &= ~0x7;    /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
+               reg |= 0x5;
+               break;
+       case CS0_64M_CS1_64M:
+               reg &= ~0x3F;   /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
+               reg |= 0x1B;
+               break;
+       case CS0_64M_CS1_32M_CS2_32M:
+               reg &= ~0x1FF;  /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
+               reg |= 0x4B;
+               break;
+       case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
+               reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
+               reg |= 0x249;
+               break;
+       default:
+               printf("Unknown chip select size: %d\n", cs_size);
+               break;
+       }
+
+       writel(reg, &iomuxc_regs->gpr1);
+}
 
 void reset_cpu(ulong addr)
 {
index 1dac6fa1459e62faf9b5bba6b12f7ed77fe24646..9589a62a126786a1937d15cff4fd163ad753daa4 100644 (file)
 #define WDOG_EN                (1 << 8)
 #define WDOG_LIMIT(x)  (((x) & 0x3) << 9)
 
+#define CS0_128                                        0
+#define CS0_64M_CS1_64M                                1
+#define CS0_64M_CS1_32M_CS2_32M                        2
+#define CS0_32M_CS1_32M_CS2_32M_CS3_32M                3
+
 /*
  * Number of GPIO pins per port
  */
index f687503cada3f38884349ff561f66735ed69bc19..ce63675629055be8bffbe865b41e1edc27c14b22 100644 (file)
@@ -27,5 +27,5 @@
 u32 get_cpu_rev(void);
 #define is_soc_rev(rev)        ((get_cpu_rev() & 0xFF) - rev)
 void sdelay(unsigned long);
-
+void set_chipselect_size(int const);
 #endif