tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_ACE_BASE, SZ_1K, 0xE0000000, 4,AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_ACE_BASE, SZ_1K, CFG_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
-#define CFG_ACE_BASE 0xe0000000 /* Xilinx ACE controller - Compact Flash */
+#define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in internal SRAM)