#include "r8a7791-koelsch.dts"
#include "r8a7791-u-boot.dtsi"
+
+&scif0 {
+ u-boot,dm-pre-reloc;
+};
#include "r8a7794-silk.dts"
#include "r8a7794-u-boot.dtsi"
+
+&scif2 {
+ u-boot,dm-pre-reloc;
+};
dma-channels = <2>;
};
+ rpc: rpc@0xee200000 {
+ compatible = "renesas,rpc-r8a7795", "renesas,rpc";
+ reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
+ clocks = <&cpg CPG_MOD 917>;
+ bank-width = <2>;
+ status = "disabled";
+ };
+
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7795";
reg = <0 0xee100000 0 0x2000>;
status = "disabled";
};
+ rpc: rpc@0xee200000 {
+ compatible = "renesas,rpc-r8a7796", "renesas,rpc";
+ reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
+ clocks = <&cpg CPG_MOD 917>;
+ bank-width = <2>;
+ status = "disabled";
+ };
+
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7796";
reg = <0 0xee100000 0 0x2000>;
status = "disabled";
};
+ rpc: rpc@0xee200000 {
+ compatible = "renesas,rpc-r8a77965", "renesas,rpc";
+ reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
+ clocks = <&cpg CPG_MOD 917>;
+ bank-width = <2>;
+ status = "disabled";
+ };
+
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a77965";
reg = <0 0xee100000 0 0x2000>;
aliases {
serial0 = &scif0;
ethernet0 = &avb;
+ spi0 = &rpc;
};
chosen {
};
};
+&rpc {
+ num-cs = <1>;
+ status = "okay";
+ spi-max-frequency = <50000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash0: spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ reg = <0>;
+ status = "okay";
+ };
+};
+
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
};
+
+ rpc: rpc@0xee200000 {
+ compatible = "renesas,rpc-r8a77970", "renesas,rpc";
+ reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
+ clocks = <&cpg CPG_MOD 917>;
+ bank-width = <2>;
+ status = "disabled";
+ };
};
};
#phy-cells = <0>;
status = "disabled";
};
+
+ rpc: rpc@0xee200000 {
+ compatible = "renesas,rpc-r8a77995", "renesas,rpc";
+ reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
+ clocks = <&cpg CPG_MOD 917>;
+ bank-width = <2>;
+ status = "disabled";
+ };
};
};
-/*
- * Device Tree Source for UniPhier LD11 Global Board
- *
- * Copyright (C) 2016-2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- * Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD11 Global Board
+//
+// Copyright (C) 2016-2017 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+// Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
/dts-v1/;
+#include <dt-bindings/gpio/uniphier-gpio.h>
#include "uniphier-ld11.dtsi"
/ {
device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
+
+ dvdd_reg: reg-fixed {
+ compatible = "regulator-fixed";
+ regulator-name = "DVDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ amp_vcc_reg: reg-fixed {
+ compatible = "regulator-fixed";
+ regulator-name = "AMP_VCC";
+ regulator-min-microvolt = <24000000>;
+ regulator-max-microvolt = <24000000>;
+ };
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "UniPhier LD11";
+ widgets = "Headphone", "Headphone Jack";
+ dais = <&i2s_port2
+ &i2s_port3
+ &i2s_port4
+ &spdif_port0
+ &comp_spdif_port0>;
+ };
+
+ spdif-out {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+
+ port@0 {
+ spdif_tx: endpoint {
+ remote-endpoint = <&spdif_hiecout1>;
+ };
+ };
+ };
+
+ comp-spdif-out {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+
+ port@0 {
+ comp_spdif_tx: endpoint {
+ remote-endpoint = <&comp_spdif_hiecout1>;
+ };
+ };
+ };
};
&serial0 {
status = "okay";
};
+&i2s_hpcmout1 {
+ dai-format = "i2s";
+ remote-endpoint = <&tas_speaker>;
+};
+
+&spdif_hiecout1 {
+ remote-endpoint = <&spdif_tx>;
+};
+
+&comp_spdif_hiecout1 {
+ remote-endpoint = <&comp_spdif_tx>;
+};
+
&i2c0 {
status = "okay";
+ tas5707a@1d {
+ compatible = "ti,tas5711";
+ reg = <0x1d>;
+ reset-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 4) GPIO_ACTIVE_LOW>;
+ pdn-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 5) GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ AVDD-supply = <&dvdd_reg>;
+ DVDD-supply = <&dvdd_reg>;
+ PVDD_A-supply = <&_vcc_reg>;
+ PVDD_B-supply = <&_vcc_reg>;
+ PVDD_C-supply = <&_vcc_reg>;
+ PVDD_D-supply = <&_vcc_reg>;
+
+ port@0 {
+ tas_speaker: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&i2s_hpcmout1>;
+ };
+ };
+ };
+
eeprom@50 {
compatible = "st,24c64", "atmel,24c64", "i2c-eeprom";
reg = <0x50>;
status = "okay";
};
+ð {
+ status = "okay";
+ phy-handle = <ðphy>;
+};
+
+&mdio {
+ ethphy: ethphy@1 {
+ reg = <1>;
+ };
+};
+
&nand {
status = "okay";
};
-/*
- * Device Tree Source for UniPhier LD11 Reference Board
- *
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD11 Reference Board
+//
+// Copyright (C) 2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-ld11.dtsi"
&usb2 {
status = "okay";
};
+
+ð {
+ status = "okay";
+ phy-handle = <ðphy>;
+};
+
+&mdio {
+ ethphy: ethphy@1 {
+ reg = <1>;
+ };
+};
-/*
- * Device Tree Source for UniPhier LD11 SoC
- *
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD11 SoC
+//
+// Copyright (C) 2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
<21 217 3>;
};
+ audio@56000000 {
+ compatible = "socionext,uniphier-ld11-aio";
+ reg = <0x56000000 0x80000>;
+ interrupts = <0 144 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_aout1>,
+ <&pinctrl_aoutiec1>;
+ clock-names = "aio";
+ clocks = <&sys_clk 40>;
+ reset-names = "aio";
+ resets = <&sys_rst 40>;
+ #sound-dai-cells = <1>;
+ socionext,syscon = <&soc_glue>;
+
+ i2s_port0: port@0 {
+ i2s_hdmi: endpoint {
+ };
+ };
+
+ i2s_port1: port@1 {
+ i2s_pcmin2: endpoint {
+ };
+ };
+
+ i2s_port2: port@2 {
+ i2s_line: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&evea_line>;
+ };
+ };
+
+ i2s_port3: port@3 {
+ i2s_hpcmout1: endpoint {
+ };
+ };
+
+ i2s_port4: port@4 {
+ i2s_hp: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&evea_hp>;
+ };
+ };
+
+ spdif_port0: port@5 {
+ spdif_hiecout1: endpoint {
+ };
+ };
+
+ src_port0: port@6 {
+ i2s_epcmout2: endpoint {
+ };
+ };
+
+ src_port1: port@7 {
+ i2s_epcmout3: endpoint {
+ };
+ };
+
+ comp_spdif_port0: port@8 {
+ comp_spdif_hiecout1: endpoint {
+ };
+ };
+ };
+
+ codec@57900000 {
+ compatible = "socionext,uniphier-evea";
+ reg = <0x57900000 0x1000>;
+ clock-names = "evea", "exiv";
+ clocks = <&sys_clk 41>, <&sys_clk 42>;
+ reset-names = "evea", "exiv", "adamv";
+ resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
+ #sound-dai-cells = <1>;
+
+ port@0 {
+ evea_line: endpoint {
+ remote-endpoint = <&i2s_line>;
+ };
+ };
+
+ port@1 {
+ evea_hp: endpoint {
+ remote-endpoint = <&i2s_hp>;
+ };
+ };
+ };
+
adamv@57920000 {
compatible = "socionext,uniphier-ld11-adamv",
"simple-mfd", "syscon";
};
};
- soc-glue@5f800000 {
+ soc_glue: soc-glue@5f800000 {
compatible = "socionext,uniphier-ld11-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
};
};
+ eth: ethernet@65000000 {
+ compatible = "socionext,uniphier-ld11-ave4";
+ status = "disabled";
+ reg = <0x65000000 0x8500>;
+ interrupts = <0 66 4>;
+ clocks = <&sys_clk 6>;
+ resets = <&sys_rst 6>;
+ phy-mode = "rmii";
+ local-mac-address = [00 00 00 00 00 00];
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
nand: nand@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
};
#include "uniphier-pinctrl.dtsi"
+
+&pinctrl_aoutiec1 {
+ drive-strength = <4>; /* default: 4mA */
+
+ ao1arc {
+ pins = "AO1ARC";
+ drive-strength = <8>; /* 8mA */
+ };
+};
-/*
- * Device Tree Source for UniPhier LD20 Global Board
- *
- * Copyright (C) 2015-2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- * Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD20 Global Board
+//
+// Copyright (C) 2015-2017 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+// Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
/dts-v1/;
+#include <dt-bindings/gpio/uniphier-gpio.h>
#include "uniphier-ld20.dtsi"
/ {
device_type = "memory";
reg = <0 0x80000000 0 0xc0000000>;
};
+
+ dvdd_reg: reg-fixed {
+ compatible = "regulator-fixed";
+ regulator-name = "DVDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ amp_vcc_reg: reg-fixed {
+ compatible = "regulator-fixed";
+ regulator-name = "AMP_VCC";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "UniPhier LD20";
+ widgets = "Headphone", "Headphone Jack";
+ dais = <&i2s_port2
+ &i2s_port3
+ &i2s_port4
+ &spdif_port0
+ &comp_spdif_port0>;
+ };
+
+ spdif-out {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+
+ port@0 {
+ spdif_tx: endpoint {
+ remote-endpoint = <&spdif_hiecout1>;
+ };
+ };
+ };
+
+ comp-spdif-out {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+
+ port@0 {
+ comp_spdif_tx: endpoint {
+ remote-endpoint = <&comp_spdif_hiecout1>;
+ };
+ };
+ };
};
&serial0 {
status = "okay";
};
+&i2s_hpcmout1 {
+ dai-format = "i2s";
+ remote-endpoint = <&tas_speaker>;
+};
+
+&spdif_hiecout1 {
+ remote-endpoint = <&spdif_tx>;
+};
+
+&comp_spdif_hiecout1 {
+ remote-endpoint = <&comp_spdif_tx>;
+};
+
&i2c0 {
status = "okay";
+
+ tas5707@1b {
+ compatible = "ti,tas5711";
+ reg = <0x1b>;
+ reset-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 0) GPIO_ACTIVE_LOW>;
+ pdn-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 1) GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ AVDD-supply = <&dvdd_reg>;
+ DVDD-supply = <&dvdd_reg>;
+ PVDD_A-supply = <&_vcc_reg>;
+ PVDD_B-supply = <&_vcc_reg>;
+ PVDD_C-supply = <&_vcc_reg>;
+ PVDD_D-supply = <&_vcc_reg>;
+
+ port@0 {
+ tas_speaker: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&i2s_hpcmout1>;
+ };
+ };
+ };
+};
+
+ð {
+ status = "okay";
+ phy-mode = "rmii";
+ pinctrl-0 = <&pinctrl_ether_rmii>;
+ phy-handle = <ðphy>;
+};
+
+&mdio {
+ ethphy: ethphy@1 {
+ reg = <1>;
+ };
};
&nand {
-/*
- * Device Tree Source for UniPhier LD20 Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD20 Reference Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-ld20.dtsi"
&i2c0 {
status = "okay";
};
+
+ð {
+ status = "okay";
+ phy-handle = <ðphy>;
+};
+
+&mdio {
+ ethphy: ethphy@0 {
+ reg = <0>;
+ };
+};
-/*
- * Device Tree Source for UniPhier LD20 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD20 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
<21 217 3>;
};
+ audio@56000000 {
+ compatible = "socionext,uniphier-ld20-aio";
+ reg = <0x56000000 0x80000>;
+ interrupts = <0 144 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_aout1>,
+ <&pinctrl_aoutiec1>;
+ clock-names = "aio";
+ clocks = <&sys_clk 40>;
+ reset-names = "aio";
+ resets = <&sys_rst 40>;
+ #sound-dai-cells = <1>;
+ socionext,syscon = <&soc_glue>;
+
+ i2s_port0: port@0 {
+ i2s_hdmi: endpoint {
+ };
+ };
+
+ i2s_port1: port@1 {
+ i2s_pcmin2: endpoint {
+ };
+ };
+
+ i2s_port2: port@2 {
+ i2s_line: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&evea_line>;
+ };
+ };
+
+ i2s_port3: port@3 {
+ i2s_hpcmout1: endpoint {
+ };
+ };
+
+ i2s_port4: port@4 {
+ i2s_hp: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&evea_hp>;
+ };
+ };
+
+ spdif_port0: port@5 {
+ spdif_hiecout1: endpoint {
+ };
+ };
+
+ src_port0: port@6 {
+ i2s_epcmout2: endpoint {
+ };
+ };
+
+ src_port1: port@7 {
+ i2s_epcmout3: endpoint {
+ };
+ };
+
+ comp_spdif_port0: port@8 {
+ comp_spdif_hiecout1: endpoint {
+ };
+ };
+ };
+
+ codec@57900000 {
+ compatible = "socionext,uniphier-evea";
+ reg = <0x57900000 0x1000>;
+ clock-names = "evea", "exiv";
+ clocks = <&sys_clk 41>, <&sys_clk 42>;
+ reset-names = "evea", "exiv", "adamv";
+ resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
+ #sound-dai-cells = <1>;
+
+ port@0 {
+ evea_line: endpoint {
+ remote-endpoint = <&i2s_line>;
+ };
+ };
+
+ port@1 {
+ evea_hp: endpoint {
+ remote-endpoint = <&i2s_hp>;
+ };
+ };
+ };
+
adamv@57920000 {
compatible = "socionext,uniphier-ld20-adamv",
"simple-mfd", "syscon";
cap-sd-highspeed;
};
- soc-glue@5f800000 {
+ soc_glue: soc-glue@5f800000 {
compatible = "socionext,uniphier-ld20-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
};
};
+ eth: ethernet@65000000 {
+ compatible = "socionext,uniphier-ld20-ave4";
+ status = "disabled";
+ reg = <0x65000000 0x8500>;
+ interrupts = <0 66 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ether_rgmii>;
+ clocks = <&sys_clk 6>;
+ resets = <&sys_rst 6>;
+ phy-mode = "rgmii";
+ local-mac-address = [00 00 00 00 00 00];
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
usb: usb@65b00000 {
compatible = "socionext,uniphier-ld20-dwc3";
reg = <0x65b00000 0x1000>;
};
#include "uniphier-pinctrl.dtsi"
+
+&pinctrl_aout1 {
+ drive-strength = <4>; /* default: 3.5mA */
+
+ ao1dacck {
+ pins = "AO1DACCK";
+ drive-strength = <5>; /* 5mA */
+ };
+};
+
+&pinctrl_aoutiec1 {
+ drive-strength = <4>; /* default: 3.5mA */
+
+ ao1arc {
+ pins = "AO1ARC";
+ drive-strength = <11>; /* 11mA */
+ };
+};
-/*
- * Device Tree Source for UniPhier LD4 Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD4 Reference Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-ld4.dtsi"
-/*
- * Device Tree Source for UniPhier LD4 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD4 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
-/*
- * Device Tree Source for UniPhier LD6b Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD6b Reference Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-ld6b.dtsi"
status = "okay";
};
+ð {
+ status = "okay";
+ phy-handle = <ðphy>;
+};
+
+&mdio {
+ ethphy: ethphy@0 {
+ reg = <0>;
+ };
+};
+
&usb0 {
status = "okay";
};
-/*
- * Device Tree Source for UniPhier LD6b SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD6b SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/*
* LD6b consists of two silicon dies: D-chip and A-chip.
-/*
- * Device Tree Source for UniPhier SoCs default pinctrl settings
- *
- * Copyright (C) 2015-2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier SoCs default pinctrl settings
+//
+// Copyright (C) 2015-2017 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
&pinctrl {
pinctrl_aout: aout {
function = "aout";
};
+ pinctrl_ain1: ain1 {
+ groups = "ain1";
+ function = "ain1";
+ };
+
+ pinctrl_ain2: ain2 {
+ groups = "ain2";
+ function = "ain2";
+ };
+
+ pinctrl_ainiec1: ainiec1 {
+ groups = "ainiec1";
+ function = "ainiec1";
+ };
+
+ pinctrl_aout1: aout1 {
+ groups = "aout1";
+ function = "aout1";
+ };
+
+ pinctrl_aout2: aout2 {
+ groups = "aout2";
+ function = "aout2";
+ };
+
+ pinctrl_aout3: aout3 {
+ groups = "aout3";
+ function = "aout3";
+ };
+
+ pinctrl_aoutiec1: aoutiec1 {
+ groups = "aoutiec1";
+ function = "aoutiec1";
+ };
+
+ pinctrl_aoutiec2: aoutiec2 {
+ groups = "aoutiec2";
+ function = "aoutiec2";
+ };
+
pinctrl_emmc: emmc {
groups = "emmc", "emmc_dat8";
function = "emmc";
function = "ether_rmii";
};
+ pinctrl_ether1_rgmii: ether1-rgmii {
+ groups = "ether1_rgmii";
+ function = "ether1_rgmii";
+ };
+
+ pinctrl_ether1_rmii: ether1-rmii {
+ groups = "ether1_rmii";
+ function = "ether1_rmii";
+ };
+
pinctrl_i2c0: i2c0 {
groups = "i2c0";
function = "i2c0";
-/*
- * Device Tree Source for UniPhier Pro4 Ace Board
- *
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Pro4 Ace Board
+//
+// Copyright (C) 2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pro4.dtsi"
status = "okay";
};
+ð {
+ status = "okay";
+ phy-handle = <ðphy>;
+};
+
+&mdio {
+ ethphy: ethphy@1 {
+ reg = <1>;
+ };
+};
+
&usb2 {
status = "okay";
};
-/*
- * Device Tree Source for UniPhier Pro4 Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Pro4 Reference Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pro4.dtsi"
status = "okay";
};
+ð {
+ status = "okay";
+ phy-handle = <ðphy>;
+};
+
+&mdio {
+ ethphy: ethphy@0 {
+ reg = <0>;
+ };
+};
+
&usb0 {
status = "okay";
};
-/*
- * Device Tree Source for UniPhier Pro4 Sanji Board
- *
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Pro4 Sanji Board
+//
+// Copyright (C) 2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pro4.dtsi"
status = "okay";
};
+ð {
+ status = "okay";
+ phy-handle = <ðphy>;
+};
+
+&mdio {
+ ethphy: ethphy@1 {
+ reg = <1>;
+ };
+};
+
&usb2 {
status = "okay";
};
-/*
- * Device Tree Source for UniPhier Pro4 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Pro4 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
};
};
+ eth: ethernet@65000000 {
+ compatible = "socionext,uniphier-pro4-ave4";
+ status = "disabled";
+ reg = <0x65000000 0x8500>;
+ interrupts = <0 66 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ether_rgmii>;
+ clocks = <&sys_clk 6>;
+ resets = <&sys_rst 6>;
+ phy-mode = "rgmii";
+ local-mac-address = [00 00 00 00 00 00];
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
usb0: usb@65b00000 {
compatible = "socionext,uniphier-pro4-dwc3";
status = "disabled";
-/*
- * Device Tree Source for UniPhier Pro5 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Pro5 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/ {
compatible = "socionext,uniphier-pro5";
-/*
- * Device Tree Source for UniPhier PXs2 Gentil Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier PXs2 Gentil Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pxs2.dtsi"
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "UniPhier PXs2";
+ dais = <&i2s_port2>;
+ };
};
&serial2 {
};
};
+&i2s_aux {
+ dai-format = "i2s";
+ remote-endpoint = <&wm_speaker>;
+};
+
&i2c2 {
status = "okay";
+
+ wm8960@1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ #sound-dai-cells = <0>;
+
+ port@0 {
+ wm_speaker: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&i2s_aux>;
+ };
+ };
+ };
};
&emmc {
status = "okay";
};
+ð {
+ status = "okay";
+ phy-handle = <ðphy>;
+};
+
+&mdio {
+ ethphy: ethphy@1 {
+ reg = <1>;
+ };
+};
+
&usb0 {
status = "okay";
};
-/*
- * Device Tree Source for UniPhier PXs2 Vodka Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier PXs2 Vodka Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pxs2.dtsi"
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "UniPhier PXs2";
+ dais = <&spdif_port0
+ &comp_spdif_port0>;
+ };
+
+ spdif-out {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+
+ port@0 {
+ spdif_tx: endpoint {
+ remote-endpoint = <&spdif_hiecout1>;
+ };
+ };
+ };
+
+ comp-spdif-out {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+
+ port@0 {
+ comp_spdif_tx: endpoint {
+ remote-endpoint = <&comp_spdif_hiecout1>;
+ };
+ };
+ };
};
&serial2 {
status = "okay";
};
+&spdif_hiecout1 {
+ remote-endpoint = <&spdif_tx>;
+};
+
+&comp_spdif_hiecout1 {
+ remote-endpoint = <&comp_spdif_tx>;
+};
+
&i2c0 {
status = "okay";
};
status = "okay";
};
+ð {
+ status = "okay";
+ phy-handle = <ðphy>;
+};
+
+&mdio {
+ ethphy: ethphy@1 {
+ reg = <1>;
+ };
+};
+
&usb0 {
status = "okay";
};
-/*
- * Device Tree Source for UniPhier PXs2 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier PXs2 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/thermal/thermal.h>
<21 217 3>;
};
+ audio@56000000 {
+ compatible = "socionext,uniphier-pxs2-aio";
+ reg = <0x56000000 0x80000>;
+ interrupts = <0 144 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ain1>,
+ <&pinctrl_ain2>,
+ <&pinctrl_ainiec1>,
+ <&pinctrl_aout2>,
+ <&pinctrl_aout3>,
+ <&pinctrl_aoutiec1>,
+ <&pinctrl_aoutiec2>;
+ clock-names = "aio";
+ clocks = <&sys_clk 40>;
+ reset-names = "aio";
+ resets = <&sys_rst 40>;
+ #sound-dai-cells = <1>;
+ socionext,syscon = <&soc_glue>;
+
+ i2s_port0: port@0 {
+ i2s_hdmi: endpoint {
+ };
+ };
+
+ i2s_port1: port@1 {
+ i2s_line: endpoint {
+ };
+ };
+
+ i2s_port2: port@2 {
+ i2s_aux: endpoint {
+ };
+ };
+
+ spdif_port0: port@3 {
+ spdif_hiecout1: endpoint {
+ };
+ };
+
+ spdif_port1: port@4 {
+ spdif_iecout1: endpoint {
+ };
+ };
+
+ comp_spdif_port0: port@5 {
+ comp_spdif_hiecout1: endpoint {
+ };
+ };
+
+ comp_spdif_port1: port@6 {
+ comp_spdif_iecout1: endpoint {
+ };
+ };
+ };
+
i2c0: i2c@58780000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
sd-uhs-sdr50;
};
- soc-glue@5f800000 {
+ soc_glue: soc-glue@5f800000 {
compatible = "socionext,uniphier-pxs2-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
};
};
+ eth: ethernet@65000000 {
+ compatible = "socionext,uniphier-pxs2-ave4";
+ status = "disabled";
+ reg = <0x65000000 0x8500>;
+ interrupts = <0 66 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ether_rgmii>;
+ clocks = <&sys_clk 6>;
+ resets = <&sys_rst 6>;
+ phy-mode = "rgmii";
+ local-mac-address = [00 00 00 00 00 00];
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
usb0: usb@65b00000 {
compatible = "socionext,uniphier-pxs2-dwc3";
status = "disabled";
-/*
- * Device Tree Source for UniPhier PXs3 Reference Board
- *
- * Copyright (C) 2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier PXs3 Reference Board
+//
+// Copyright (C) 2017 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-pxs3.dtsi"
status = "okay";
};
+ð0 {
+ status = "okay";
+ phy-handle = <ðphy0>;
+};
+
+&mdio0 {
+ ethphy0: ethphy@0 {
+ reg = <0>;
+ };
+};
+
+ð1 {
+ status = "okay";
+ phy-handle = <ðphy1>;
+};
+
+&mdio1 {
+ ethphy1: ethphy@0 {
+ reg = <0>;
+ };
+};
+
&usb0 {
status = "okay";
};
-/*
- * Device Tree Source for UniPhier PXs3 SoC
- *
- * Copyright (C) 2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier PXs3 SoC
+//
+// Copyright (C) 2017 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
cap-sd-highspeed;
};
- soc-glue@5f800000 {
+ soc_glue: soc-glue@5f800000 {
compatible = "socionext,uniphier-pxs3-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
};
};
+ eth0: ethernet@65000000 {
+ compatible = "socionext,uniphier-pxs3-ave4";
+ status = "disabled";
+ reg = <0x65000000 0x8500>;
+ interrupts = <0 66 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ether_rgmii>;
+ clocks = <&sys_clk 6>;
+ resets = <&sys_rst 6>;
+ phy-mode = "rgmii";
+ local-mac-address = [00 00 00 00 00 00];
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ eth1: ethernet@65200000 {
+ compatible = "socionext,uniphier-pxs3-ave4";
+ status = "disabled";
+ reg = <0x65200000 0x8500>;
+ interrupts = <0 67 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ether1_rgmii>;
+ clocks = <&sys_clk 7>;
+ resets = <&sys_rst 7>;
+ phy-mode = "rgmii";
+ local-mac-address = [00 00 00 00 00 00];
+
+ mdio1: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
usb0: usb@65b00000 {
compatible = "socionext,uniphier-pxs3-dwc3";
status = "disabled";
-/*
- * Device Tree Source for UniPhier Reference Daughter Board
- *
- * Copyright (C) 2015-2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Reference Daughter Board
+//
+// Copyright (C) 2015-2017 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
&i2c0 {
eeprom@50 {
-/*
- * Device Tree Source for UniPhier sLD8 Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier sLD8 Reference Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/dts-v1/;
#include "uniphier-sld8.dtsi"
-/*
- * Device Tree Source for UniPhier sLD8 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier sLD8 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
-/*
- * Device Tree Source for UniPhier Support Card (Expansion Board)
- *
- * Copyright (C) 2015-2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Support Card (Expansion Board)
+//
+// Copyright (C) 2015-2017 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
&system_bus {
status = "okay";
u-boot,dm-pre-reloc;
};
- mioctrl@59810000 {
- u-boot,dm-pre-reloc;
-
- clock {
- u-boot,dm-pre-reloc;
- };
- };
-
- sdctrl@59810000 {
- u-boot,dm-pre-reloc;
-
- clock {
- u-boot,dm-pre-reloc;
- };
- };
-
soc-glue@5f800000 {
u-boot,dm-pre-reloc;
bool "Koelsch board"
select DM
select DM_SERIAL
+ select SUPPORT_SPL
+ select USE_TINY_PRINTF
+ select SPL_TINY_MEMSET
config TARGET_LAGER
bool "Lager board"
bool "Silk board"
select DM
select DM_SERIAL
+ select SUPPORT_SPL
+ select USE_TINY_PRINTF
+ select SPL_TINY_MEMSET
config TARGET_PORTER
bool "Porter board"
want to skip ddr init and this option is useful for it.
config SYS_BOARD
+ string "Board name"
default "zynq"
config SYS_VENDOR
+++ /dev/null
-/*
- * Copyright (C) 2017 National Instruments Corp.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <nand.h>
-
-void zynq_nand_init(void);
# SPDX-License-Identifier: GPL-2.0
#
-obj-y := koelsch.o qos.o ../rcar-common/common.o
+ifdef CONFIG_SPL_BUILD
+obj-y := koelsch_spl.o
+else
+obj-y := koelsch.o qos.o
+endif
qos_init();
}
-#define TMU0_MSTP125 (1 << 25)
-#define SCIF0_MSTP721 (1 << 21)
-#define ETHER_MSTP813 (1 << 13)
-
-#define SDHI0_MSTP314 (1 << 14)
-#define SDHI1_MSTP312 (1 << 12)
-#define SDHI2_MSTP311 (1 << 11)
+#define TMU0_MSTP125 BIT(25)
#define SD1CKCR 0xE6150078
#define SD2CKCR 0xE615026C
{
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
- /* SCIF0 */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
-
- /* ETHER */
- mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
-
- /* SDHI */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3,
- SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311);
-
/*
* SD0 clock is set to 97.5MHz by default.
* Set SD1 and SD2 to the 97.5MHz as well.
return 0;
}
-/* LSI pin pull-up control */
-#define PUPR5 0xe6060114
-#define PUPR5_ETH 0x3FFC0000
-#define PUPR5_ETH_MAGIC (1 << 27)
+#define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
+
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- /* Init PFC controller */
- r8a7791_pinmux_init();
-
- /* ETHER Enable */
- gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
- gpio_request(GPIO_FN_ETH_RX_ER, NULL);
- gpio_request(GPIO_FN_ETH_RXD0, NULL);
- gpio_request(GPIO_FN_ETH_RXD1, NULL);
- gpio_request(GPIO_FN_ETH_LINK, NULL);
- gpio_request(GPIO_FN_ETH_REFCLK, NULL);
- gpio_request(GPIO_FN_ETH_MDIO, NULL);
- gpio_request(GPIO_FN_ETH_TXD1, NULL);
- gpio_request(GPIO_FN_ETH_TX_EN, NULL);
- gpio_request(GPIO_FN_ETH_TXD0, NULL);
- gpio_request(GPIO_FN_ETH_MDC, NULL);
- gpio_request(GPIO_FN_IRQ0, NULL);
-
- mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
- gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
- mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
-
- gpio_direction_output(GPIO_GP_5_22, 0);
- mdelay(20);
- gpio_set_value(GPIO_GP_5_22, 1);
- udelay(1);
+ /* Force ethernet PHY out of reset */
+ gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+ gpio_direction_output(ETHERNET_PHY_RESET, 0);
+ mdelay(10);
+ gpio_direction_output(ETHERNET_PHY_RESET, 1);
return 0;
}
-#define CXR24 0xEE7003C0 /* MAC address high register */
-#define CXR25 0xEE7003C8 /* MAC address low register */
-int board_eth_init(bd_t *bis)
+int dram_init(void)
{
-#ifdef CONFIG_SH_ETHER
- int ret = -ENODEV;
- u32 val;
- unsigned char enetaddr[6];
-
- ret = sh_eth_initialize(bis);
- if (!eth_env_get_enetaddr("ethaddr", enetaddr))
- return ret;
-
- /* Set Mac address */
- val = enetaddr[0] << 24 | enetaddr[1] << 16 |
- enetaddr[2] << 8 | enetaddr[3];
- writel(val, CXR24);
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
- val = enetaddr[4] << 8 | enetaddr[5];
- writel(val, CXR25);
-
- return ret;
-#else
return 0;
-#endif
}
-int board_mmc_init(bd_t *bis)
+int dram_init_banksize(void)
{
- int ret = -ENODEV;
-
-#ifdef CONFIG_SH_SDHI
- gpio_request(GPIO_FN_SD0_DATA0, NULL);
- gpio_request(GPIO_FN_SD0_DATA1, NULL);
- gpio_request(GPIO_FN_SD0_DATA2, NULL);
- gpio_request(GPIO_FN_SD0_DATA3, NULL);
- gpio_request(GPIO_FN_SD0_CLK, NULL);
- gpio_request(GPIO_FN_SD0_CMD, NULL);
- gpio_request(GPIO_FN_SD0_CD, NULL);
- gpio_request(GPIO_FN_SD2_DATA0, NULL);
- gpio_request(GPIO_FN_SD2_DATA1, NULL);
- gpio_request(GPIO_FN_SD2_DATA2, NULL);
- gpio_request(GPIO_FN_SD2_DATA3, NULL);
- gpio_request(GPIO_FN_SD2_CLK, NULL);
- gpio_request(GPIO_FN_SD2_CMD, NULL);
- gpio_request(GPIO_FN_SD2_CD, NULL);
-
- /* SDHI 0 */
- gpio_request(GPIO_GP_7_17, NULL);
- gpio_request(GPIO_GP_2_12, NULL);
- gpio_direction_output(GPIO_GP_7_17, 1); /* power on */
- gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
- SH_SDHI_QUIRK_16BIT_BUF);
- if (ret)
- return ret;
-
- /* SDHI 1 */
- gpio_request(GPIO_GP_7_18, NULL);
- gpio_request(GPIO_GP_2_13, NULL);
- gpio_direction_output(GPIO_GP_7_18, 1); /* power on */
- gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
- if (ret)
- return ret;
-
- /* SDHI 2 */
- gpio_request(GPIO_GP_7_19, NULL);
- gpio_request(GPIO_GP_2_26, NULL);
- gpio_direction_output(GPIO_GP_7_19, 1); /* power on */
- gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
-#endif
- return ret;
-}
-
-int dram_init(void)
-{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ fdtdec_setup_memory_banksize();
return 0;
}
-/* koelsch has KSZ8041NL/RNL */
-#define PHY_CONTROL1 0x1E
-#define PHY_LED_MODE 0xC0000
+/* Koelsch has KSZ8041NL/RNL */
+#define PHY_CONTROL1 0x1E
+#define PHY_LED_MODE 0xC0000
#define PHY_LED_MODE_ACK 0x4000
int board_phy_config(struct phy_device *phydev)
{
void reset_cpu(ulong addr)
{
- u8 val;
+ struct udevice *dev;
+ const u8 pmic_bus = 6;
+ const u8 pmic_addr = 0x58;
+ u8 data;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+ if (ret)
+ hang();
+
+ ret = dm_i2c_read(dev, 0x13, &data, 1);
+ if (ret)
+ hang();
+
+ data |= BIT(1);
- i2c_set_bus_num(2); /* PowerIC connected to ch2 */
- i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
- val |= 0x02;
- i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+ ret = dm_i2c_write(dev, 0x13, &data, 1);
+ if (ret)
+ hang();
}
-static const struct sh_serial_platdata serial_platdata = {
- .base = SCIF0_BASE,
- .type = PORT_SCIF,
- .clk = 14745600,
- .clk_mode = EXT_CLK,
-};
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ const u32 load_magic = 0xb33fc0de;
-U_BOOT_DEVICE(koelsch_serials) = {
- .name = "serial_sh",
- .platdata = &serial_platdata,
-};
+ /* Block environment access if loaded using JTAG */
+ if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+ (op != ENVOP_INIT))
+ return ENVL_UNKNOWN;
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ return ENVL_SPI_FLASH;
+}
--- /dev/null
+/*
+ * board/renesas/koelsch/koelsch_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125 BIT(25)
+#define SCIF0_MSTP721 BIT(21)
+#define QSPI_MSTP917 BIT(17)
+
+#define SD2CKCR 0xE615026C
+#define SD_97500KHZ 0x7
+
+struct reg_config {
+ u16 off;
+ u32 val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+ static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
+
+ while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+ ;
+
+ while (!(readl(dbsc3_1_base + reg) & BIT(0)))
+ ;
+}
+
+static void spl_init_sys(void)
+{
+ u32 r0 = 0;
+
+ writel(0xa5a5a500, 0xe6020004);
+ writel(0xa5a5a500, 0xe6030004);
+
+ asm volatile(
+ /* ICIALLU - Invalidate I$ to PoU */
+ "mcr 15, 0, %0, cr7, cr5, 0 \n"
+ /* BPIALL - Invalidate branch predictors */
+ "mcr 15, 0, %0, cr7, cr5, 6 \n"
+ /* Set SCTLR[IZ] */
+ "mrc 15, 0, %0, cr1, cr0, 0 \n"
+ "orr %0, #0x1800 \n"
+ "mcr 15, 0, %0, cr1, cr0, 0 \n"
+ "isb sy \n"
+ :"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+ static const struct reg_config pfc_with_unlock[] = {
+ { 0x0090, 0x60000000 },
+ { 0x0094, 0x60000000 },
+ { 0x0098, 0x00800200 },
+ { 0x009c, 0x00000000 },
+ { 0x0020, 0x00000000 },
+ { 0x0024, 0x00000000 },
+ { 0x0028, 0x000244c8 },
+ { 0x002c, 0x00000000 },
+ { 0x0030, 0x00002400 },
+ { 0x0034, 0x01520000 },
+ { 0x0038, 0x00724003 },
+ { 0x003c, 0x00000000 },
+ { 0x0040, 0x00000000 },
+ { 0x0044, 0x00000000 },
+ { 0x0048, 0x00000000 },
+ { 0x004c, 0x00000000 },
+ { 0x0050, 0x00000000 },
+ { 0x0054, 0x00000000 },
+ { 0x0058, 0x00000000 },
+ { 0x005c, 0x00000000 },
+ { 0x0160, 0x00000000 },
+ { 0x0004, 0xffffffff },
+ { 0x0008, 0x00ec3fff },
+ { 0x000c, 0x3bc001e7 },
+ { 0x0010, 0x5bffffff },
+ { 0x0014, 0x1ffffffb },
+ { 0x0018, 0x01bffff0 },
+ { 0x001c, 0xcf7fffff },
+ { 0x0074, 0x0381fc00 },
+ };
+
+ static const struct reg_config pfc_without_unlock[] = {
+ { 0x0100, 0xffffffdf },
+ { 0x0104, 0xc883c3ff },
+ { 0x0108, 0x1201f3c9 },
+ { 0x010c, 0x00000000 },
+ { 0x0110, 0xffffeb04 },
+ { 0x0114, 0xc003ffff },
+ { 0x0118, 0x0800000f },
+ { 0x011c, 0x001800f0 },
+ };
+
+ static const u32 pfc_base = 0xe6060000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+ writel(~pfc_with_unlock[i].val, pfc_base);
+ writel(pfc_with_unlock[i].val,
+ pfc_base | pfc_with_unlock[i].off);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+ writel(pfc_without_unlock[i].val,
+ pfc_base | pfc_without_unlock[i].off);
+}
+
+static void spl_init_gpio(void)
+{
+ static const u16 gpio_offs[] = {
+ 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800
+ };
+
+ static const struct reg_config gpio_set[] = {
+ { 0x2000, 0x04381000 },
+ { 0x5000, 0x00000000 },
+ { 0x5800, 0x000e0000 },
+
+ };
+
+ static const struct reg_config gpio_clr[] = {
+ { 0x1000, 0x00000000 },
+ { 0x2000, 0x04381010 },
+ { 0x3000, 0x00000000 },
+ { 0x4000, 0x00000000 },
+ { 0x5000, 0x00400000 },
+ { 0x5400, 0x00000000 },
+ { 0x5800, 0x000e0380 },
+ };
+
+ static const u32 gpio_base = 0xe6050000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+ writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+ writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+ static const struct reg_config lbsc_config[] = {
+ { 0x00, 0x00000020 },
+ { 0x08, 0x00002020 },
+ { 0x30, 0x2a103320 },
+ { 0x38, 0xff70ff70 },
+ };
+
+ static const u16 lbsc_offs[] = {
+ 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
+ };
+
+ static const u32 lbsc_base = 0xfec00200;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+ writel(lbsc_config[i].val,
+ lbsc_base | lbsc_config[i].off);
+ writel(lbsc_config[i].val,
+ lbsc_base | (lbsc_config[i].off + 4));
+ }
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+ writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+ static const struct reg_config dbsc_config1[] = {
+ { 0x0018, 0x21000000 },
+ { 0x0018, 0x11000000 },
+ { 0x0018, 0x10000000 },
+ { 0x0280, 0x0000a55a },
+ { 0x0290, 0x00000010 },
+ { 0x02a0, 0xf004649b },
+ { 0x0020, 0x00000007 },
+ { 0x0024, 0x0f030a02 },
+ { 0x0030, 0x00000001 },
+ { 0x00b0, 0x00000000 },
+ { 0x0040, 0x0000000b },
+ { 0x0044, 0x00000008 },
+ { 0x0048, 0x00000000 },
+ { 0x0050, 0x0000000b },
+ { 0x0054, 0x000c000b },
+ { 0x0058, 0x00000027 },
+ { 0x005c, 0x0000001c },
+ { 0x0060, 0x00000006 },
+ { 0x0064, 0x00000020 },
+ { 0x0068, 0x00000008 },
+ { 0x006c, 0x0000000c },
+ { 0x0070, 0x00000009 },
+ { 0x0074, 0x00000012 },
+ { 0x0078, 0x000000d0 },
+ { 0x007c, 0x00140005 },
+ { 0x0080, 0x00050004 },
+ { 0x0084, 0x70233005 },
+ { 0x0088, 0x000c0000 },
+ { 0x008c, 0x00000300 },
+ { 0x0090, 0x00000040 },
+ { 0x0100, 0x00000001 },
+ { 0x00c0, 0x00020001 },
+ { 0x00c8, 0x20082008 },
+ { 0x0380, 0x00020002 },
+ { 0x0390, 0x0000001f },
+ };
+
+ static const struct reg_config dbsc_config5[] = {
+ { 0x0244, 0x00000011 },
+ { 0x0290, 0x00000006 },
+ { 0x02a0, 0x0005c000 },
+ { 0x0290, 0x00000003 },
+ { 0x02a0, 0x0300c481 },
+ { 0x0290, 0x00000023 },
+ { 0x02a0, 0x00fdb6c0 },
+ { 0x0290, 0x00000011 },
+ { 0x02a0, 0x1000040b },
+ { 0x0290, 0x00000012 },
+ { 0x02a0, 0x9d9cbb66 },
+ { 0x0290, 0x00000013 },
+ { 0x02a0, 0x1a868400 },
+ { 0x0290, 0x00000014 },
+ { 0x02a0, 0x300214d8 },
+ { 0x0290, 0x00000015 },
+ { 0x02a0, 0x00000d70 },
+ { 0x0290, 0x00000016 },
+ { 0x02a0, 0x00000006 },
+ { 0x0290, 0x00000017 },
+ { 0x02a0, 0x00000018 },
+ { 0x0290, 0x0000001a },
+ { 0x02a0, 0x910035c7 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config6[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000181 },
+ { 0x0018, 0x11000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config7[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x0000fe01 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config8[] = {
+ { 0x0304, 0x00000000 },
+ { 0x00f4, 0x01004c20 },
+ { 0x00f8, 0x014000aa },
+ { 0x00e0, 0x00000140 },
+ { 0x00e4, 0x00081860 },
+ { 0x00e8, 0x00010000 },
+ { 0x0014, 0x00000001 },
+ { 0x0010, 0x00000001 },
+ { 0x0280, 0x00000000 },
+ };
+
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+ static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
+ writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+ writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
+ }
+
+ dbsc_wait(0x240);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
+ writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+ writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
+ }
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
+ writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+ writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
+ }
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
+ writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+ writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
+ }
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
+ writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+ writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
+ }
+
+}
+
+static void spl_init_qspi(void)
+{
+ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+ static const u32 qspi_base = 0xe6b10000;
+
+ writeb(0x08, qspi_base + 0x00);
+ writeb(0x00, qspi_base + 0x01);
+ writeb(0x06, qspi_base + 0x02);
+ writeb(0x01, qspi_base + 0x0a);
+ writeb(0x00, qspi_base + 0x0b);
+ writeb(0x00, qspi_base + 0x0c);
+ writeb(0x00, qspi_base + 0x0d);
+ writeb(0x00, qspi_base + 0x0e);
+
+ writew(0xe080, qspi_base + 0x10);
+
+ writeb(0xc0, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x08);
+ writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+ int i;
+
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+ /*
+ * SD0 clock is set to 97.5MHz by default.
+ * Set SD2 to the 97.5MHz as well.
+ */
+ writel(SD_97500KHZ, SD2CKCR);
+
+ spl_init_sys();
+ spl_init_pfc();
+ spl_init_gpio();
+ spl_init_lbsc();
+
+ /* Unknown, likely ES1.0-specific delay */
+ for (i = 0; i < 100000; i++)
+ asm volatile("nop");
+
+ spl_init_dbsc();
+ spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ const u32 jtag_magic = 0x1337c0de;
+ const u32 load_magic = 0xb33fc0de;
+
+ /*
+ * If JTAG probe sets special word at 0xe6300020, then it must
+ * put U-Boot into RAM and SPL will start it from RAM.
+ */
+ if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+ printf("JTAG boot detected!\n");
+
+ while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+ ;
+
+ spl_boot_list[0] = BOOT_DEVICE_RAM;
+ spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+ return;
+ }
+
+ /* Boot from SPI NOR with YMODEM UART fallback. */
+ spl_boot_list[0] = BOOT_DEVICE_SPI;
+ spl_boot_list[1] = BOOT_DEVICE_UART;
+ spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(ulong addr)
+{
+}
#include <malloc.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
+#include <environment.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
if (ret)
hang();
}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ const u32 load_magic = 0xb33fc0de;
+
+ /* Block environment access if loaded using JTAG */
+ if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+ (op != ENVOP_INIT))
+ return ENVL_UNKNOWN;
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ return ENVL_SPI_FLASH;
+}
# SPDX-License-Identifier: GPL-2.0
#
-obj-y := silk.o qos.o ../rcar-common/common.o
+ifdef CONFIG_SPL_BUILD
+obj-y := silk_spl.o
+else
+obj-y := silk.o qos.o
+endif
DECLARE_GLOBAL_DATA_PTR;
-#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
qos_init();
}
-#define TMU0_MSTP125 (1 << 25)
-#define SCIF2_MSTP719 (1 << 19)
-#define ETHER_MSTP813 (1 << 13)
-#define IIC1_MSTP323 (1 << 23)
-#define MMC0_MSTP315 (1 << 15)
-#define SDHI1_MSTP312 (1 << 12)
+#define TMU0_MSTP125 BIT(25)
+#define MMC0_MSTP315 BIT(15)
#define SD1CKCR 0xE6150078
-#define SD1_97500KHZ 0x7
+#define SD_97500KHZ 0x7
int board_early_init_f(void)
{
/* TMU */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
- /* SCIF2 */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
+ /* Set SD1 to the 97.5MHz */
+ writel(SD_97500KHZ, SD1CKCR);
- /* ETHER */
- mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
-
- /* IIC1 / sh-i2c ch1 */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
-
-#ifdef CONFIG_SH_MMCIF
- /* MMC */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
-#endif
-
-#ifdef CONFIG_SH_SDHI
- /* SDHI1 */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI1_MSTP312);
-
- /*
- * Set SD1 to the 97.5MHz
- */
- writel(SD1_97500KHZ, SD1CKCR);
-#endif
return 0;
}
-/* LSI pin pull-up control */
-#define PUPR3 0xe606010C
-#define PUPR3_ETH 0x006FF800
-#define PUPR1 0xe6060104
-#define PUPR1_DREQ0_N (1 << 20)
+#define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */
+
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- /* Init PFC controller */
- r8a7794_pinmux_init();
-
- /* Ether Enable */
- gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
- gpio_request(GPIO_FN_ETH_RX_ER, NULL);
- gpio_request(GPIO_FN_ETH_RXD0, NULL);
- gpio_request(GPIO_FN_ETH_RXD1, NULL);
- gpio_request(GPIO_FN_ETH_LINK, NULL);
- gpio_request(GPIO_FN_ETH_REFCLK, NULL);
- gpio_request(GPIO_FN_ETH_MDIO, NULL);
- gpio_request(GPIO_FN_ETH_TXD1, NULL);
- gpio_request(GPIO_FN_ETH_TX_EN, NULL);
- gpio_request(GPIO_FN_ETH_MAGIC, NULL);
- gpio_request(GPIO_FN_ETH_TXD0, NULL);
- gpio_request(GPIO_FN_ETH_MDC, NULL);
- gpio_request(GPIO_FN_IRQ8, NULL);
-
- /* PHY reset */
- mstp_clrbits_le32(PUPR3, PUPR3, PUPR3_ETH);
- gpio_request(GPIO_GP_1_24, NULL);
- mstp_clrbits_le32(PUPR1, PUPR1, PUPR1_DREQ0_N);
-
- gpio_direction_output(GPIO_GP_1_24, 0);
+ /* Force ethernet PHY out of reset */
+ gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+ gpio_direction_output(ETHERNET_PHY_RESET, 0);
mdelay(20);
- gpio_set_value(GPIO_GP_1_24, 1);
+ gpio_direction_output(ETHERNET_PHY_RESET, 1);
udelay(1);
return 0;
}
-#define CXR24 0xEE7003C0 /* MAC address high register */
-#define CXR25 0xEE7003C8 /* MAC address low register */
-int board_eth_init(bd_t *bis)
+int dram_init(void)
{
-#ifdef CONFIG_SH_ETHER
- int ret = -ENODEV;
- u32 val;
- unsigned char enetaddr[6];
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
- ret = sh_eth_initialize(bis);
- if (!eth_env_get_enetaddr("ethaddr", enetaddr))
- return ret;
-
- /* Set Mac address */
- val = enetaddr[0] << 24 | enetaddr[1] << 16 |
- enetaddr[2] << 8 | enetaddr[3];
- writel(val, CXR24);
-
- val = enetaddr[4] << 8 | enetaddr[5];
- writel(val, CXR25);
-
- return ret;
-#else
return 0;
-#endif
}
-int board_mmc_init(bd_t *bis)
+int dram_init_banksize(void)
{
- int ret = -ENODEV;
-
-#ifdef CONFIG_SH_MMCIF
- /* MMC0 */
- gpio_request(GPIO_GP_4_31, NULL);
- gpio_direction_output(GPIO_GP_4_31, 1);
-
- ret = mmcif_mmc_init();
-#endif
-
-#ifdef CONFIG_SH_SDHI
- gpio_request(GPIO_FN_SD1_DATA0, NULL);
- gpio_request(GPIO_FN_SD1_DATA1, NULL);
- gpio_request(GPIO_FN_SD1_DATA2, NULL);
- gpio_request(GPIO_FN_SD1_DATA3, NULL);
- gpio_request(GPIO_FN_SD1_CLK, NULL);
- gpio_request(GPIO_FN_SD1_CMD, NULL);
- gpio_request(GPIO_FN_SD1_CD, NULL);
-
- /* SDHI 1 */
- gpio_request(GPIO_GP_4_26, NULL);
- gpio_request(GPIO_GP_4_29, NULL);
- gpio_direction_output(GPIO_GP_4_26, 1);
- gpio_direction_output(GPIO_GP_4_29, 1);
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
-#endif
- return ret;
+ fdtdec_setup_memory_banksize();
+
+ return 0;
}
-int dram_init(void)
+/* porter has KSZ8041RNLI */
+#define PHY_CONTROL1 0x1E
+#define PHY_LED_MODE 0xC0000
+#define PHY_LED_MODE_ACK 0x4000
+int board_phy_config(struct phy_device *phydev)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+ ret &= ~PHY_LED_MODE;
+ ret |= PHY_LED_MODE_ACK;
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
return 0;
}
void reset_cpu(ulong addr)
{
- u8 val;
+ struct udevice *dev;
+ const u8 pmic_bus = 1;
+ const u8 pmic_addr = 0x58;
+ u8 data;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+ if (ret)
+ hang();
+
+ ret = dm_i2c_read(dev, 0x13, &data, 1);
+ if (ret)
+ hang();
- i2c_set_bus_num(1); /* PowerIC connected to ch1 */
- i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
- val |= 0x02;
- i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+ data |= BIT(1);
+
+ ret = dm_i2c_write(dev, 0x13, &data, 1);
+ if (ret)
+ hang();
}
-static const struct sh_serial_platdata serial_platdata = {
- .base = SCIF2_BASE,
- .type = PORT_SCIF,
- .clk = 14745600,
- .clk_mode = EXT_CLK,
-};
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ const u32 load_magic = 0xb33fc0de;
-U_BOOT_DEVICE(silk_serials) = {
- .name = "serial_sh",
- .platdata = &serial_platdata,
-};
+ /* Block environment access if loaded using JTAG */
+ if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+ (op != ENVOP_INIT))
+ return ENVL_UNKNOWN;
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ return ENVL_SPI_FLASH;
+}
--- /dev/null
+/*
+ * board/renesas/silk/silk_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125 BIT(25)
+#define SCIF2_MSTP719 BIT(19)
+#define QSPI_MSTP917 BIT(17)
+
+#define SD1CKCR 0xE6150078
+#define SD_97500KHZ 0x7
+
+struct reg_config {
+ u16 off;
+ u32 val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+
+ while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+ ;
+}
+
+static void spl_init_sys(void)
+{
+ u32 r0 = 0;
+
+ writel(0xa5a5a500, 0xe6020004);
+ writel(0xa5a5a500, 0xe6030004);
+
+ asm volatile(
+ /* ICIALLU - Invalidate I$ to PoU */
+ "mcr 15, 0, %0, cr7, cr5, 0 \n"
+ /* BPIALL - Invalidate branch predictors */
+ "mcr 15, 0, %0, cr7, cr5, 6 \n"
+ /* Set SCTLR[IZ] */
+ "mrc 15, 0, %0, cr1, cr0, 0 \n"
+ "orr %0, #0x1800 \n"
+ "mcr 15, 0, %0, cr1, cr0, 0 \n"
+ "isb sy \n"
+ :"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+ static const struct reg_config pfc_with_unlock[] = {
+ { 0x0090, 0x00018040 },
+ { 0x0094, 0x00000000 },
+ { 0x0098, 0x00000000 },
+ { 0x0020, 0x94000000 },
+ { 0x0024, 0x00000006 },
+ { 0x0028, 0x40000000 },
+ { 0x002c, 0x00000155 },
+ { 0x0030, 0x00000002 },
+ { 0x0034, 0x00000000 },
+ { 0x0038, 0x00000000 },
+ { 0x003c, 0x00000000 },
+ { 0x0040, 0x60000000 },
+ { 0x0044, 0x36dab6db },
+ { 0x0048, 0x926da012 },
+ { 0x004c, 0x0008c383 },
+ { 0x0050, 0x00000000 },
+ { 0x0054, 0x00000140 },
+ { 0x0004, 0xffffffff },
+ { 0x0008, 0x00ec3fff },
+ { 0x000c, 0x5bffffff },
+ { 0x0010, 0x01bfe1ff },
+ { 0x0014, 0x5bffffff },
+ { 0x0018, 0x0f4b200f },
+ { 0x001c, 0x03ffffff },
+ };
+
+ static const struct reg_config pfc_without_unlock[] = {
+ { 0x0100, 0x00000000 },
+ { 0x0104, 0x4203fdf0 },
+ { 0x0108, 0x00000000 },
+ { 0x010c, 0x159007ff },
+ { 0x0110, 0x80000000 },
+ { 0x0114, 0x00de481f },
+ { 0x0118, 0x00000000 },
+ };
+
+ static const struct reg_config pfc_with_unlock2[] = {
+ { 0x0060, 0xffffffff },
+ { 0x0064, 0xfffff000 },
+ { 0x0068, 0x55555500 },
+ { 0x006c, 0xffffff00 },
+ { 0x0070, 0x00000000 },
+ };
+
+ static const u32 pfc_base = 0xe6060000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+ writel(~pfc_with_unlock[i].val, pfc_base);
+ writel(pfc_with_unlock[i].val,
+ pfc_base | pfc_with_unlock[i].off);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+ writel(pfc_without_unlock[i].val,
+ pfc_base | pfc_without_unlock[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(pfc_with_unlock2); i++) {
+ writel(~pfc_with_unlock2[i].val, pfc_base);
+ writel(pfc_with_unlock2[i].val,
+ pfc_base | pfc_with_unlock2[i].off);
+ }
+}
+
+static void spl_init_gpio(void)
+{
+ static const u16 gpio_offs[] = {
+ 0x1000, 0x2000, 0x3000, 0x4000
+ };
+
+ static const struct reg_config gpio_set[] = {
+ { 0x2000, 0x24000000 },
+ { 0x4000, 0xa4000000 },
+ { 0x5000, 0x0084c000 },
+ };
+
+ static const struct reg_config gpio_clr[] = {
+ { 0x1000, 0x01000000 },
+ { 0x2000, 0x24000000 },
+ { 0x3000, 0x00000000 },
+ { 0x4000, 0xa4000000 },
+ { 0x5000, 0x00044380 },
+ };
+
+ static const u32 gpio_base = 0xe6050000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x20 | gpio_offs[i]);
+ writel(BIT(23), gpio_base | 0x5020);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x00 | gpio_offs[i]);
+ writel(BIT(23), gpio_base | 0x5000);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+ writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+ writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+ static const struct reg_config lbsc_config[] = {
+ { 0x00, 0x00000020 },
+ { 0x08, 0x00002020 },
+ { 0x30, 0x2a103320 },
+ { 0x38, 0xff70ff70 },
+ };
+
+ static const u16 lbsc_offs[] = {
+ 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8
+ };
+
+ static const u32 lbsc_base = 0xfec00200;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+ writel(lbsc_config[i].val,
+ lbsc_base | lbsc_config[i].off);
+ writel(lbsc_config[i].val,
+ lbsc_base | (lbsc_config[i].off + 4));
+ }
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+ writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+ static const struct reg_config dbsc_config1[] = {
+ { 0x0018, 0x21000000 },
+ { 0x0018, 0x11000000 },
+ { 0x0018, 0x10000000 },
+ { 0x0280, 0x0000a55a },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x80000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config2[] = {
+ { 0x0290, 0x00000006 },
+ { 0x02a0, 0x0005c000 },
+ };
+
+ static const struct reg_config dbsc_config3r2[] = {
+ { 0x0290, 0x0000000f },
+ { 0x02a0, 0x00181224 },
+ };
+
+ static const struct reg_config dbsc_config4[] = {
+ { 0x0290, 0x00000010 },
+ { 0x02a0, 0xf004649b },
+ { 0x0290, 0x00000061 },
+ { 0x02a0, 0x0000006d },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000073 },
+ { 0x0020, 0x00000007 },
+ { 0x0024, 0x0f030a02 },
+ { 0x0030, 0x00000001 },
+ { 0x00b0, 0x00000000 },
+ { 0x0040, 0x00000009 },
+ { 0x0044, 0x00000007 },
+ { 0x0048, 0x00000000 },
+ { 0x0050, 0x00000009 },
+ { 0x0054, 0x000a0009 },
+ { 0x0058, 0x00000021 },
+ { 0x005c, 0x00000018 },
+ { 0x0060, 0x00000005 },
+ { 0x0064, 0x00000020 },
+ { 0x0068, 0x00000007 },
+ { 0x006c, 0x0000000a },
+ { 0x0070, 0x00000009 },
+ { 0x0074, 0x00000010 },
+ { 0x0078, 0x000000ae },
+ { 0x007c, 0x00140005 },
+ { 0x0080, 0x00050004 },
+ { 0x0084, 0x50213005 },
+ { 0x0088, 0x000c0000 },
+ { 0x008c, 0x00000200 },
+ { 0x0090, 0x00000040 },
+ { 0x0100, 0x00000001 },
+ { 0x00c0, 0x00020001 },
+ { 0x00c8, 0x20042004 },
+ { 0x0380, 0x00020003 },
+ { 0x0390, 0x0000001f },
+ };
+
+ static const struct reg_config dbsc_config5[] = {
+ { 0x0244, 0x00000011 },
+ { 0x0290, 0x00000003 },
+ { 0x02a0, 0x0300c4e1 },
+ { 0x0290, 0x00000023 },
+ { 0x02a0, 0x00fcb6d0 },
+ { 0x0290, 0x00000011 },
+ { 0x02a0, 0x1000040b },
+ { 0x0290, 0x00000012 },
+ { 0x02a0, 0x85589955 },
+ { 0x0290, 0x00000013 },
+ { 0x02a0, 0x1a852400 },
+ { 0x0290, 0x00000014 },
+ { 0x02a0, 0x300210b4 },
+ { 0x0290, 0x00000015 },
+ { 0x02a0, 0x00000b50 },
+ { 0x0290, 0x00000016 },
+ { 0x02a0, 0x00000006 },
+ { 0x0290, 0x00000017 },
+ { 0x02a0, 0x00000010 },
+ { 0x0290, 0x0000001a },
+ { 0x02a0, 0x910035c7 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config6[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000181 },
+ { 0x0018, 0x11000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config7[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x0000fe01 },
+ { 0x0304, 0x00000000 },
+ { 0x00f4, 0x01004c20 },
+ { 0x00f8, 0x012c00be },
+ { 0x00e0, 0x00000140 },
+ { 0x00e4, 0x00081450 },
+ { 0x00e8, 0x00010000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config8[] = {
+ { 0x0014, 0x00000001 },
+ { 0x0290, 0x00000010 },
+ { 0x02a0, 0xf00464db },
+ { 0x0010, 0x00000001 },
+ { 0x0280, 0x00000000 },
+ };
+
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
+ writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
+ writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
+ writel(dbsc_config3r2[i].val,
+ dbsc3_0_base | dbsc_config3r2[i].off);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
+ writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+
+ dbsc_wait(0x240);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
+ writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
+ writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
+ writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
+ writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+
+}
+
+static void spl_init_qspi(void)
+{
+ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+ static const u32 qspi_base = 0xe6b10000;
+
+ writeb(0x08, qspi_base + 0x00);
+ writeb(0x00, qspi_base + 0x01);
+ writeb(0x06, qspi_base + 0x02);
+ writeb(0x01, qspi_base + 0x0a);
+ writeb(0x00, qspi_base + 0x0b);
+ writeb(0x00, qspi_base + 0x0c);
+ writeb(0x00, qspi_base + 0x0d);
+ writeb(0x00, qspi_base + 0x0e);
+
+ writew(0xe080, qspi_base + 0x10);
+
+ writeb(0xc0, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x08);
+ writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
+
+ /* Set SD1 to the 97.5MHz */
+ writel(SD_97500KHZ, SD1CKCR);
+
+ spl_init_sys();
+ spl_init_pfc();
+ spl_init_gpio();
+ spl_init_lbsc();
+ spl_init_dbsc();
+ spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ const u32 jtag_magic = 0x1337c0de;
+ const u32 load_magic = 0xb33fc0de;
+
+ /*
+ * If JTAG probe sets special word at 0xe6300020, then it must
+ * put U-Boot into RAM and SPL will start it from RAM.
+ */
+ if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+ printf("JTAG boot detected!\n");
+
+ while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+ ;
+
+ spl_boot_list[0] = BOOT_DEVICE_RAM;
+ spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+ return;
+ }
+
+ /* Boot from SPI NOR with YMODEM UART fallback. */
+ spl_boot_list[0] = BOOT_DEVICE_SPI;
+ spl_boot_list[1] = BOOT_DEVICE_UART;
+ spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(ulong addr)
+{
+}
const struct rmobile_sysinfo sysinfo = {
CONFIG_ARCH_RMOBILE_BOARD_STRING
};
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ const u32 load_magic = 0xb33fc0de;
+
+ /* Block environment access if loaded using JTAG */
+ if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+ (op != ENVOP_INIT))
+ return ENVL_UNKNOWN;
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ return ENVL_SPI_FLASH;
+}
#else
int dram_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
zynq_ddrc_init();
#else
int dram_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
return 0;
}
static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
- return soc_clk_dump();
+ int ret;
+
+ ret = soc_clk_dump();
+ if (ret < 0) {
+ printf("Clock dump error %d\n", ret);
+ ret = CMD_RET_FAILURE;
+ }
+
+ return ret;
}
static cmd_tbl_t cmd_clk_sub[] = {
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SH_MMCIF=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0xE6304000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_R8A7791=y
CONFIG_TARGET_KOELSCH=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7791-koelsch-u-boot"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
+CONFIG_RENESAS_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MICREL=y
-CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
-CONFIG_BAUDRATE=38400
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SH_QSPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SH_MMCIF=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_TARGET_SALVATOR_X=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7795-salvator-x-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_TARGET_ULCB=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7795-h3ulcb-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_TARGET_SALVATOR_X=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77965-salvator-x-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_TARGET_SALVATOR_X=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7796-salvator-x-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_TARGET_ULCB=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7796-m3ulcb-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_TARGET_EAGLE=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_BLK=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_RENESAS_SDHI=y
+# CONFIG_MMC is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_TARGET_DRAAK=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak-u-boot"
CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_DOS_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MMC=y
+CONFIG_SH_MMCIF=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MMC=y
+CONFIG_SH_MMCIF=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_MMC=y
+CONFIG_SH_MMCIF=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0xE6304000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_R8A7794=y
CONFIG_TARGET_SILK=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7794-silk-u-boot"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
+CONFIG_SH_MMCIF=y
+CONFIG_RENESAS_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MICREL=y
-CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
-CONFIG_BAUDRATE=38400
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SH_QSPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_BLK=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
-CONFIG_DM_MMC=y
CONFIG_NAND=y
CONFIG_NAND_ZYNQ=y
CONFIG_DEBUG_UART_ZYNQ=y
* persistence
* runtime support
+* support bootefi booting ARMv7 in non-secure mode (CONFIG_ARMV7_NONSEC=y)
+
## Links
* [1](http://uefi.org/specifications)
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
+static const struct cpg_core_clk r8a7792_core_clks[] = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_FIXED("osc", R8A7792_CLK_OSC, CLK_PLL1, 12288, 1),
};
-static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
+static const struct mssr_mod_clk r8a7792_mod_clks[] = {
DEF_MOD("msiof0", 0, R8A7792_CLK_MP),
DEF_MOD("jpu", 106, R8A7792_CLK_M2),
DEF_MOD("tmu1", 111, R8A7792_CLK_P),
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
};
-static const unsigned int r8a7792_crit_mod_clks[] __initconst = {
- MOD_CLK_ID(408), /* INTC-SYS (GIC) */
-};
-
/*
* CPG Clock Data
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
{ 1, 208, 106, 200 },
{ 1, 208, 88, 200 },
{ 1, 156, 80, 150 },
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
+static const struct cpg_core_clk r8a7794_core_clks[] = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
};
-static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
+static const struct mssr_mod_clk r8a7794_mod_clks[] = {
DEF_MOD("msiof0", 0, R8A7794_CLK_MP),
DEF_MOD("vcp0", 101, R8A7794_CLK_ZS),
DEF_MOD("vpc0", 103, R8A7794_CLK_ZS),
DEF_MOD("scifa5", 1108, R8A7794_CLK_MP),
};
-static const unsigned int r8a7794_crit_mod_clks[] __initconst = {
- MOD_CLK_ID(408), /* INTC-SYS (GIC) */
-};
-
/*
* CPG Clock Data
*/
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] = {
{ 1, 208, 88, 200 },
{ 1, 156, 66, 150 },
{ 2, 240, 102, 230 },
def_bool y
depends on ARCH_UNIPHIER
select CLK
- select SPL_CLK if SPL
help
Support for clock controllers on UniPhier SoCs.
Say Y if you want to control clocks provided by System Control
defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\
defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
UNIPHIER_LD4_SYS_CLK_NAND(2),
+ UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */
+ UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */
UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */
+ UNIPHIER_CLK_GATE_SIMPLE(10, 0x2260, 0), /* ether-phy (Pro4) */
UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6), /* gio (Pro4, Pro5) */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */
UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */
const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
UNIPHIER_LD11_SYS_CLK_NAND(2),
+ UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */
UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */
UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */
const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
UNIPHIER_LD11_SYS_CLK_NAND(2),
+ UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */
+ UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */
UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */
UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5), /* usb31-0 (gio1) */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6), /* usb31-1 (gio1-1) */
help
Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform
+config SH_MMCIF
+ bool "SuperH/Renesas ARM SoCs on-chip MMCIF host controller support"
+ depends on ARCH_RMOBILE || SH
+ help
+ Support for the on-chip MMCIF host controller on SuperH/Renesas ARM SoCs platform
+
config MMC_UNIPHIER
bool "UniPhier SD/MMC Host Controller support"
depends on ARCH_UNIPHIER
uint32_t meson_mmc_clk = 0;
unsigned int clk, clk_src, clk_div;
+ if (!mmc->clock)
+ return;
+
/* 1GHz / CLK_MAX_DIV = 15,9 MHz */
if (mmc->clock > 16000000) {
clk = SD_EMMC_CLKSRC_DIV2;
return 0;
}
-int sd_select_bus_width(struct mmc *mmc, int w)
+static int sd_select_bus_width(struct mmc *mmc, int w)
{
int err;
struct mmc_cmd cmd;
static int renesas_sdhi_probe(struct udevice *dev)
{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
u32 quirks = dev_get_driver_data(dev);
struct fdt_resource reg_res;
+ struct clk clk;
DECLARE_GLOBAL_DATA_PTR;
int ret;
quirks |= TMIO_SD_CAP_16BIT;
}
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get host clock\n");
+ return ret;
+ }
+
+ /* set to max rate */
+ priv->mclk = clk_set_rate(&clk, ULONG_MAX);
+ if (IS_ERR_VALUE(priv->mclk)) {
+ dev_err(dev, "failed to set rate for host clock\n");
+ clk_free(&clk);
+ return priv->mclk;
+ }
+
+ ret = clk_enable(&clk);
+ clk_free(&clk);
+ if (ret) {
+ dev_err(dev, "failed to enable host clock\n");
+ return ret;
+ }
+
ret = tmio_sd_probe(dev, quirks);
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
if (!ret)
#include <watchdog.h>
#include <command.h>
#include <mmc.h>
+#include <clk.h>
+#include <dm.h>
#include <malloc.h>
#include <linux/errno.h>
-#include <asm/io.h>
+#include <linux/compat.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
#include "sh_mmcif.h"
#define DRIVER_NAME "sh_mmcif"
return ret;
}
-static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data)
+static int sh_mmcif_send_cmd_common(struct sh_mmcif_host *host,
+ struct mmc_cmd *cmd, struct mmc_data *data)
{
- struct sh_mmcif_host *host = mmc->priv;
int ret;
WATCHDOG_RESET();
return ret;
}
-static int sh_mmcif_set_ios(struct mmc *mmc)
+static int sh_mmcif_set_ios_common(struct sh_mmcif_host *host, struct mmc *mmc)
{
- struct sh_mmcif_host *host = mmc->priv;
-
if (mmc->clock)
sh_mmcif_clock_control(host, mmc->clock);
return 0;
}
-static int sh_mmcif_init(struct mmc *mmc)
+static int sh_mmcif_initialize_common(struct sh_mmcif_host *host)
{
- struct sh_mmcif_host *host = mmc->priv;
-
sh_mmcif_sync_reset(host);
sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
return 0;
}
+#ifndef CONFIG_DM_MMC
+static void *mmc_priv(struct mmc *mmc)
+{
+ return (void *)mmc->priv;
+}
+
+static int sh_mmcif_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct sh_mmcif_host *host = mmc_priv(mmc);
+
+ return sh_mmcif_send_cmd_common(host, cmd, data);
+}
+
+static int sh_mmcif_set_ios(struct mmc *mmc)
+{
+ struct sh_mmcif_host *host = mmc_priv(mmc);
+
+ return sh_mmcif_set_ios_common(host, mmc);
+}
+
+static int sh_mmcif_initialize(struct mmc *mmc)
+{
+ struct sh_mmcif_host *host = mmc_priv(mmc);
+
+ return sh_mmcif_initialize_common(host);
+}
+
static const struct mmc_ops sh_mmcif_ops = {
- .send_cmd = sh_mmcif_request,
- .set_ios = sh_mmcif_set_ios,
- .init = sh_mmcif_init,
+ .send_cmd = sh_mmcif_send_cmd,
+ .set_ios = sh_mmcif_set_ios,
+ .init = sh_mmcif_initialize,
};
static struct mmc_config sh_mmcif_cfg = {
return 0;
}
+
+#else
+struct sh_mmcif_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+int sh_mmcif_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct sh_mmcif_host *host = dev_get_priv(dev);
+
+ return sh_mmcif_send_cmd_common(host, cmd, data);
+}
+
+int sh_mmcif_dm_set_ios(struct udevice *dev)
+{
+ struct sh_mmcif_host *host = dev_get_priv(dev);
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+
+ return sh_mmcif_set_ios_common(host, mmc);
+}
+
+static const struct dm_mmc_ops sh_mmcif_dm_ops = {
+ .send_cmd = sh_mmcif_dm_send_cmd,
+ .set_ios = sh_mmcif_dm_set_ios,
+};
+
+static int sh_mmcif_dm_bind(struct udevice *dev)
+{
+ struct sh_mmcif_plat *plat = dev_get_platdata(dev);
+
+ return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static int sh_mmcif_dm_probe(struct udevice *dev)
+{
+ struct sh_mmcif_plat *plat = dev_get_platdata(dev);
+ struct sh_mmcif_host *host = dev_get_priv(dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct clk sh_mmcif_clk;
+ fdt_addr_t base;
+ int ret;
+
+ base = devfdt_get_addr(dev);
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ host->regs = (struct sh_mmcif_regs *)devm_ioremap(dev, base, SZ_2K);
+ if (!host->regs)
+ return -ENOMEM;
+
+ ret = clk_get_by_index(dev, 0, &sh_mmcif_clk);
+ if (ret) {
+ debug("failed to get clock, ret=%d\n", ret);
+ return ret;
+ }
+
+ ret = clk_enable(&sh_mmcif_clk);
+ if (ret) {
+ debug("failed to enable clock, ret=%d\n", ret);
+ return ret;
+ }
+
+ host->clk = clk_get_rate(&sh_mmcif_clk);
+
+ plat->cfg.name = dev->name;
+ plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
+
+ switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
+ 1)) {
+ case 8:
+ plat->cfg.host_caps |= MMC_MODE_8BIT;
+ break;
+ case 4:
+ plat->cfg.host_caps |= MMC_MODE_4BIT;
+ break;
+ case 1:
+ break;
+ default:
+ dev_err(dev, "Invalid \"bus-width\" value\n");
+ return -EINVAL;
+ }
+
+ sh_mmcif_initialize_common(host);
+
+ plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
+ plat->cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
+ plat->cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
+ plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+
+ upriv->mmc = &plat->mmc;
+
+ return 0;
+}
+
+static const struct udevice_id sh_mmcif_sd_match[] = {
+ { .compatible = "renesas,sh-mmcif" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sh_mmcif_mmc) = {
+ .name = "sh-mmcif",
+ .id = UCLASS_MMC,
+ .of_match = sh_mmcif_sd_match,
+ .bind = sh_mmcif_dm_bind,
+ .probe = sh_mmcif_dm_probe,
+ .priv_auto_alloc_size = sizeof(struct sh_mmcif_host),
+ .platdata_auto_alloc_size = sizeof(struct sh_mmcif_plat),
+ .ops = &sh_mmcif_dm_ops,
+};
+#endif
struct tmio_sd_priv *priv = dev_get_priv(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
fdt_addr_t base;
- struct clk clk;
int ret;
base = devfdt_get_addr(dev);
device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
#endif
- ret = clk_get_by_index(dev, 0, &clk);
- if (ret < 0) {
- dev_err(dev, "failed to get host clock\n");
- return ret;
- }
-
- /* set to max rate */
- priv->mclk = clk_set_rate(&clk, ULONG_MAX);
- if (IS_ERR_VALUE(priv->mclk)) {
- dev_err(dev, "failed to set rate for host clock\n");
- clk_free(&clk);
- return priv->mclk;
- }
-
- ret = clk_enable(&clk);
- clk_free(&clk);
- if (ret) {
- dev_err(dev, "failed to enable host clock\n");
- return ret;
- }
-
ret = mmc_of_parse(dev, &plat->cfg);
if (ret < 0) {
dev_err(dev, "failed to parse host caps\n");
static int uniphier_sd_probe(struct udevice *dev)
{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+#ifndef CONFIG_SPL_BUILD
+ struct clk clk;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get host clock\n");
+ return ret;
+ }
+
+ /* set to max rate */
+ priv->mclk = clk_set_rate(&clk, ULONG_MAX);
+ if (IS_ERR_VALUE(priv->mclk)) {
+ dev_err(dev, "failed to set rate for host clock\n");
+ clk_free(&clk);
+ return priv->mclk;
+ }
+
+ ret = clk_enable(&clk);
+ clk_free(&clk);
+ if (ret) {
+ dev_err(dev, "failed to enable host clock\n");
+ return ret;
+ }
+#else
+ priv->mclk = 100000000;
+#endif
+
return tmio_sd_probe(dev, 0);
}
return 0;
}
-int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
+static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
{
struct zynq_nand_info *xnand;
struct mtd_info *mtd;
}
xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
- mtd = get_nand_dev_by_index(0);
+ mtd = nand_to_mtd(nand_chip);
nand_chip->priv = xnand;
mtd->priv = nand_chip;
return err;
}
-#ifdef CONFIG_SYS_NAND_SELF_INIT
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-void __weak board_nand_init(void)
+void board_nand_init(void)
{
struct nand_chip *nand = &nand_chip[0];
if (zynq_nand_init(nand, 0))
puts("ZYNQ NAND init failed\n");
}
-#endif
/* System reset data */
static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
+ UNIPHIER_RESETX(6, 0x2000, 12), /* ETHER */
UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */
UNIPHIER_RESETX(12, 0x2000, 6), /* GIO */
UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
+ UNIPHIER_RESETX(6, 0x2000, 12), /* ETHER */
UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */
UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
+ UNIPHIER_RESETX(6, 0x200c, 6), /* ETHER */
UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC */
UNIPHIER_RESETX(12, 0x200c, 5), /* GIO */
UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
+ UNIPHIER_RESETX(6, 0x200c, 9), /* ETHER0 */
+ UNIPHIER_RESETX(7, 0x200c, 10), /* ETHER1 */
UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */
UNIPHIER_RESETX(12, 0x200c, 5), /* USB30 (GIO0) */
UNIPHIER_RESETX(13, 0x200c, 6), /* USB31 (GIO1) */
config USB_XHCI_DWC3_OF_SIMPLE
bool "DesignWare USB3 DRD Generic OF Simple Glue Layer"
- select MISC
+ depends on DM_USB
+ default y if DRA7XX
help
Support USB2/3 functionality in simple SoC integrations with
USB controller based on the DesignWare USB3 IP Core.
int ret;
ret = clk_get_bulk(dev, &simple->clks);
- if (ret == -ENOTSUPP)
+ if (ret == -ENOSYS)
return 0;
if (ret)
return ret;
static const struct udevice_id dwc3_of_simple_ids[] = {
{ .compatible = "amlogic,meson-gxl-dwc3" },
+ { .compatible = "ti,dwc3" },
{ }
};
ulong size;
/* Before relocation there is nothing to do here */
- if ((!gd->flags & GD_FLG_RELOC))
+ if (!(gd->flags & GD_FLG_RELOC))
return 0;
size = alloc_fb(dev, &addr);
if (addr < gd->video_bottom) {
struct cdns_wdt_priv {
bool rst;
u32 timeout;
- void __iomem *reg;
struct cdns_regs *regs;
};
*/
static int cdns_wdt_probe(struct udevice *dev)
{
- struct cdns_wdt_priv *priv = dev_get_priv(dev);
-
debug("%s: Probing wdt%u\n", __func__, dev->seq);
- priv->reg = ioremap((u32)priv->regs, sizeof(struct cdns_regs));
-
cdns_wdt_stop(dev);
return 0;
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* MMCIF */
-#define CONFIG_SH_MMCIF
#define CONFIG_SH_MMCIF_ADDR 0xee200000
#define CONFIG_SH_MMCIF_CLK 48000000
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
+/* Environment compatibility */
+#undef CONFIG_ENV_SIZE_REDUND
+#undef CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE (256 * 1024)
+#define CONFIG_ENV_OFFSET 0x700000
+
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#define CONFIG_SYS_CLK_FREQ 33333333u
#include "rcar-gen2-common.h"
-/* STACK */
-#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
-#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
-#else
-#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC
-#endif
-
-#define STACK_AREA_SIZE 0xC000
-#define LOW_LEVEL_MERAM_STACK \
+#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
+#define STACK_AREA_SIZE 0x00100000
+#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
/* MEMORY */
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-#define CONFIG_SYS_TMU_CLK_DIV 4
-
-/* i2c */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SH
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
-#define CONFIG_SYS_I2C_SH_SPEED0 400000
-#define CONFIG_SYS_I2C_SH_SPEED1 400000
-#define CONFIG_SYS_I2C_SH_SPEED2 400000
-#define CONFIG_SH_I2C_DATA_HIGH 4
-#define CONFIG_SH_I2C_DATA_LOW 5
-#define CONFIG_SH_I2C_CLOCK 10000000
-#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
-
-/* USB */
-#define CONFIG_USB_EHCI_RMOBILE
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
-/* Module stop status bits */
-/* INTC-RT */
-#define CONFIG_SMSTP0_ENA 0x00400000
-/* MSIF*/
-#define CONFIG_SMSTP2_ENA 0x00002000
-/* INTC-SYS, IRQC */
-#define CONFIG_SMSTP4_ENA 0x00000180
-/* SCIF0 */
-#define CONFIG_SMSTP7_ENA 0x00200000
+#define CONFIG_SYS_TMU_CLK_DIV 4
-/* SD */
-#define CONFIG_SH_SDHI_FREQ 97500000
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0"
+
+/* SPL support */
+#define CONFIG_SPL_TEXT_BASE 0xe6300000
+#define CONFIG_SPL_STACK 0xe6340000
+#define CONFIG_SPL_MAX_SIZE 0x4000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF0
+#define CONFIG_SH_SCIF_CLK_FREQ 65000000
+#endif
#endif /* __KOELSCH_H */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
/* MMC */
-#define CONFIG_SH_MMCIF
#define CONFIG_SH_MMCIF_ADDR 0xEE220000
#define CONFIG_SH_MMCIF_CLK 97500000
#define CONFIG_SH_SPI_BASE 0xfe002000
/* MMCIF */
-#define CONFIG_SH_MMCIF 1
#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
#define CONFIG_SH_MMCIF_CLK 48000000
#define CONFIG_SH_SPI_BASE 0xfe002000
/* MMCIF */
-#define CONFIG_SH_MMCIF 1
#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
#define CONFIG_SH_MMCIF_CLK 48000000
#define CONFIG_SH_SPI_BASE 0xfe002000
/* MMCIF */
-#define CONFIG_SH_MMCIF 1
#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
#define CONFIG_SH_MMCIF_CLK 48000000
#include "rcar-gen2-common.h"
-#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
-#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
-#else
-#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
-#endif
-#define STACK_AREA_SIZE 0xC000
+#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
+#define STACK_AREA_SIZE 0x00100000
#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
-#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
-#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
-
-/* i2c */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SH
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
-#define CONFIG_SYS_I2C_SH_SPEED0 400000
-#define CONFIG_SYS_I2C_SH_SPEED1 400000
-#define CONFIG_SYS_I2C_SH_SPEED2 400000
-#define CONFIG_SH_I2C_DATA_HIGH 4
-#define CONFIG_SH_I2C_DATA_LOW 5
-#define CONFIG_SH_I2C_CLOCK 10000000
-
-#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
-
-/* USB */
-#define CONFIG_USB_EHCI_RMOBILE
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
-/* MMCIF */
-#define CONFIG_SH_MMCIF
-#define CONFIG_SH_MMCIF_ADDR 0xee200000
-#define CONFIG_SH_MMCIF_CLK 48000000
-
-/* SDHI */
-#define CONFIG_SH_SDHI_FREQ 97500000
-
-/* Module stop status bits */
-/* INTC-RT */
-#define CONFIG_SMSTP0_ENA 0x00400000
-/* MSIF */
-#define CONFIG_SMSTP2_ENA 0x00002000
-/* INTC-SYS, IRQC */
-#define CONFIG_SMSTP4_ENA 0x00000180
-/* SCIF2 */
-#define CONFIG_SMSTP7_ENA 0x00080000
+#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
+
+#define CONFIG_SYS_TMU_CLK_DIV 4
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0"
+
+/* SPL support */
+#define CONFIG_SPL_TEXT_BASE 0xe6300000
+#define CONFIG_SPL_STACK 0xe6340000
+#define CONFIG_SPL_MAX_SIZE 0x4000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF2
+#define CONFIG_SH_SCIF_CLK_FREQ 65000000
+#endif
#endif /* __SILK_H */
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_MONITOR_BASE 0
-#define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */
+#define CONFIG_SYS_MONITOR_LEN 0x00090000 /* 576KB */
#define CONFIG_SYS_FLASH_BASE 0
/*
"setexpr tmp_addr $nor_base + 0x70000 && " \
"tftpboot $tmp_addr $third_image\0" \
"emmcupdate=mmcsetn &&" \
+ "mmc dev $mmc_first_dev &&" \
"mmc partconf $mmc_first_dev 0 1 1 &&" \
"tftpboot $second_image && " \
"mmc write $loadaddr 0 100 && " \
#define CONFIG_SPL_TEXT_BASE 0x00100000
#endif
-#define CONFIG_SPL_STACK (0x00100000)
+#define CONFIG_SPL_STACK (0x00200000)
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
#endif
/* Total Size of Environment Sector */
-#define CONFIG_ENV_SIZE (128 << 10)
+#ifndef CONFIG_ENV_SIZE
+# define CONFIG_ENV_SIZE (128 << 10)
+#endif
/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* Environment */
#ifndef CONFIG_ENV_IS_NOWHERE
# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# define CONFIG_ENV_OFFSET 0xE0000
+# ifndef CONFIG_ENV_OFFSET
+# define CONFIG_ENV_OFFSET 0xE0000
+# endif
#endif
/* enable preboot to be loaded before CONFIG_BOOTDELAY */
0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b )
#define DEVICE_PATH_TYPE_END 0x7f
+# define DEVICE_PATH_SUB_TYPE_INSTANCE_END 0x01
# define DEVICE_PATH_SUB_TYPE_END 0xff
struct efi_device_path {
const struct efi_device_path *b);
struct efi_object *efi_dp_find_obj(struct efi_device_path *dp,
struct efi_device_path **rem);
-unsigned efi_dp_size(const struct efi_device_path *dp);
+/* get size of the first device path instance excluding end node */
+efi_uintn_t efi_dp_instance_size(const struct efi_device_path *dp);
+/* size of multi-instance device path excluding end node */
+efi_uintn_t efi_dp_size(const struct efi_device_path *dp);
struct efi_device_path *efi_dp_dup(const struct efi_device_path *dp);
struct efi_device_path *efi_dp_append(const struct efi_device_path *dp1,
const struct efi_device_path *dp2);
struct efi_device_path *efi_dp_append_node(const struct efi_device_path *dp,
const struct efi_device_path *node);
-
+/* Create a device path node of given type, sub-type, length */
+struct efi_device_path *efi_dp_create_device_node(const u8 type,
+ const u8 sub_type,
+ const u16 length);
+/* Append device path instance */
+struct efi_device_path *efi_dp_append_instance(
+ const struct efi_device_path *dp,
+ const struct efi_device_path *dpi);
+/* Get next device path instance */
+struct efi_device_path *efi_dp_get_next_instance(struct efi_device_path **dp,
+ efi_uintn_t *size);
+/* Check if a device path contains muliple instances */
+bool efi_dp_is_multi_instance(const struct efi_device_path *dp);
struct efi_device_path *efi_dp_from_dev(struct udevice *dev);
struct efi_device_path *efi_dp_from_part(struct blk_desc *desc, int part);
* @setup: set up the unit test
* @teardown: tear down the unit test
* @execute: execute the unit test
+ * @setup_ok: setup was successful (set at runtime)
* @on_request: test is only executed on request
*/
struct efi_unit_test {
const struct efi_system_table *systable);
int (*execute)(void);
int (*teardown)(void);
+ int setup_ok;
bool on_request;
};
LOGC_CORE,
LOGC_DM, /* Core driver-model */
LOGC_DT, /* Device-tree */
- LOGL_EFI, /* EFI implementation */
+ LOGC_EFI, /* EFI implementation */
LOGC_COUNT,
LOGC_END,
config EFI_LOADER
bool "Support running EFI Applications in U-Boot"
depends on (ARM || X86) && OF_LIBFDT
+ # We do not support bootefi booting ARMv7 in non-secure mode
+ depends on !ARMV7_NONSEC
# We need EFI_STUB_64BIT to be set on x86_64 with EFI_STUB
depends on !EFI_STUB || !X86_64 || EFI_STUB_64BIT
# We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB
}
/* Find end of device path */
- len = efi_dp_size(*device_path);
+ len = efi_dp_instance_size(*device_path);
/* Get all handles implementing the protocol */
ret = EFI_CALL(efi_locate_handle_buffer(BY_PROTOCOL, protocol, NULL,
if (ret != EFI_SUCCESS)
continue;
dp = (struct efi_device_path *)handler->protocol_interface;
- len_dp = efi_dp_size(dp);
+ len_dp = efi_dp_instance_size(dp);
/*
* This handle can only be a better fit
* if its device path length is longer than the best fit and
struct efi_device_path **rem)
{
struct efi_object *efiobj;
- unsigned int dp_size = efi_dp_size(dp);
+ efi_uintn_t dp_size = efi_dp_instance_size(dp);
list_for_each_entry(efiobj, &efi_obj_list, link) {
struct efi_handler *handler;
* the caller.
*/
*rem = ((void *)dp) +
- efi_dp_size(obj_dp);
+ efi_dp_instance_size(obj_dp);
return efiobj;
} else {
/* Only return on exact matches */
- if (efi_dp_size(obj_dp) == dp_size)
+ if (efi_dp_instance_size(obj_dp) ==
+ dp_size)
return efiobj;
}
}
return ret;
}
-/* return size not including End node: */
-unsigned efi_dp_size(const struct efi_device_path *dp)
+/* get size of the first device path instance excluding end node */
+efi_uintn_t efi_dp_instance_size(const struct efi_device_path *dp)
{
- unsigned sz = 0;
+ efi_uintn_t sz = 0;
+ if (!dp || dp->type == DEVICE_PATH_TYPE_END)
+ return 0;
while (dp) {
sz += dp->length;
dp = efi_dp_next(dp);
return sz;
}
+/* get size of multi-instance device path excluding end node */
+efi_uintn_t efi_dp_size(const struct efi_device_path *dp)
+{
+ const struct efi_device_path *p = dp;
+
+ if (!p)
+ return 0;
+ while (p->type != DEVICE_PATH_TYPE_END ||
+ p->sub_type != DEVICE_PATH_SUB_TYPE_END)
+ p = (void *)p + p->length;
+
+ return (void *)p - (void *)dp;
+}
+
+/* copy multi-instance device path */
struct efi_device_path *efi_dp_dup(const struct efi_device_path *dp)
{
struct efi_device_path *ndp;
- unsigned sz = efi_dp_size(dp) + sizeof(END);
+ size_t sz = efi_dp_size(dp) + sizeof(END);
if (!dp)
return NULL;
{
struct efi_device_path *ret;
- if (!dp1) {
+ if (!dp1 && !dp2) {
+ /* return an end node */
+ ret = efi_dp_dup(&END);
+ } else if (!dp1) {
ret = efi_dp_dup(dp2);
} else if (!dp2) {
ret = efi_dp_dup(dp1);
if (!p)
return NULL;
memcpy(p, dp1, sz1);
- memcpy(p + sz1, dp2, sz2);
- memcpy(p + sz1 + sz2, &END, sizeof(END));
+ /* the end node of the second device path has to be retained */
+ memcpy(p + sz1, dp2, sz2 + sizeof(END));
ret = p;
}
} else if (!node) {
ret = efi_dp_dup(dp);
} else if (!dp) {
- unsigned sz = node->length;
+ size_t sz = node->length;
void *p = dp_alloc(sz + sizeof(END));
if (!p)
return NULL;
ret = p;
} else {
/* both dp and node are non-null */
- unsigned sz = efi_dp_size(dp);
+ size_t sz = efi_dp_size(dp);
void *p = dp_alloc(sz + node->length + sizeof(END));
if (!p)
return NULL;
return ret;
}
+struct efi_device_path *efi_dp_create_device_node(const u8 type,
+ const u8 sub_type,
+ const u16 length)
+{
+ struct efi_device_path *ret;
+
+ ret = dp_alloc(length);
+ if (!ret)
+ return ret;
+ ret->type = type;
+ ret->sub_type = sub_type;
+ ret->length = length;
+ return ret;
+}
+
+struct efi_device_path *efi_dp_append_instance(
+ const struct efi_device_path *dp,
+ const struct efi_device_path *dpi)
+{
+ size_t sz, szi;
+ struct efi_device_path *p, *ret;
+
+ if (!dpi)
+ return NULL;
+ if (!dp)
+ return efi_dp_dup(dpi);
+ sz = efi_dp_size(dp);
+ szi = efi_dp_instance_size(dpi);
+ p = dp_alloc(sz + szi + 2 * sizeof(END));
+ if (!p)
+ return NULL;
+ ret = p;
+ memcpy(p, dp, sz + sizeof(END));
+ p = (void *)p + sz;
+ p->sub_type = DEVICE_PATH_SUB_TYPE_INSTANCE_END;
+ p = (void *)p + sizeof(END);
+ memcpy(p, dpi, szi);
+ p = (void *)p + szi;
+ memcpy(p, &END, sizeof(END));
+ return ret;
+}
+
+struct efi_device_path *efi_dp_get_next_instance(struct efi_device_path **dp,
+ efi_uintn_t *size)
+{
+ size_t sz;
+ struct efi_device_path *p;
+
+ if (size)
+ *size = 0;
+ if (!dp || !*dp)
+ return NULL;
+ p = *dp;
+ sz = efi_dp_instance_size(*dp);
+ p = dp_alloc(sz + sizeof(END));
+ if (!p)
+ return NULL;
+ memcpy(p, *dp, sz + sizeof(END));
+ *dp = (void *)*dp + sz;
+ if ((*dp)->sub_type == DEVICE_PATH_SUB_TYPE_INSTANCE_END)
+ *dp = (void *)*dp + sizeof(END);
+ else
+ *dp = NULL;
+ if (size)
+ *size = sz + sizeof(END);
+ return p;
+}
+
+bool efi_dp_is_multi_instance(const struct efi_device_path *dp)
+{
+ const struct efi_device_path *p = dp;
+
+ if (!p)
+ return false;
+ while (p->type != DEVICE_PATH_TYPE_END)
+ p = (void *)p + p->length;
+ return p->sub_type == DEVICE_PATH_SUB_TYPE_INSTANCE_END;
+}
+
#ifdef CONFIG_DM
/* size of device-path not including END node for device and all parents
* up to the root device.
const efi_guid_t efi_guid_device_path_utilities_protocol =
EFI_DEVICE_PATH_UTILITIES_PROTOCOL_GUID;
+/*
+ * Get size of a device path.
+ *
+ * This function implements the GetDevicePathSize service of the device path
+ * utilities protocol. The device path length includes the end of path tag
+ * which may be an instance end.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @device_path device path
+ * @return size in bytes
+ */
static efi_uintn_t EFIAPI get_device_path_size(
const struct efi_device_path *device_path)
{
efi_uintn_t sz = 0;
- EFI_ENTRY("%p", device_path);
+ EFI_ENTRY("%pD", device_path);
/* size includes the END node: */
if (device_path)
sz = efi_dp_size(device_path) + sizeof(struct efi_device_path);
return EFI_EXIT(sz);
}
+/*
+ * Duplicate a device path.
+ *
+ * This function implements the DuplicateDevicePath service of the device path
+ * utilities protocol.
+ *
+ * The UEFI spec does not indicate what happens to the end tag. We follow the
+ * EDK2 logic: In case the device path ends with an end of instance tag, the
+ * copy will also end with an end of instance tag.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @device_path device path
+ * @return copy of the device path
+ */
static struct efi_device_path * EFIAPI duplicate_device_path(
const struct efi_device_path *device_path)
{
- EFI_ENTRY("%p", device_path);
+ EFI_ENTRY("%pD", device_path);
return EFI_EXIT(efi_dp_dup(device_path));
}
+/*
+ * Append device path.
+ *
+ * This function implements the AppendDevicePath service of the device path
+ * utilities protocol.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @src1 1st device path
+ * @src2 2nd device path
+ * @return concatenated device path
+ */
static struct efi_device_path * EFIAPI append_device_path(
const struct efi_device_path *src1,
const struct efi_device_path *src2)
{
- EFI_ENTRY("%p, %p", src1, src2);
+ EFI_ENTRY("%pD, %pD", src1, src2);
return EFI_EXIT(efi_dp_append(src1, src2));
}
+/*
+ * Append device path node.
+ *
+ * This function implements the AppendDeviceNode service of the device path
+ * utilities protocol.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @device_path device path
+ * @device_node device node
+ * @return concatenated device path
+ */
static struct efi_device_path * EFIAPI append_device_node(
const struct efi_device_path *device_path,
const struct efi_device_path *device_node)
{
- EFI_ENTRY("%p, %p", device_path, device_node);
+ EFI_ENTRY("%pD, %p", device_path, device_node);
return EFI_EXIT(efi_dp_append_node(device_path, device_node));
}
+/*
+ * Append device path instance.
+ *
+ * This function implements the AppendDevicePathInstance service of the device
+ * path utilities protocol.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @device_path 1st device path
+ * @device_path_instance 2nd device path
+ * @return concatenated device path
+ */
static struct efi_device_path * EFIAPI append_device_path_instance(
const struct efi_device_path *device_path,
const struct efi_device_path *device_path_instance)
{
- EFI_ENTRY("%p, %p", device_path, device_path_instance);
- return EFI_EXIT(NULL);
+ EFI_ENTRY("%pD, %pD", device_path, device_path_instance);
+ return EFI_EXIT(efi_dp_append_instance(device_path,
+ device_path_instance));
}
+/*
+ * Get next device path instance.
+ *
+ * This function implements the GetNextDevicePathInstance service of the device
+ * path utilities protocol.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @device_path_instance next device path instance
+ * @device_path_instance_size size of the device path instance
+ * @return concatenated device path
+ */
static struct efi_device_path * EFIAPI get_next_device_path_instance(
struct efi_device_path **device_path_instance,
efi_uintn_t *device_path_instance_size)
{
- EFI_ENTRY("%p, %p", device_path_instance, device_path_instance_size);
- return EFI_EXIT(NULL);
+ EFI_ENTRY("%pD, %p", device_path_instance, device_path_instance_size);
+ return EFI_EXIT(efi_dp_get_next_instance(device_path_instance,
+ device_path_instance_size));
}
+/*
+ * Check if a device path contains more than one instance.
+ *
+ * This function implements the AppendDeviceNode service of the device path
+ * utilities protocol.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @device_path device path
+ * @device_node device node
+ * @return concatenated device path
+ */
static bool EFIAPI is_device_path_multi_instance(
const struct efi_device_path *device_path)
{
- EFI_ENTRY("%p", device_path);
- return EFI_EXIT(false);
+ EFI_ENTRY("%pD", device_path);
+ return EFI_EXIT(efi_dp_is_multi_instance(device_path));
}
+/*
+ * Create device node.
+ *
+ * This function implements the CreateDeviceNode service of the device path
+ * utilities protocol.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @node_type node type
+ * @node_sub_type node sub type
+ * @node_length node length
+ * @return device path node
+ */
static struct efi_device_path * EFIAPI create_device_node(
uint8_t node_type, uint8_t node_sub_type, uint16_t node_length)
{
EFI_ENTRY("%u, %u, %u", node_type, node_sub_type, node_length);
- return EFI_EXIT(NULL);
+ return EFI_EXIT(efi_dp_create_device_node(node_type, node_sub_type,
+ node_length));
}
const struct efi_device_path_utilities_protocol efi_device_path_utilities = {
efi_selftest_controllers.o \
efi_selftest_console.o \
efi_selftest_devicepath.o \
+efi_selftest_devicepath_util.o \
efi_selftest_events.o \
efi_selftest_event_groups.o \
efi_selftest_exitbootservices.o \
*/
static int setup(struct efi_unit_test *test, unsigned int *failures)
{
- int ret;
-
- if (!test->setup)
+ if (!test->setup) {
+ test->setup_ok = EFI_ST_SUCCESS;
return EFI_ST_SUCCESS;
+ }
efi_st_printc(EFI_LIGHTBLUE, "\nSetting up '%s'\n", test->name);
- ret = test->setup(handle, systable);
- if (ret != EFI_ST_SUCCESS) {
+ test->setup_ok = test->setup(handle, systable);
+ if (test->setup_ok != EFI_ST_SUCCESS) {
efi_st_error("Setting up '%s' failed\n", test->name);
++*failures;
} else {
efi_st_printc(EFI_LIGHTGREEN,
"Setting up '%s' succeeded\n", test->name);
}
- return ret;
+ return test->setup_ok;
}
/*
continue;
if (steps & EFI_ST_SETUP)
setup(test, failures);
- if (steps & EFI_ST_EXECUTE)
+ if (steps & EFI_ST_EXECUTE && test->setup_ok == EFI_ST_SUCCESS)
execute(test, failures);
if (steps & EFI_ST_TEARDOWN)
teardown(test, failures);
* Setup unit test.
*
* Create three handles. Install a new protocol on two of them and
- * provice device paths.
+ * provide device paths.
*
* handle1
* guid interface
--- /dev/null
+/*
+ * efi_selftest_devicepath_util
+ *
+ * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This unit test checks the device path utilities protocol.
+ */
+
+#include <efi_selftest.h>
+
+static struct efi_boot_services *boottime;
+
+static efi_guid_t guid_device_path_utilities_protocol =
+ EFI_DEVICE_PATH_UTILITIES_PROTOCOL_GUID;
+
+struct efi_device_path_utilities_protocol *dpu;
+
+/*
+ * Setup unit test.
+ *
+ * Locate the device path utilities protocol.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ */
+static int setup(const efi_handle_t img_handle,
+ const struct efi_system_table *systable)
+{
+ int ret;
+
+ boottime = systable->boottime;
+
+ ret = boottime->locate_protocol(&guid_device_path_utilities_protocol,
+ NULL, (void **)&dpu);
+ if (ret != EFI_SUCCESS) {
+ dpu = NULL;
+ efi_st_error(
+ "Device path to text protocol is not available.\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Create a device path consisting of a single media device node followed by an
+ * end node.
+ *
+ * @length: length of the media device node
+ * @dp: device path
+ * @return: status code
+ */
+static int create_single_node_device_path(unsigned int length,
+ struct efi_device_path **dp)
+{
+ struct efi_device_path *node;
+ efi_uintn_t len;
+ int ret;
+
+ node = dpu->create_device_node(DEVICE_PATH_TYPE_MEDIA_DEVICE,
+ DEVICE_PATH_SUB_TYPE_FILE_PATH, length);
+ if (!node) {
+ efi_st_error("CreateDeviceNode failed\n");
+ return EFI_ST_FAILURE;
+ }
+ *dp = dpu->append_device_node(NULL, node);
+ if (!*dp) {
+ efi_st_error("AppendDeviceNode failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(node);
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ len = dpu->get_device_path_size(*dp);
+ if (len != length + 4) {
+ efi_st_error("Wrong device path length %u, expected %u\n",
+ (unsigned int)len, length);
+ return EFI_ST_FAILURE;
+ }
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Execute unit test.
+ *
+ * In the test device paths are created, copied, and concatenated. The device
+ * path length is used as a measure of success.
+ */
+static int execute(void)
+{
+ struct efi_device_path *dp1;
+ struct efi_device_path *dp2;
+ struct efi_device_path *dp3;
+
+ efi_uintn_t len;
+ int ret;
+
+ /* IsDevicePathMultiInstance(NULL) */
+ if (dpu->is_device_path_multi_instance(NULL)) {
+ efi_st_error("IsDevicePathMultiInstance(NULL) returned true\n");
+ return EFI_ST_FAILURE;
+ }
+ /* GetDevicePathSize(NULL) */
+ len = dpu->get_device_path_size(NULL);
+ if (len) {
+ efi_st_error("Wrong device path length %u, expected 0\n",
+ (unsigned int)len);
+ return EFI_ST_FAILURE;
+ }
+ /* DuplicateDevicePath(NULL) */
+ dp1 = dpu->duplicate_device_path(NULL);
+ if (dp1) {
+ efi_st_error("DuplicateDevicePath(NULL) failed\n");
+ return EFI_ST_FAILURE;
+ }
+ /* AppendDevicePath(NULL, NULL) */
+ dp1 = dpu->append_device_path(NULL, NULL);
+ if (!dp1) {
+ efi_st_error("AppendDevicePath(NULL, NULL) failed\n");
+ return EFI_ST_FAILURE;
+ }
+ len = dpu->get_device_path_size(dp1);
+ if (len != 4) {
+ efi_st_error("Wrong device path length %u, expected 4\n",
+ (unsigned int)len);
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(dp1);
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ /* CreateDeviceNode */
+ ret = create_single_node_device_path(21, &dp1);
+ if (ret != EFI_ST_SUCCESS)
+ return ret;
+ ret = create_single_node_device_path(17, &dp2);
+ if (ret != EFI_ST_SUCCESS)
+ return ret;
+ /* AppendDevicePath */
+ dp3 = dpu->append_device_path(dp1, dp2);
+ if (!dp3) {
+ efi_st_error("AppendDevicePath failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (dp3 == dp1 || dp3 == dp2) {
+ efi_st_error("AppendDevicePath reused buffer\n");
+ return EFI_ST_FAILURE;
+ }
+ len = dpu->get_device_path_size(dp3);
+ /* 21 + 17 + 4 */
+ if (len != 42) {
+ efi_st_error("Wrong device path length %u, expected 42\n",
+ (unsigned int)len);
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(dp2);
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ /* AppendDeviceNode */
+ dp2 = dpu->append_device_node(dp1, dp3);
+ if (!dp2) {
+ efi_st_error("AppendDevicePath failed\n");
+ return EFI_ST_FAILURE;
+ }
+ len = dpu->get_device_path_size(dp2);
+ /* 21 + 21 + 4 */
+ if (len != 46) {
+ printf("%s(%d) %s\n", __FILE__, __LINE__, __func__);
+ efi_st_error("Wrong device path length %u, expected 46\n",
+ (unsigned int)len);
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(dp1);
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ /* IsDevicePathMultiInstance */
+ if (dpu->is_device_path_multi_instance(dp2)) {
+ printf("%s(%d) %s\n", __FILE__, __LINE__, __func__);
+ efi_st_error("IsDevicePathMultiInstance returned true\n");
+ return EFI_ST_FAILURE;
+ }
+ /* AppendDevicePathInstance */
+ dp1 = dpu->append_device_path_instance(dp2, dp3);
+ if (!dp1) {
+ efi_st_error("AppendDevicePathInstance failed\n");
+ return EFI_ST_FAILURE;
+ }
+ len = dpu->get_device_path_size(dp1);
+ /* 46 + 42 */
+ if (len != 88) {
+ efi_st_error("Wrong device path length %u, expected 88\n",
+ (unsigned int)len);
+ return EFI_ST_FAILURE;
+ }
+ /* IsDevicePathMultiInstance */
+ if (!dpu->is_device_path_multi_instance(dp1)) {
+ efi_st_error("IsDevicePathMultiInstance returned false\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(dp2);
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(dp3);
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ /* GetNextDevicePathInstance */
+ dp3 = dp1;
+ dp2 = dpu->get_next_device_path_instance(&dp1, &len);
+ if (!dp2) {
+ efi_st_error("GetNextDevicePathInstance failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (!dp1) {
+ efi_st_error("GetNextDevicePathInstance no 2nd instance\n");
+ return EFI_ST_FAILURE;
+ }
+ if (len != 46) {
+ efi_st_error("Wrong device path length %u, expected 46\n",
+ (unsigned int)len);
+ return EFI_ST_FAILURE;
+ }
+ len = dpu->get_device_path_size(dp1);
+ if (len != 42) {
+ efi_st_error("Wrong device path length %u, expected 42\n",
+ (unsigned int)len);
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(dp2);
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ dp2 = dpu->get_next_device_path_instance(&dp1, &len);
+ if (!dp2) {
+ efi_st_error("GetNextDevicePathInstance failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (len != 42) {
+ efi_st_error("Wrong device path length %u, expected 46\n",
+ (unsigned int)len);
+ return EFI_ST_FAILURE;
+ }
+ if (dp1) {
+ efi_st_error("GetNextDevicePathInstance did not signal end\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(dp2);
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ /* Clean up */
+ ret = boottime->free_pool(dp2);
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->free_pool(dp3);
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(dputil) = {
+ .name = "device path utilities protocol",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+};
CONFIG_SH_I2C_CLOCK
CONFIG_SH_I2C_DATA_HIGH
CONFIG_SH_I2C_DATA_LOW
-CONFIG_SH_MMCIF
CONFIG_SH_MMCIF_ADDR
CONFIG_SH_MMCIF_CLK
CONFIG_SH_QSPI_BASE
projects / oweals / u-boot.git / commitdiff