mpc8xxx: LCRR[CLKDIV] is sometimes five bits
authorTrent Piepho <tpiepho@freescale.com>
Wed, 3 Dec 2008 23:16:34 +0000 (15:16 -0800)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Sat, 20 Dec 2008 00:20:25 +0000 (18:20 -0600)
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.

In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems.  It
should be safe as the fifth bit was defined as reserved and set to 0.

Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
15 files changed:
board/freescale/mpc8540ads/mpc8540ads.c
board/freescale/mpc8541cds/mpc8541cds.c
board/freescale/mpc8548cds/mpc8548cds.c
board/freescale/mpc8555cds/mpc8555cds.c
board/freescale/mpc8560ads/mpc8560ads.c
board/freescale/mpc8568mds/mpc8568mds.c
board/mpc8540eval/mpc8540eval.c
board/pm854/pm854.c
board/pm856/pm856.c
board/sbc8548/sbc8548.c
board/socrates/socrates.c
board/tqc/tqm85xx/tqm85xx.c
cpu/mpc85xx/cpu.c
cpu/mpc86xx/cpu.c
include/asm-ppc/fsl_lbc.h

index a0b6fbd121606da784da8697fb58bb4d57e81875..9e3f67768cf09e4ca8f5d9b7025fd610344bdbf3 100644 (file)
@@ -133,7 +133,7 @@ local_bus_init(void)
         */
 
        get_sys_info(&sysinfo);
-       clkdiv = lbc->lcrr & 0x0f;
+       clkdiv = lbc->lcrr & LCRR_CLKDIV;
        lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
        if (lbc_hz < 66) {
index 7e40c5c80a04895d4ba32c607433441e6255023c..e6025c8a567096a766b55422a860972b68db9864 100644 (file)
@@ -308,7 +308,7 @@ local_bus_init(void)
         */
 
        get_sys_info(&sysinfo);
-       clkdiv = lbc->lcrr & 0x0f;
+       clkdiv = lbc->lcrr & LCRR_CLKDIV;
        lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
        if (lbc_hz < 66) {
index c562fc9d95524ed80c6dbef12983b66800bc5613..90e89bc71927363e91792879b17e117211d2e2aa 100644 (file)
@@ -125,7 +125,7 @@ local_bus_init(void)
        sys_info_t sysinfo;
 
        get_sys_info(&sysinfo);
-       clkdiv = (lbc->lcrr & 0x0f) * 2;
+       clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
        lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
        gur->lbiuiplldcr1 = 0x00078080;
index 33685c19f392339f8693b58cea1ff7a522db622d..53d5a936af3a499a24e6598ec88e2bbc52339bee 100644 (file)
@@ -308,7 +308,7 @@ local_bus_init(void)
         */
 
        get_sys_info(&sysinfo);
-       clkdiv = lbc->lcrr & 0x0f;
+       clkdiv = lbc->lcrr & LCRR_CLKDIV;
        lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
        if (lbc_hz < 66) {
index 37308189d20d6aa04caab70046e53dfced23019c..ac7778e25c7c40f87448c5a7947472e480431cfa 100644 (file)
@@ -337,7 +337,7 @@ local_bus_init(void)
         */
 
        get_sys_info(&sysinfo);
-       clkdiv = lbc->lcrr & 0x0f;
+       clkdiv = lbc->lcrr & LCRR_CLKDIV;
        lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
        if (lbc_hz < 66) {
index bc93be80fcba278d4ab983fb59e440d5697636d5..7a23b338a593e3fdb5494a116808c5ee437ac1c3 100644 (file)
@@ -188,7 +188,7 @@ local_bus_init(void)
        sys_info_t sysinfo;
 
        get_sys_info(&sysinfo);
-       clkdiv = (lbc->lcrr & 0x0f) * 2;
+       clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
        lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
        gur->lbiuiplldcr1 = 0x00078080;
index fa0a33686664e91b47ef126234b42eef62a078d5..bf270f4ce647a672e52c4f9197cf6f42e4fc7ef0 100644 (file)
@@ -101,7 +101,7 @@ phys_size_t initdram (int board_type)
 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
        get_sys_info(&sysinfo);
        /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
-       if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
+       if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) {
                lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
        } else {
                lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
index fed0ed431872b5149ddcf100e5a79827e1286b73..5353d738b4cfe13c55875db5fc8a0cc36bc61227 100644 (file)
@@ -150,7 +150,7 @@ local_bus_init(void)
         */
 
        get_sys_info(&sysinfo);
-       clkdiv = lbc->lcrr & 0x0f;
+       clkdiv = lbc->lcrr & LCRR_CLKDIV;
        lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
        if (lbc_hz < 66) {
index 932f1121e858498fdf19829c3b8dde07375e6614..b14a3d34b1f66abf794d39cad2518dc31e746f4b 100644 (file)
@@ -306,7 +306,7 @@ local_bus_init(void)
         */
 
        get_sys_info(&sysinfo);
-       clkdiv = lbc->lcrr & 0x0f;
+       clkdiv = lbc->lcrr & LCRR_CLKDIV;
        lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
        if (lbc_hz < 66) {
index 8c073cb4bb28a983492471d9c5e056ad4822c4f1..519b0f749d315c3635970d046dcad66de639f22a 100644 (file)
@@ -126,7 +126,7 @@ local_bus_init(void)
        sys_info_t sysinfo;
 
        get_sys_info(&sysinfo);
-       clkdiv = (lbc->lcrr & 0x0f) * 2;
+       clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
        lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
        gur->lbiuiplldcr1 = 0x00078080;
index d83dc7d6a3fcd1d309c9f7cfdafe0ea952b959fa..df9696e69a39cc8d6aed6ea6d209e093f00ab0bc 100644 (file)
@@ -156,7 +156,7 @@ void local_bus_init (void)
        uint lcrr = CONFIG_SYS_LBC_LCRR;
 
        get_sys_info (&sysinfo);
-       clkdiv = lbc->lcrr & 0x0f;
+       clkdiv = lbc->lcrr & LCRR_CLKDIV;
        lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
        /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
index 73f1d01bdf23d52c143b06baf34e146456732690..cda8208eec270f14462f34cd43919fadb67f76fb 100644 (file)
@@ -361,7 +361,7 @@ uint get_lbc_clock (void)
 {
        volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
        sys_info_t sys_info;
-       ulong clkdiv = lbc->lcrr & 0x0f;
+       ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
 
        get_sys_info (&sys_info);
 
index 943602f923ee91d109949e84d7546d33be426764..59a9ac8d923513475b6a59c2627227a6d3689137 100644 (file)
@@ -174,7 +174,7 @@ int checkcpu (void)
            lcrr = lbc->lcrr;
        }
 #endif
-       clkdiv = lcrr & 0x0f;
+       clkdiv = lcrr & LCRR_CLKDIV;
        if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
 #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
     defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
index 4cace984d91743e3fd2d45cf2ed9ad7d2aefbb76..0ff76e3f7ed65e0c830f9116e85543ea35968abe 100644 (file)
@@ -110,7 +110,7 @@ checkcpu(void)
                lcrr = lbc->lcrr;
        }
 #endif
-       clkdiv = lcrr & 0x0f;
+       clkdiv = lcrr & LCRR_CLKDIV;
        if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
                printf("LBC:%4lu MHz\n",
                       sysinfo.freqSystemBus / 1000000 / clkdiv);
index 51fc5c13b0b2dcc84cecc08fd36fec6e8e5e7171..e492c62a8bcb09053e1d50f31e5d863d75bcf8fb 100644 (file)
 #define LCRR_EADC_2                    0x00020000
 #define LCRR_EADC_3                    0x00030000
 #define LCRR_EADC_4                    0x00000000
-#define LCRR_CLKDIV                    0x0000000F
+/* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit
+ * should always be zero on older parts that have a four bit CLKDIV.
+ */
+#define LCRR_CLKDIV                    0x0000001F
 #define LCRR_CLKDIV_SHIFT              0
 #define LCRR_CLKDIV_2                  0x00000002
 #define LCRR_CLKDIV_4                  0x00000004