#concatenated with u-boot binary. It is need by PowerPC SoC having
#internal SRAM <= 512KB.
MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
- -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
+ -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage \
+ -A $(ARCH) -a $(CONFIG_SPL_TEXT_BASE)
spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
+ifeq ($(ARCH),arm)
+UBOOT_BINLOAD := u-boot.img
+else
+UBOOT_BINLOAD := u-boot.bin
+endif
+
OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
--gap-fill=0xff
-u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl u-boot.bin FORCE
+u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl $(UBOOT_BINLOAD) FORCE
$(call if_changed,pad_cat)
# PPC4xx needs the SPL at the end of the image, since the reset vector
select ARM64
config TARGET_LS1021AQDS
- bool "Support ls1021aqds_nor"
+ bool "Support ls1021aqds"
select CPU_V7
+ select SUPPORT_SPL
config TARGET_LS1021ATWR
- bool "Support ls1021atwr_nor"
+ bool "Support ls1021atwr"
select CPU_V7
+ select SUPPORT_SPL
config TARGET_BALLOON3
bool "Support balloon3"
obj-y += cpu.o
obj-y += clock.o
obj-y += timer.o
+obj-y += fsl_epu.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
+obj-$(CONFIG_SPL) += spl.o
#include <netdev.h>
#include <fsl_esdhc.h>
+#include "fsl_epu.h"
+
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_DISPLAY_CPUINFO)
return 0;
}
+
+int arch_cpu_init(void)
+{
+ void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+
+ /*
+ * After wakeup from deep sleep, Clear EPU registers
+ * as early as possible to prevent from possible issue.
+ * It's also safe to clear at normal boot.
+ */
+ fsl_epu_clean(epu_base);
+
+ return 0;
+}
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+/* Set the address at which the secondary core starts from.*/
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ out_be32(&gur->scratchrw[0], addr);
+}
+
+/* Release the secondary core from holdoff state and kick it */
+void smp_kick_all_cpus(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ out_be32(&gur->brrl, 0x2);
+}
+#endif
}
do_fixup_by_prop_u32(blob, "device_type", "soc",
- 4, "bus-frequency", busclk / 2, 1);
+ 4, "bus-frequency", busclk, 1);
ft_fixup_enet_phy_connect_type(blob);
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "fsl_epu.h"
+
+/**
+ * fsl_epu_clean - Clear EPU registers
+ */
+void fsl_epu_clean(void *epu_base)
+{
+ u32 offset;
+
+ /* follow the exact sequence to clear the registers */
+ /* Clear EPACRn */
+ for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPEVTCRn */
+ for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPGCR */
+ out_be32(epu_base + EPGCR, 0);
+
+ /* Clear EPSMCRn */
+ for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPCCRn */
+ for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPCMPRn */
+ for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPCTRn */
+ for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPIMCRn */
+ for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPXTRIGCRn */
+ out_be32(epu_base + EPXTRIGCR, 0);
+
+ /* Clear EPECRn */
+ for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
+ out_be32(epu_base + offset, 0);
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_EPU_H
+#define __FSL_EPU_H
+
+#include <asm/types.h>
+
+#define FSL_STRIDE_4B 4
+#define FSL_STRIDE_8B 8
+
+/* Block offsets */
+#define EPU_BLOCK_OFFSET 0x00000000
+
+/* EPGCR (Event Processor Global Control Register) */
+#define EPGCR 0x000
+
+/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
+#define EPEVTCR0 0x050
+#define EPEVTCR9 0x074
+#define EPEVTCR_STRIDE FSL_STRIDE_4B
+
+/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+#define EPXTRIGCR 0x090
+
+/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
+#define EPIMCR0 0x100
+#define EPIMCR31 0x17C
+#define EPIMCR_STRIDE FSL_STRIDE_4B
+
+/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
+#define EPSMCR0 0x200
+#define EPSMCR15 0x278
+#define EPSMCR_STRIDE FSL_STRIDE_8B
+
+/* EPECR0-15 (Event Processor Event Control Registers) */
+#define EPECR0 0x300
+#define EPECR15 0x33C
+#define EPECR_STRIDE FSL_STRIDE_4B
+
+/* EPACR0-15 (Event Processor Action Control Registers) */
+#define EPACR0 0x400
+#define EPACR15 0x43C
+#define EPACR_STRIDE FSL_STRIDE_4B
+
+/* EPCCRi0-15 (Event Processor Counter Control Registers) */
+#define EPCCR0 0x800
+#define EPCCR15 0x83C
+#define EPCCR31 0x87C
+#define EPCCR_STRIDE FSL_STRIDE_4B
+
+/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
+#define EPCMPR0 0x900
+#define EPCMPR15 0x93C
+#define EPCMPR31 0x97C
+#define EPCMPR_STRIDE FSL_STRIDE_4B
+
+/* EPCTR0-31 (Event Processor Counter Register) */
+#define EPCTR0 0xA00
+#define EPCTR31 0xA7C
+#define EPCTR_STRIDE FSL_STRIDE_4B
+
+void fsl_epu_clean(void *epu_base);
+
+#endif
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ return BOOT_DEVICE_MMC1;
+#endif
+ return BOOT_DEVICE_NAND;
+}
+
+u32 spl_boot_mode(void)
+{
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_MMC1:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+ return MMCSD_MODE_FAT;
+#else
+ return MMCSD_MODE_RAW;
+#endif
+ case BOOT_DEVICE_NAND:
+ return 0;
+ default:
+ puts("spl: error: unsupported device\n");
+ hang();
+ }
+}
* we do this here instead.
* But first check if we have the generic timer.
*/
-#ifdef CONFIG_SYS_CLK_FREQ
+#ifdef CONFIG_TIMER_CLK_FREQ
mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits
cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
- ldreq r1, =CONFIG_SYS_CLK_FREQ
+ ldreq r1, =CONFIG_TIMER_CLK_FREQ
mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
#endif
wfi
ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address
ldr r1, [r1]
+#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
+ rev r1, r1
+#endif
cmp r0, r1 @ make sure we dont execute this code
beq smp_waitloop @ again (due to a spurious wakeup)
mov r0, r1
}
. = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*_i2c_*)));
+ }
. = .;
#ifdef CONFIG_SPL_DM
#define OCRAM_BASE_ADDR 0x10000000
#define OCRAM_SIZE 0x00020000
+#define OCRAM_BASE_S_ADDR 0x10010000
+#define OCRAM_S_SIZE 0x00010000
#define CONFIG_SYS_IMMR 0x01000000
+#define CONFIG_SYS_DCSRBAR 0x20000000
+
+#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
+#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
+#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
+#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
+
#ifdef CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_VERY_BIG_RAM
#define SOC_VER_LS1021 0x11
#define SOC_VER_LS1022 0x12
+#define CCSR_BRR_OFFSET 0xe4
+#define CCSR_SCRATCHRW1_OFFSET 0x200
+
#define RCWSR0_SYS_PLL_RAT_SHIFT 25
#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
#define RCWSR0_MEM_PLL_RAT_SHIFT 16
#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
#define SYS_COUNTER_CTRL_ENABLE (1 << 24)
+#define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000
+#define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000
+
+#define DCFG_DCSR_PORCR1 0
+
struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
unsigned long freq_systembus;
#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
#define SCFG_PIXCLKCR_PXCKEN 0x80000000
+#define SCFG_QSPI_CLKSEL 0xc0100000
/* Supplemental Configuration Unit */
struct ccsr_scfg {
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_LS102XA_STREAM_ID_H_
+#define __FSL_LS102XA_STREAM_ID_H_
+
+struct smmu_stream_id {
+ uint16_t offset;
+ uint16_t stream_id;
+ char dev_name[32];
+};
+
+void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
+#endif
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_NS_ACCESS_H_
+#define __FSL_NS_ACCESS_H_
+
+enum csu_cslx_access {
+ CSU_NS_SUP_R = 0x08,
+ CSU_NS_SUP_W = 0x80,
+ CSU_NS_SUP_RW = 0x88,
+ CSU_NS_USER_R = 0x04,
+ CSU_NS_USER_W = 0x40,
+ CSU_NS_USER_RW = 0x44,
+ CSU_S_SUP_R = 0x02,
+ CSU_S_SUP_W = 0x20,
+ CSU_S_SUP_RW = 0x22,
+ CSU_S_USER_R = 0x01,
+ CSU_S_USER_W = 0x10,
+ CSU_S_USER_RW = 0x11,
+ CSU_ALL_RW = 0xff,
+};
+
+enum csu_cslx_ind {
+ CSU_CSLX_PCIE2_IO = 0,
+ CSU_CSLX_PCIE1_IO,
+ CSU_CSLX_MG2TPR_IP,
+ CSU_CSLX_IFC_MEM,
+ CSU_CSLX_OCRAM,
+ CSU_CSLX_GIC,
+ CSU_CSLX_PCIE1,
+ CSU_CSLX_OCRAM2,
+ CSU_CSLX_QSPI_MEM,
+ CSU_CSLX_PCIE2,
+ CSU_CSLX_SATA,
+ CSU_CSLX_USB3,
+ CSU_CSLX_SERDES = 32,
+ CSU_CSLX_QDMA,
+ CSU_CSLX_LPUART2,
+ CSU_CSLX_LPUART1,
+ CSU_CSLX_LPUART4,
+ CSU_CSLX_LPUART3,
+ CSU_CSLX_LPUART6,
+ CSU_CSLX_LPUART5,
+ CSU_CSLX_DSPI2 = 40,
+ CSU_CSLX_DSPI1,
+ CSU_CSLX_QSPI,
+ CSU_CSLX_ESDHC,
+ CSU_CSLX_2D_ACE,
+ CSU_CSLX_IFC,
+ CSU_CSLX_I2C1,
+ CSU_CSLX_USB2,
+ CSU_CSLX_I2C3,
+ CSU_CSLX_I2C2,
+ CSU_CSLX_DUART2 = 50,
+ CSU_CSLX_DUART1,
+ CSU_CSLX_WDT2,
+ CSU_CSLX_WDT1,
+ CSU_CSLX_EDMA,
+ CSU_CSLX_SYS_CNT,
+ CSU_CSLX_DMA_MUX2,
+ CSU_CSLX_DMA_MUX1,
+ CSU_CSLX_DDR,
+ CSU_CSLX_QUICC,
+ CSU_CSLX_DCFG_CCU_RCPM = 60,
+ CSU_CSLX_SECURE_BOOTROM,
+ CSU_CSLX_SFP,
+ CSU_CSLX_TMU,
+ CSU_CSLX_SECURE_MONITOR,
+ CSU_CSLX_RESERVED0,
+ CSU_CSLX_ETSEC1,
+ CSU_CSLX_SEC5_5,
+ CSU_CSLX_ETSEC3,
+ CSU_CSLX_ETSEC2,
+ CSU_CSLX_GPIO2 = 70,
+ CSU_CSLX_GPIO1,
+ CSU_CSLX_GPIO4,
+ CSU_CSLX_GPIO3,
+ CSU_CSLX_PLATFORM_CONT,
+ CSU_CSLX_CSU,
+ CSU_CSLX_ASRC,
+ CSU_CSLX_SPDIF,
+ CSU_CSLX_FLEXCAN2,
+ CSU_CSLX_FLEXCAN1,
+ CSU_CSLX_FLEXCAN4 = 80,
+ CSU_CSLX_FLEXCAN3,
+ CSU_CSLX_SAI2,
+ CSU_CSLX_SAI1,
+ CSU_CSLX_SAI4,
+ CSU_CSLX_SAI3,
+ CSU_CSLX_FTM2,
+ CSU_CSLX_FTM1,
+ CSU_CSLX_FTM4,
+ CSU_CSLX_FTM3,
+ CSU_CSLX_FTM6 = 90,
+ CSU_CSLX_FTM5,
+ CSU_CSLX_FTM8,
+ CSU_CSLX_FTM7,
+ CSU_CSLX_COP_DCSR,
+ CSU_CSLX_EPU,
+ CSU_CSLX_GDI,
+ CSU_CSLX_DDI,
+ CSU_CSLX_RESERVED1,
+ CSU_CSLX_USB3_PHY = 117,
+ CSU_CSLX_RESERVED2,
+ CSU_CSLX_MAX,
+};
+
+struct csu_ns_dev {
+ unsigned long ind;
+ uint32_t val;
+};
+
+void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num);
+
+#endif
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_SPL_H__
+#define __ASM_ARCH_SPL_H__
+
+#define BOOT_DEVICE_NONE 0
+#define BOOT_DEVICE_XIP 1
+#define BOOT_DEVICE_XIPWAIT 2
+#define BOOT_DEVICE_NAND 3
+#define BOOT_DEVICE_ONENAND 4
+#define BOOT_DEVICE_MMC1 5
+#define BOOT_DEVICE_MMC2 6
+#define BOOT_DEVICE_MMC2_2 7
+#define BOOT_DEVICE_SPI 10
+
+#endif /* __ASM_ARCH_SPL_H__ */
MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0),
+
+ MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0),
};
#endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PCIE_LAYERSCAPE_H_
+#define __PCIE_LAYERSCAPE_H_
+
+void pci_init_board(void);
+void ft_pcie_setup(void *blob, bd_t *bd);
+
+#endif
}
#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
- const char *phy_type, int start_offset)
-{
- const char *compat_dr = "fsl-usb2-dr";
- const char *compat_mph = "fsl-usb2-mph";
- const char *prop_mode = "dr_mode";
- const char *prop_type = "phy_type";
- const char *node_type = NULL;
- int node_offset;
- int err;
-
- node_offset = fdt_node_offset_by_compatible(blob,
- start_offset, compat_mph);
- if (node_offset < 0) {
- node_offset = fdt_node_offset_by_compatible(blob,
- start_offset, compat_dr);
- if (node_offset < 0) {
- printf("WARNING: could not find compatible"
- " node %s or %s: %s.\n", compat_mph,
- compat_dr, fdt_strerror(node_offset));
- return -1;
- } else
- node_type = compat_dr;
- } else
- node_type = compat_mph;
-
- if (mode) {
- err = fdt_setprop(blob, node_offset, prop_mode, mode,
- strlen(mode) + 1);
- if (err < 0)
- printf("WARNING: could not set %s for %s: %s.\n",
- prop_mode, node_type, fdt_strerror(err));
- }
-
- if (phy_type) {
- err = fdt_setprop(blob, node_offset, prop_type, phy_type,
- strlen(phy_type) + 1);
- if (err < 0)
- printf("WARNING: could not set %s for %s: %s.\n",
- prop_type, node_type, fdt_strerror(err));
- }
-
- return node_offset;
-}
-
-void fdt_fixup_dr_usb(void *blob, bd_t *bd)
-{
- const char *modes[] = { "host", "peripheral", "otg" };
- const char *phys[] = { "ulpi", "utmi" };
- int usb_mode_off = -1;
- int usb_phy_off = -1;
- char str[5];
- int i, j;
-
- for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
- const char *dr_mode_type = NULL;
- const char *dr_phy_type = NULL;
- int mode_idx = -1, phy_idx = -1;
- snprintf(str, 5, "%s%d", "usb", i);
- if (hwconfig(str)) {
- for (j = 0; j < ARRAY_SIZE(modes); j++) {
- if (hwconfig_subarg_cmp(str, "dr_mode",
- modes[j])) {
- mode_idx = j;
- break;
- }
- }
-
- for (j = 0; j < ARRAY_SIZE(phys); j++) {
- if (hwconfig_subarg_cmp(str, "phy_type",
- phys[j])) {
- phy_idx = j;
- break;
- }
- }
-
- if (mode_idx < 0 && phy_idx < 0) {
- printf("WARNING: invalid phy or mode\n");
- return;
- }
-
- if (mode_idx > -1)
- dr_mode_type = modes[mode_idx];
-
- if (phy_idx > -1)
- dr_phy_type = phys[phy_idx];
- }
-
- usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
- dr_mode_type, NULL, usb_mode_off);
-
- if (usb_mode_off < 0)
- return;
-
- usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
- NULL, dr_phy_type, usb_phy_off);
-
- if (usb_phy_off < 0)
- return;
- }
-}
-#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
-
/*
* update crypto node properties to a specified revision of the SEC
* called with sec_rev == 0 if not on an E processor
obj-$(CONFIG_FSL_DIU_CH7301) += diu_ch7301.o
+ifdef CONFIG_ARM
+obj-$(CONFIG_DEEP_SLEEP) += arm_sleep.o
+else
+obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o
+endif
+
obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o
obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
obj-$(CONFIG_ZM7300) += zm7300.o
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
+obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o
+
# deal with common files for P-series corenet based devices
obj-$(CONFIG_P2041RDB) += p_corenet/
obj-$(CONFIG_P3041DS) += p_corenet/
obj-$(CONFIG_P4080DS) += p_corenet/
obj-$(CONFIG_P5020DS) += p_corenet/
obj-$(CONFIG_P5040DS) += p_corenet/
+
+obj-$(CONFIG_LS102XA_NS_ACCESS) += ns_access.o
endif
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#if !defined(CONFIG_ARMV7_NONSEC) || !defined(CONFIG_ARMV7_VIRT)
+#error " Deep sleep needs non-secure mode support. "
+#else
+#include <asm/secure.h>
+#endif
+#include <asm/armv7.h>
+#include <asm/cache.h>
+
+#if defined(CONFIG_LS102XA)
+#include <asm/arch/immap_ls102xa.h>
+#endif
+
+#include "sleep.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __weak board_mem_sleep_setup(void)
+{
+}
+
+void __weak board_sleep_prepare(void)
+{
+}
+
+bool is_warm_boot(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+ if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
+ return 1;
+
+ return 0;
+}
+
+void fsl_dp_disable_console(void)
+{
+ gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+}
+
+/*
+ * When wakeup from deep sleep, the first 128 bytes space
+ * will be used to do DDR training which corrupts the data
+ * in there. This function will restore them.
+ */
+static void dp_ddr_restore(void)
+{
+ u64 *src, *dst;
+ int i;
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+ /* get the address of ddr date from SPARECR3 */
+ src = (u64 *)in_le32(&scfg->sparecr[2]);
+ dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+
+ for (i = 0; i < DDR_BUFF_LEN / 8; i++)
+ *dst++ = *src++;
+
+ flush_dcache_all();
+}
+
+static void dp_resume_prepare(void)
+{
+ dp_ddr_restore();
+ board_sleep_prepare();
+ armv7_init_nonsec();
+ cleanup_before_linux();
+}
+
+int fsl_dp_resume(void)
+{
+ u32 start_addr;
+ void (*kernel_resume)(void);
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+ if (!is_warm_boot())
+ return 0;
+
+ dp_resume_prepare();
+
+ /* Get the entry address and jump to kernel */
+ start_addr = in_le32(&scfg->sparecr[1]);
+ debug("Entry address is 0x%08x\n", start_addr);
+ kernel_resume = (void (*)(void))start_addr;
+ secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ls102xa_stream_id.h>
+
+void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
+{
+ uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR;
+ int i;
+
+ for (i = 0; i < num; i++)
+ out_be32(scfg + id[i].offset, id[i].stream_id);
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/immap_85xx.h>
+#include "sleep.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __weak board_mem_sleep_setup(void)
+{
+}
+
+void __weak board_sleep_prepare(void)
+{
+}
+
+bool is_warm_boot(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR)
+ return 1;
+
+ return 0;
+}
+
+void fsl_dp_disable_console(void)
+{
+ gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+}
+
+/*
+ * When wakeup from deep sleep, the first 128 bytes space
+ * will be used to do DDR training which corrupts the data
+ * in there. This function will restore them.
+ */
+static void dp_ddr_restore(void)
+{
+ volatile u64 *src, *dst;
+ int i;
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+
+ /* get the address of ddr date from SPARECR3 */
+ src = (u64 *)in_be32(&scfg->sparecr[2]);
+ dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+
+ for (i = 0; i < DDR_BUFF_LEN / 8; i++)
+ *dst++ = *src++;
+
+ flush_dcache();
+}
+
+static void dp_resume_prepare(void)
+{
+ dp_ddr_restore();
+
+ board_sleep_prepare();
+
+ l2cache_init();
+#if defined(CONFIG_RAMBOOT_PBL)
+ disable_cpc_sram();
+#endif
+ enable_cpc();
+}
+
+int fsl_dp_resume(void)
+{
+ u32 start_addr;
+ void (*kernel_resume)(void);
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+
+ if (!is_warm_boot())
+ return 0;
+
+ dp_resume_prepare();
+
+ /* Get the entry address and jump to kernel */
+ start_addr = in_be32(&scfg->sparecr[1]);
+ debug("Entry address is 0x%08x\n", start_addr);
+ kernel_resume = (void (*)(void))start_addr;
+ kernel_resume();
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ns_access.h>
+
+void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
+{
+ u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
+ u32 *reg;
+ uint32_t val;
+ int i;
+
+ for (i = 0; i < num; i++) {
+ reg = base + ns_dev[i].ind / 2;
+ val = in_be32(reg);
+ if (ns_dev[i].ind % 2 == 0) {
+ val &= 0x0000ffff;
+ val |= ns_dev[i].val << 16;
+ } else {
+ val &= 0xffff0000;
+ val |= ns_dev[i].val;
+ }
+ out_be32(reg, val);
+ }
+}
void qixis_write_i2c(unsigned int reg, u8 value);
#endif
+#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR)
+#define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg))
+#define QIXIS_WRITE(reg, value) \
+ qixis_write_i2c(offsetof(struct qixis, reg), value)
+#else
#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
+#endif
+
#ifdef CONFIG_SYS_I2C_FPGA_ADDR
#define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
#define QIXIS_WRITE_I2C(reg, value) \
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SLEEP_H
+#define __SLEEP_H
+
+#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
+#define DDR_BUFF_LEN 128
+
+/* determine if it is a wakeup from deep sleep */
+bool is_warm_boot(void);
+
+/* disable console output */
+void fsl_dp_disable_console(void);
+
+/* clean up everything and jump to kernel */
+int fsl_dp_resume(void);
+#endif
F: configs/ls1021aqds_nor_defconfig
F: configs/ls1021aqds_ddr4_nor_defconfig
F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+F: configs/ls1021aqds_sdcard_defconfig
+F: configs/ls1021aqds_qspi_defconfig
+F: configs/ls1021aqds_nand_defconfig
{
phys_size_t dram_size;
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
puts("Initializing DDR....using SPD\n");
dram_size = fsl_ddr_sdram();
-
+#else
+ dram_size = fsl_ddr_sdram_size();
+#endif
return dram_size;
}
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ns_access.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_stream_id.h>
+#include <asm/pcie_layerscape.h>
+#include <hwconfig.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <fsl_sec.h>
+#include <spl.h>
#include "../common/qixis.h"
#include "ls1021aqds_qixis.h"
#include "../../../drivers/qe/qe.h"
#endif
+#define PIN_MUX_SEL_CAN 0x03
+#define PIN_MUX_SEL_IIC2 0xa0
+#define PIN_MUX_SEL_RGMII 0x00
+#define PIN_MUX_SEL_SAI 0x0c
+#define PIN_MUX_SEL_SDHC 0x00
+
+#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
+#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
DECLARE_GLOBAL_DATA_PTR;
enum {
+ MUX_TYPE_CAN,
+ MUX_TYPE_IIC2,
+ MUX_TYPE_RGMII,
+ MUX_TYPE_SAI,
+ MUX_TYPE_SDHC,
MUX_TYPE_SD_PCI4,
MUX_TYPE_SD_PC_SA_SG_SG,
MUX_TYPE_SD_PC_SA_PC_SG,
int checkboard(void)
{
+#ifndef CONFIG_QSPI_BOOT
char buf[64];
+#endif
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
u8 sw;
+#endif
puts("Board: LS1021AQDS\n");
+#ifdef CONFIG_SD_BOOT
+ puts("SD\n");
+#elif CONFIG_QSPI_BOOT
+ puts("QSPI\n");
+#else
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
printf("IFCCard\n");
else
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
+#ifndef CONFIG_QSPI_BOOT
printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
QIXIS_READ(id), QIXIS_READ(arch));
printf("FPGA: v%d (%s), build %d\n",
(int)QIXIS_READ(scver), qixis_read_tag(buf),
(int)qixis_read_minor());
+#endif
return 0;
}
return 66666666;
}
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
int dram_init(void)
{
+ /*
+ * When resuming from deep sleep, the I2C channel may not be
+ * in the default channel. So, switch to the default channel
+ * before accessing DDR SPD.
+ */
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
gd->ram_size = initdram(0);
return 0;
}
#endif
-int select_i2c_ch_pca9547(u8 ch)
-{
- int ret;
-
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
init_early_memctl_regs();
#endif
+#ifdef CONFIG_FSL_QSPI
+ out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
+
/* Workaround for the issue that DDR could not respond to
* barrier transaction which is generated by executing DSB/ISB
* instruction. Set CCI-400 control override register to
return 0;
}
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+
+#ifdef CONFIG_NAND_BOOT
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 porsr1, pinctl;
+
+ /*
+ * There is LS1 SoC issue where NOR, FPGA are inaccessible during
+ * NAND boot because IFC signals > IFC_AD7 are not enabled.
+ * This workaround changes RCW source to make all signals enabled.
+ */
+ porsr1 = in_be32(&gur->porsr1);
+ pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
+ DCFG_CCSR_PORSR1_RCW_SRC_I2C);
+ out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+ pinctl);
+#endif
+
+ /* Set global data pointer */
+ gd = &gdata;
+
+ /* Clear the BSS */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+#ifdef CONFIG_FSL_IFC
+ init_early_memctl_regs();
+#endif
+
+ get_clocks();
+
+ preloader_console_init();
+
+#ifdef CONFIG_SPL_I2C_SUPPORT
+ i2c_init_all();
+#endif
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+
+ dram_init();
+
+ board_init_r(NULL, 0);
+}
+#endif
+
int config_board_mux(int ctrl_type)
{
- u8 reg12;
+ u8 reg12, reg14;
reg12 = QIXIS_READ(brdcfg[12]);
+ reg14 = QIXIS_READ(brdcfg[14]);
switch (ctrl_type) {
+ case MUX_TYPE_CAN:
+ reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
+ break;
+ case MUX_TYPE_IIC2:
+ reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
+ break;
+ case MUX_TYPE_RGMII:
+ reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
+ break;
+ case MUX_TYPE_SAI:
+ reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
+ break;
+ case MUX_TYPE_SDHC:
+ reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
+ break;
case MUX_TYPE_SD_PCI4:
reg12 = 0x38;
break;
}
QIXIS_WRITE(brdcfg[12], reg12);
+ QIXIS_WRITE(brdcfg[14], reg14);
return 0;
}
return 0;
}
-#if defined(CONFIG_MISC_INIT_R)
int misc_init_r(void)
{
+ int conflict_flag;
+
+ /* some signals can not enable simultaneous*/
+ conflict_flag = 0;
+ if (hwconfig("sdhc"))
+ conflict_flag++;
+ if (hwconfig("iic2"))
+ conflict_flag++;
+ if (conflict_flag > 1) {
+ printf("WARNING: pin conflict !\n");
+ return 0;
+ }
+
+ conflict_flag = 0;
+ if (hwconfig("rgmii"))
+ conflict_flag++;
+ if (hwconfig("can"))
+ conflict_flag++;
+ if (hwconfig("sai"))
+ conflict_flag++;
+ if (conflict_flag > 1) {
+ printf("WARNING: pin conflict !\n");
+ return 0;
+ }
+
+ if (hwconfig("can"))
+ config_board_mux(MUX_TYPE_CAN);
+ else if (hwconfig("rgmii"))
+ config_board_mux(MUX_TYPE_RGMII);
+ else if (hwconfig("sai"))
+ config_board_mux(MUX_TYPE_SAI);
+
+ if (hwconfig("iic2"))
+ config_board_mux(MUX_TYPE_IIC2);
+ else if (hwconfig("sdhc"))
+ config_board_mux(MUX_TYPE_SDHC);
+
#ifdef CONFIG_FSL_CAAM
return sec_init();
#endif
+ return 0;
}
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+static struct csu_ns_dev ns_dev[] = {
+ { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+ { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+ { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM, CSU_ALL_RW },
+ { CSU_CSLX_GIC, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+ { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+ { CSU_CSLX_PCIE2, CSU_ALL_RW },
+ { CSU_CSLX_SATA, CSU_ALL_RW },
+ { CSU_CSLX_USB3, CSU_ALL_RW },
+ { CSU_CSLX_SERDES, CSU_ALL_RW },
+ { CSU_CSLX_QDMA, CSU_ALL_RW },
+ { CSU_CSLX_LPUART2, CSU_ALL_RW },
+ { CSU_CSLX_LPUART1, CSU_ALL_RW },
+ { CSU_CSLX_LPUART4, CSU_ALL_RW },
+ { CSU_CSLX_LPUART3, CSU_ALL_RW },
+ { CSU_CSLX_LPUART6, CSU_ALL_RW },
+ { CSU_CSLX_LPUART5, CSU_ALL_RW },
+ { CSU_CSLX_DSPI2, CSU_ALL_RW },
+ { CSU_CSLX_DSPI1, CSU_ALL_RW },
+ { CSU_CSLX_QSPI, CSU_ALL_RW },
+ { CSU_CSLX_ESDHC, CSU_ALL_RW },
+ { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+ { CSU_CSLX_IFC, CSU_ALL_RW },
+ { CSU_CSLX_I2C1, CSU_ALL_RW },
+ { CSU_CSLX_USB2, CSU_ALL_RW },
+ { CSU_CSLX_I2C3, CSU_ALL_RW },
+ { CSU_CSLX_I2C2, CSU_ALL_RW },
+ { CSU_CSLX_DUART2, CSU_ALL_RW },
+ { CSU_CSLX_DUART1, CSU_ALL_RW },
+ { CSU_CSLX_WDT2, CSU_ALL_RW },
+ { CSU_CSLX_WDT1, CSU_ALL_RW },
+ { CSU_CSLX_EDMA, CSU_ALL_RW },
+ { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+ { CSU_CSLX_DDR, CSU_ALL_RW },
+ { CSU_CSLX_QUICC, CSU_ALL_RW },
+ { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+ { CSU_CSLX_SFP, CSU_ALL_RW },
+ { CSU_CSLX_TMU, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+ { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO1, CSU_ALL_RW },
+ { CSU_CSLX_GPIO4, CSU_ALL_RW },
+ { CSU_CSLX_GPIO3, CSU_ALL_RW },
+ { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+ { CSU_CSLX_CSU, CSU_ALL_RW },
+ { CSU_CSLX_ASRC, CSU_ALL_RW },
+ { CSU_CSLX_SPDIF, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+ { CSU_CSLX_SAI2, CSU_ALL_RW },
+ { CSU_CSLX_SAI1, CSU_ALL_RW },
+ { CSU_CSLX_SAI4, CSU_ALL_RW },
+ { CSU_CSLX_SAI3, CSU_ALL_RW },
+ { CSU_CSLX_FTM2, CSU_ALL_RW },
+ { CSU_CSLX_FTM1, CSU_ALL_RW },
+ { CSU_CSLX_FTM4, CSU_ALL_RW },
+ { CSU_CSLX_FTM3, CSU_ALL_RW },
+ { CSU_CSLX_FTM6, CSU_ALL_RW },
+ { CSU_CSLX_FTM5, CSU_ALL_RW },
+ { CSU_CSLX_FTM8, CSU_ALL_RW },
+ { CSU_CSLX_FTM7, CSU_ALL_RW },
+ { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+ { CSU_CSLX_EPU, CSU_ALL_RW },
+ { CSU_CSLX_GDI, CSU_ALL_RW },
+ { CSU_CSLX_DDI, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED1, CSU_ALL_RW },
+ { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED2, CSU_ALL_RW },
+};
#endif
+struct smmu_stream_id dev_stream_id[] = {
+ { 0x100, 0x01, "ETSEC MAC1" },
+ { 0x104, 0x02, "ETSEC MAC2" },
+ { 0x108, 0x03, "ETSEC MAC3" },
+ { 0x10c, 0x04, "PEX1" },
+ { 0x110, 0x05, "PEX2" },
+ { 0x114, 0x06, "qDMA" },
+ { 0x118, 0x07, "SATA" },
+ { 0x11c, 0x08, "USB3" },
+ { 0x120, 0x09, "QE" },
+ { 0x124, 0x0a, "eSDHC" },
+ { 0x128, 0x0b, "eMA" },
+ { 0x14c, 0x0c, "2D-ACE" },
+ { 0x150, 0x0d, "USB2" },
+ { 0x18c, 0x0e, "DEBUG" },
+};
+
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
config_serdes_mux();
#endif
+ ls102xa_config_smmu_stream_id(dev_stream_id,
+ ARRAY_SIZE(dev_stream_id));
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+ enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
+
#ifdef CONFIG_U_QE
u_qe_init();
#endif
{
ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCIE_LAYERSCAPE
+ ft_pcie_setup(blob, bd);
+#endif
+
return 0;
}
--- /dev/null
+#PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+
+#Configure Scratch register
+09ee0200 10000000
+#Configure alternate space
+09570158 00001000
+#Flush PBL data
+096100c0 000FFFFF
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0608000a 00000000 00000000 00000000
+60000000 00407900 e0106a00 21046000
+00000000 00000000 00000000 00038000
+00000000 001b7200 00000000 00000000
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#enable IFC, disable QSPI and DSPI
+0608000a 00000000 00000000 00000000
+60000000 00407900 60040a00 21046000
+00000000 00000000 00000000 00038000
+00000000 001b7200 00000000 00000000
+
+#disable IFC, enable QSPI and DSPI
+#0608000a 00000000 00000000 00000000
+#60000000 00407900 60040a00 21046000
+#00000000 00000000 00000000 00038000
+#20024800 001b7200 00000000 00000000
F: include/configs/ls1021atwr.h
F: configs/ls1021atwr_nor_defconfig
F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+F: configs/ls1021atwr_sdcard_defconfig
+F: configs/ls1021atwr_qspi_defconfig
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ns_access.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_stream_id.h>
+#include <asm/pcie_layerscape.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <fsl_sec.h>
+#include <spl.h>
#ifdef CONFIG_U_QE
#include "../../../drivers/qe/qe.h"
#endif
u8 rev2; /* Reserved */
};
+#ifndef CONFIG_QSPI_BOOT
static void convert_serdes_mux(int type, int need_reset);
void cpld_show(void)
in_8(&cpld_data->serdes_mux));
#endif
}
+#endif
int checkboard(void)
{
puts("Board: LS1021ATWR\n");
+#ifndef CONFIG_QSPI_BOOT
cpld_show();
+#endif
return 0;
}
}
#endif
+#ifndef CONFIG_QSPI_BOOT
int config_serdes_mux(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
return 0;
}
+#endif
int board_early_init_f(void)
{
out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
#endif
+#ifdef CONFIG_FSL_QSPI
+ out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
+
return 0;
}
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ /* Set global data pointer */
+ gd = &gdata;
+
+ /* Clear the BSS */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ get_clocks();
+
+ preloader_console_init();
+
+ dram_init();
+
+ board_init_r(NULL, 0);
+}
+#endif
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+static struct csu_ns_dev ns_dev[] = {
+ { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+ { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+ { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM, CSU_ALL_RW },
+ { CSU_CSLX_GIC, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+ { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+ { CSU_CSLX_PCIE2, CSU_ALL_RW },
+ { CSU_CSLX_SATA, CSU_ALL_RW },
+ { CSU_CSLX_USB3, CSU_ALL_RW },
+ { CSU_CSLX_SERDES, CSU_ALL_RW },
+ { CSU_CSLX_QDMA, CSU_ALL_RW },
+ { CSU_CSLX_LPUART2, CSU_ALL_RW },
+ { CSU_CSLX_LPUART1, CSU_ALL_RW },
+ { CSU_CSLX_LPUART4, CSU_ALL_RW },
+ { CSU_CSLX_LPUART3, CSU_ALL_RW },
+ { CSU_CSLX_LPUART6, CSU_ALL_RW },
+ { CSU_CSLX_LPUART5, CSU_ALL_RW },
+ { CSU_CSLX_DSPI2, CSU_ALL_RW },
+ { CSU_CSLX_DSPI1, CSU_ALL_RW },
+ { CSU_CSLX_QSPI, CSU_ALL_RW },
+ { CSU_CSLX_ESDHC, CSU_ALL_RW },
+ { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+ { CSU_CSLX_IFC, CSU_ALL_RW },
+ { CSU_CSLX_I2C1, CSU_ALL_RW },
+ { CSU_CSLX_USB2, CSU_ALL_RW },
+ { CSU_CSLX_I2C3, CSU_ALL_RW },
+ { CSU_CSLX_I2C2, CSU_ALL_RW },
+ { CSU_CSLX_DUART2, CSU_ALL_RW },
+ { CSU_CSLX_DUART1, CSU_ALL_RW },
+ { CSU_CSLX_WDT2, CSU_ALL_RW },
+ { CSU_CSLX_WDT1, CSU_ALL_RW },
+ { CSU_CSLX_EDMA, CSU_ALL_RW },
+ { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+ { CSU_CSLX_DDR, CSU_ALL_RW },
+ { CSU_CSLX_QUICC, CSU_ALL_RW },
+ { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+ { CSU_CSLX_SFP, CSU_ALL_RW },
+ { CSU_CSLX_TMU, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+ { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO1, CSU_ALL_RW },
+ { CSU_CSLX_GPIO4, CSU_ALL_RW },
+ { CSU_CSLX_GPIO3, CSU_ALL_RW },
+ { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+ { CSU_CSLX_CSU, CSU_ALL_RW },
+ { CSU_CSLX_ASRC, CSU_ALL_RW },
+ { CSU_CSLX_SPDIF, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+ { CSU_CSLX_SAI2, CSU_ALL_RW },
+ { CSU_CSLX_SAI1, CSU_ALL_RW },
+ { CSU_CSLX_SAI4, CSU_ALL_RW },
+ { CSU_CSLX_SAI3, CSU_ALL_RW },
+ { CSU_CSLX_FTM2, CSU_ALL_RW },
+ { CSU_CSLX_FTM1, CSU_ALL_RW },
+ { CSU_CSLX_FTM4, CSU_ALL_RW },
+ { CSU_CSLX_FTM3, CSU_ALL_RW },
+ { CSU_CSLX_FTM6, CSU_ALL_RW },
+ { CSU_CSLX_FTM5, CSU_ALL_RW },
+ { CSU_CSLX_FTM8, CSU_ALL_RW },
+ { CSU_CSLX_FTM7, CSU_ALL_RW },
+ { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+ { CSU_CSLX_EPU, CSU_ALL_RW },
+ { CSU_CSLX_GDI, CSU_ALL_RW },
+ { CSU_CSLX_DDI, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED1, CSU_ALL_RW },
+ { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED2, CSU_ALL_RW },
+};
+#endif
+
+struct smmu_stream_id dev_stream_id[] = {
+ { 0x100, 0x01, "ETSEC MAC1" },
+ { 0x104, 0x02, "ETSEC MAC2" },
+ { 0x108, 0x03, "ETSEC MAC3" },
+ { 0x10c, 0x04, "PEX1" },
+ { 0x110, 0x05, "PEX2" },
+ { 0x114, 0x06, "qDMA" },
+ { 0x118, 0x07, "SATA" },
+ { 0x11c, 0x08, "USB3" },
+ { 0x120, 0x09, "QE" },
+ { 0x124, 0x0a, "eSDHC" },
+ { 0x128, 0x0b, "eMA" },
+ { 0x14c, 0x0c, "2D-ACE" },
+ { 0x150, 0x0d, "USB2" },
+ { 0x18c, 0x0e, "DEBUG" },
+};
+
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
+#ifndef CONFIG_QSPI_BOOT
config_serdes_mux();
#endif
+#endif
+
+ ls102xa_config_smmu_stream_id(dev_stream_id,
+ ARRAY_SIZE(dev_stream_id));
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+ enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
#ifdef CONFIG_U_QE
u_qe_init();
{
ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCIE_LAYERSCAPE
+ ft_pcie_setup(blob, bd);
+#endif
+
return 0;
}
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
+#ifndef CONFIG_QSPI_BOOT
static void convert_flash_bank(char bank)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
" -change lane C & lane D to PCIeX2\n"
"\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
);
+#endif
--- /dev/null
+#PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+
+#Configure Scratch register
+09ee0200 10000000
+#Configure alternate space
+09570158 00001000
+#Flush PBL data
+096100c0 000FFFFF
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#enable IFC, disable QSPI and DSPI
+0608000a 00000000 00000000 00000000
+20000000 00407900 60040a00 21046000
+00000000 00000000 00000000 00038000
+00080000 881b7340 00000000 00000000
+
+#disable IFC, enable QSPI and DSPI
+#0608000a 00000000 00000000 00000000
+#20000000 00407900 60040a00 21046000
+#00000000 00000000 00000000 00038000
+#20084800 881b7340 00000000 00000000
#include <fsl_esdhc.h>
#include <mmc.h>
#include <netdev.h>
+#include <usb.h>
+#include <usb/ehci-fsl.h>
DECLARE_GLOBAL_DATA_PTR;
}
#endif
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ /* OTG1 */
+ MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* OTG2 */
+ MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ /* Set Power polarity */
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+#endif
int board_early_init_f(void)
{
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
return 0;
}
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
+#include <usb.h>
+#include <usb/ehci-fsl.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ /* OGT1 */
+ MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* OTG2 */
+ MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ /* Set Power polarity */
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+#endif
+
int board_phy_config(struct phy_device *phydev)
{
/*
/* Active high for ncp692 */
gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
return 0;
}
return 0;
}
-
int board_init(void)
{
/* Address of boot parameters */
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021AQDS=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021AQDS=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021AQDS=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021ATWR=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021ATWR=y
ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
- ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
- ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
- ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
-
ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
- ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+#ifdef CONFIG_DEEP_SLEEP
+ if (is_warm_boot()) {
+ ddr_out32(&ddr->sdram_cfg_2,
+ regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
+ ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
+
+ /* DRAM VRef will not be trained */
+ ddr_out32(&ddr->ddr_cdr2,
+ regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
+ } else
+#endif
+ {
+ ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+ ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
+ ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+ ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+ }
ddr_out32(&ddr->err_disable, regs->err_disable);
ddr_out32(&ddr->err_int_en, regs->err_int_en);
for (i = 0; i < 32; i++) {
udelay(500);
asm volatile("dsb sy;isb");
+#ifdef CONFIG_DEEP_SLEEP
+ if (is_warm_boot()) {
+ /* enter self-refresh */
+ temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
+ temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
+ ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+ /* do board specific memory setup */
+ board_mem_sleep_setup();
+
+ temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
+ } else
+#endif
+ temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
/* Let the controller go */
- temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
asm volatile("dsb sy;isb");
if (timeout <= 0)
printf("Waiting for D_INIT timeout. Memory may not work.\n");
+#ifdef CONFIG_DEEP_SLEEP
+ if (is_warm_boot()) {
+ /* exit self-refresh */
+ temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
+ temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
+ ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+ }
+#endif
}
ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
- ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
- ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
- ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
#ifndef CONFIG_SYS_FSL_DDR_EMU
/*
ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
- ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+#ifdef CONFIG_DEEP_SLEEP
+ if (is_warm_boot()) {
+ ddr_out32(&ddr->sdram_cfg_2,
+ regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
+ ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
+
+ /* DRAM VRef will not be trained */
+ ddr_out32(&ddr->ddr_cdr2,
+ regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
+ } else
+#endif
+ {
+ ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+ ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
+ ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+ ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+ }
ddr_out32(&ddr->err_disable, regs->err_disable);
ddr_out32(&ddr->err_int_en, regs->err_int_en);
for (i = 0; i < 32; i++) {
mb();
isb();
+#ifdef CONFIG_DEEP_SLEEP
+ if (is_warm_boot()) {
+ /* enter self-refresh */
+ temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
+ temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
+ ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+ /* do board specific memory setup */
+ board_mem_sleep_setup();
+
+ temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
+ } else
+#endif
+ temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
/* Let the controller go */
- temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
mb();
isb();
if (timeout <= 0)
printf("Waiting for D_INIT timeout. Memory may not work.\n");
+#ifdef CONFIG_DEEP_SLEEP
+ if (is_warm_boot()) {
+ /* exit self-refresh */
+ temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
+ temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
+ ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+ }
+#endif
}
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
#endif
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* regs has the to-be-set values for DDR controller registers
* ctrl_num is the DDR controller number
u32 save1, save2;
#endif
-#ifdef CONFIG_DEEP_SLEEP
- const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- bool sleep_flag = 0;
-#endif
-
-#ifdef CONFIG_DEEP_SLEEP
- if (in_be32(&gur->scrtsr[0]) & (1 << 3))
- sleep_flag = 1;
-#endif
-
switch (ctrl_num) {
case 0:
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
-#ifdef CONFIG_DEEP_SLEEP
- if (sleep_flag)
- out_be32(&ddr->sdram_cfg_2,
- regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
- else
-#endif
- out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
-#ifdef CONFIG_DEEP_SLEEP
- if (sleep_flag) {
- out_be32(&ddr->init_addr, 0);
- out_be32(&ddr->init_ext_addr, (1 << 31));
- } else
-#endif
- {
- out_be32(&ddr->init_addr, regs->ddr_init_addr);
- out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
- }
-
out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
- out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+#ifdef CONFIG_DEEP_SLEEP
+ if (is_warm_boot()) {
+ out_be32(&ddr->sdram_cfg_2,
+ regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
+ out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
+
+ /* DRAM VRef will not be trained */
+ out_be32(&ddr->ddr_cdr2,
+ regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
+ } else
+#endif
+ {
+ out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+ out_be32(&ddr->init_addr, regs->ddr_init_addr);
+ out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+ out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+ }
out_be32(&ddr->err_disable, regs->err_disable);
out_be32(&ddr->err_int_en, regs->err_int_en);
for (i = 0; i < 32; i++) {
asm volatile("sync;isync");
#ifdef CONFIG_DEEP_SLEEP
- if (sleep_flag) {
+ if (is_warm_boot()) {
/* enter self-refresh */
- setbits_be32(&ddr->sdram_cfg_2, (1 << 31));
+ setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
/* do board specific memory setup */
board_mem_sleep_setup();
- }
-#endif
-
- /* Let the controller go */
-#ifdef CONFIG_DEEP_SLEEP
- if (sleep_flag)
temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
- else
+ } else
#endif
temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);
+
+ /* Let the controller go */
out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
asm volatile("sync;isync");
}
#endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
#ifdef CONFIG_DEEP_SLEEP
- if (sleep_flag)
+ if (is_warm_boot())
/* exit self-refresh */
- clrbits_be32(&ddr->sdram_cfg_2, (1 << 31));
+ clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
#endif
}
int dfu_get_alt(char *name)
{
struct dfu_entity *dfu;
+ char *str;
list_for_each_entry(dfu, &dfu_list, list) {
- if (!strncmp(dfu->name, name, strlen(dfu->name)))
- return dfu->alt;
+ if (dfu->name[0] != '/') {
+ if (!strncmp(dfu->name, name, strlen(dfu->name)))
+ return dfu->alt;
+ } else {
+ /*
+ * One must also consider absolute path
+ * (/boot/bin/uImage) available at dfu->name when
+ * compared "plain" file name (uImage)
+ *
+ * It is the case for e.g. thor gadget where lthor SW
+ * sends only the file name, so only the very last part
+ * of path must be checked for equality
+ */
+
+ str = strstr(dfu->name, name);
+ if (!str)
+ continue;
+
+ /*
+ * Check if matching substring is the last element of
+ * dfu->name (uImage)
+ */
+ if (strlen(dfu->name) ==
+ ((str - dfu->name) + strlen(name)))
+ return dfu->alt;
+ }
}
return -ENODEV;
struct fsl_ifc *ifc = ctrl->regs;
u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
u32 time_start;
- u32 eccstat[4];
+ u32 eccstat[4] = {0};
int i;
/* set the chip select for NAND Transaction */
uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
uboot();
}
+
+#ifndef CONFIG_SPL_NAND_INIT
+void nand_init(void)
+{
+}
+
+void nand_deselect(void)
+{
+}
+#endif
obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
obj-$(CONFIG_WINBOND_83C553) += w83c553f.o
+obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Layerscape PCIe driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/pcie_layerscape.h>
+
+#ifdef CONFIG_OF_BOARD_SETUP
+#include <libfdt.h>
+#include <fdt_support.h>
+
+static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
+ unsigned long ctrl_addr, enum srds_prtcl dev)
+{
+ int off;
+
+ off = fdt_node_offset_by_compat_reg(blob, pci_compat,
+ (phys_addr_t)ctrl_addr);
+ if (off < 0)
+ return;
+
+ if (!is_serdes_configured(dev))
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+}
+
+void ft_pcie_setup(void *blob, bd_t *bd)
+{
+ #ifdef CONFIG_PCIE1
+ ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
+ #endif
+
+ #ifdef CONFIG_PCIE2
+ ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
+ #endif
+}
+
+#else
+void ft_pcie_setup(void *blob, bd_t *bd)
+{
+}
+#endif
+
+void pci_init_board(void)
+{
+}
#include <usb/ehci-fsl.h>
#include <hwconfig.h>
#include <fsl_usb.h>
+#include <fdt_support.h>
#include "ehci.h"
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
static void set_txfifothresh(struct usb_ehci *, u32);
/* Check USB PHY clock valid */
cmd |= TXFIFO_THRESH(txfifo_thresh);
ehci_writel(&ehci->txfilltuning, cmd);
}
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
+ const char *phy_type, int start_offset)
+{
+ const char *compat_dr = "fsl-usb2-dr";
+ const char *compat_mph = "fsl-usb2-mph";
+ const char *prop_mode = "dr_mode";
+ const char *prop_type = "phy_type";
+ const char *node_type = NULL;
+ int node_offset;
+ int err;
+
+ node_offset = fdt_node_offset_by_compatible(blob,
+ start_offset, compat_mph);
+ if (node_offset < 0) {
+ node_offset = fdt_node_offset_by_compatible(blob,
+ start_offset,
+ compat_dr);
+ if (node_offset < 0) {
+ printf("WARNING: could not find compatible node: %s",
+ fdt_strerror(node_offset));
+ return -1;
+ }
+ node_type = compat_dr;
+ } else {
+ node_type = compat_mph;
+ }
+
+ if (mode) {
+ err = fdt_setprop(blob, node_offset, prop_mode, mode,
+ strlen(mode) + 1);
+ if (err < 0)
+ printf("WARNING: could not set %s for %s: %s.\n",
+ prop_mode, node_type, fdt_strerror(err));
+ }
+
+ if (phy_type) {
+ err = fdt_setprop(blob, node_offset, prop_type, phy_type,
+ strlen(phy_type) + 1);
+ if (err < 0)
+ printf("WARNING: could not set %s for %s: %s.\n",
+ prop_type, node_type, fdt_strerror(err));
+ }
+
+ return node_offset;
+}
+
+static const char *fdt_usb_get_node_type(void *blob, int start_offset,
+ int *node_offset)
+{
+ const char *compat_dr = "fsl-usb2-dr";
+ const char *compat_mph = "fsl-usb2-mph";
+ const char *node_type = NULL;
+
+ *node_offset = fdt_node_offset_by_compatible(blob, start_offset,
+ compat_mph);
+ if (*node_offset < 0) {
+ *node_offset = fdt_node_offset_by_compatible(blob,
+ start_offset,
+ compat_dr);
+ if (*node_offset < 0) {
+ printf("ERROR: could not find compatible node: %s\n",
+ fdt_strerror(*node_offset));
+ } else {
+ node_type = compat_dr;
+ }
+ } else {
+ node_type = compat_mph;
+ }
+
+ return node_type;
+}
+
+static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum,
+ int start_offset)
+{
+ int node_offset, err;
+ const char *node_type = NULL;
+
+ node_type = fdt_usb_get_node_type(blob, start_offset, &node_offset);
+ if (!node_type)
+ return -1;
+
+ err = fdt_setprop(blob, node_offset, prop_erratum, NULL, 0);
+ if (err < 0) {
+ printf("ERROR: could not set %s for %s: %s.\n",
+ prop_erratum, node_type, fdt_strerror(err));
+ }
+
+ return node_offset;
+}
+
+void fdt_fixup_dr_usb(void *blob, bd_t *bd)
+{
+ static const char * const modes[] = { "host", "peripheral", "otg" };
+ static const char * const phys[] = { "ulpi", "utmi" };
+ int usb_erratum_a006261_off = -1;
+ int usb_erratum_a007075_off = -1;
+ int usb_erratum_a007792_off = -1;
+ int usb_mode_off = -1;
+ int usb_phy_off = -1;
+ char str[5];
+ int i, j;
+
+ for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
+ const char *dr_mode_type = NULL;
+ const char *dr_phy_type = NULL;
+ int mode_idx = -1, phy_idx = -1;
+
+ snprintf(str, 5, "%s%d", "usb", i);
+ if (hwconfig(str)) {
+ for (j = 0; j < ARRAY_SIZE(modes); j++) {
+ if (hwconfig_subarg_cmp(str, "dr_mode",
+ modes[j])) {
+ mode_idx = j;
+ break;
+ }
+ }
+
+ for (j = 0; j < ARRAY_SIZE(phys); j++) {
+ if (hwconfig_subarg_cmp(str, "phy_type",
+ phys[j])) {
+ phy_idx = j;
+ break;
+ }
+ }
+
+ if (mode_idx < 0 && phy_idx < 0) {
+ printf("WARNING: invalid phy or mode\n");
+ return;
+ }
+
+ if (mode_idx > -1)
+ dr_mode_type = modes[mode_idx];
+
+ if (phy_idx > -1)
+ dr_phy_type = phys[phy_idx];
+ }
+
+ usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
+ dr_mode_type, NULL,
+ usb_mode_off);
+
+ if (usb_mode_off < 0)
+ return;
+
+ usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
+ NULL, dr_phy_type,
+ usb_phy_off);
+
+ if (usb_phy_off < 0)
+ return;
+
+ if (has_erratum_a006261()) {
+ usb_erratum_a006261_off = fdt_fixup_usb_erratum
+ (blob,
+ "fsl,usb-erratum-a006261",
+ usb_erratum_a006261_off);
+ if (usb_erratum_a006261_off < 0)
+ return;
+ }
+ if (has_erratum_a007075()) {
+ usb_erratum_a007075_off = fdt_fixup_usb_erratum
+ (blob,
+ "fsl,usb-erratum-a007075",
+ usb_erratum_a007075_off);
+ if (usb_erratum_a007075_off < 0)
+ return;
+ }
+ if (has_erratum_a007792()) {
+ usb_erratum_a007792_off = fdt_fixup_usb_erratum
+ (blob,
+ "fsl,usb-erratum-a007792",
+ usb_erratum_a007792_off);
+ if (usb_erratum_a007792_off < 0)
+ return;
+ }
+ }
+}
+#endif
qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
QH_ENDPT1_EPS(USB_SPEED_HIGH));
- qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
qh_list->qh_overlay.qt_token =
val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
__raw_writel(val, phy_ctrl);
- return val & USBPHY_CTRL_OTG_ID;
+ return 0;
}
/* Base address for this IP block is 0x02184800 */
__raw_writel(val, ctrl);
}
+int usb_phy_mode(int port)
+{
+ void __iomem *phy_reg;
+ void __iomem *phy_ctrl;
+ u32 val;
+
+ phy_reg = (void __iomem *)phy_bases[port];
+ phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+ val = __raw_readl(phy_ctrl);
+
+ if (val & USBPHY_CTRL_OTG_ID)
+ return USB_INIT_DEVICE;
+ else
+ return USB_INIT_HOST;
+}
+
+int __weak board_usb_phy_mode(int port)
+{
+ return usb_phy_mode(port);
+}
+
int __weak board_ehci_hcd_init(int port)
{
return 0;
usb_power_config(index);
usb_oc_config(index);
usb_internal_phy_clock_gate(index, 1);
- type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
+ usb_phy_enable(index, ehci);
+ type = board_usb_phy_mode(index);
*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
unsigned long get_board_ddr_clk(void);
#endif
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 100000000
+#define CONFIG_QIXIS_I2C_ACCESS
+#else
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
+#endif
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
+
+#define CONFIG_SPL_TEXT_BASE 0x10000000
+#define CONFIG_SPL_MAX_SIZE 0x1a000
+#define CONFIG_SPL_STACK 0x1001d000
+#define CONFIG_SPL_PAD_TO 0x1c000
+#define CONFIG_SYS_TEXT_BASE 0x82000000
+
+#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+#define CONFIG_SPL_BSS_START_ADDR 0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_MONITOR_LEN 0x80000
+#endif
+
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_TEXT_BASE 0x40010000
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+
+#define CONFIG_SPL_TEXT_BASE 0x10000000
+#define CONFIG_SPL_MAX_SIZE 0x1a000
+#define CONFIG_SPL_STACK 0x1001d000
+#define CONFIG_SPL_PAD_TO 0x1c000
+#define CONFIG_SYS_TEXT_BASE 0x82000000
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+#define CONFIG_SPL_BSS_START_ADDR 0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_MONITOR_LEN 0x80000
+#endif
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x67f80000
#define CONFIG_FSL_CAAM /* Enable CAAM */
-#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI)
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
+ !defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#endif
/*
* IFC Definitions
*/
+#ifndef CONFIG_QSPI_BOOT
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE 0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#endif
/*
* QIXIS Definitions
#define CONFIG_SYS_FPGA_FTIM3 0x0
#endif
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#endif
/*
* Serial Port
#define CONFIG_FSL_ESDHC
#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* QSPI */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_FSL_QSPI
+#define QSPI0_AMBA_BASE 0x40000000
+#define FSL_QSPI_FLASH_SIZE (1 << 24)
+#define FSL_QSPI_FLASH_NUM 2
+
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#endif
+
/*
* USB
*/
#endif
#endif
+
+/* PCIe */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 /* PCIE controler 2 */
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
+
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING
+
+#ifdef CONFIG_QSPI_BOOT
+#undef CONFIG_CMD_IMLS
+#else
#define CONFIG_CMD_IMLS
+#endif
+
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_LS102XA_NS_ACCESS
+#define CONFIG_SMP_PEN_ADDR 0x01ee0200
+#define CONFIG_TIMER_CLK_FREQ 12500000
+#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
#define CONFIG_SYS_LOAD_ADDR 0x82000000
+#define CONFIG_LS102XA_STREAM_ID
+
/*
* Stack sizes
* The stack sizes are set up in start.S using the settings below
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
/*
* Environment
*/
#define CONFIG_ENV_OVERWRITE
+#if defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET 0x100000
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_NAND_BOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
+
+#define CONFIG_SPL_TEXT_BASE 0x10000000
+#define CONFIG_SPL_MAX_SIZE 0x1a000
+#define CONFIG_SPL_STACK 0x1001d000
+#define CONFIG_SPL_PAD_TO 0x1c000
+#define CONFIG_SYS_TEXT_BASE 0x82000000
+
+#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+#define CONFIG_SPL_BSS_START_ADDR 0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_MONITOR_LEN 0x80000
+#endif
+
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_TEXT_BASE 0x40010000
+#define CONFIG_SYS_NO_FLASH
+#endif
+
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x67f80000
#endif
#define CONFIG_FSL_CAAM /* Enable CAAM */
-#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI)
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
+ !defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#endif
/*
* IFC Definitions
*/
+#ifndef CONFIG_QSPI_BOOT
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE 0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#endif
/* CPLD */
#define CONFIG_FSL_ESDHC
#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* QSPI */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_FSL_QSPI
+#define QSPI0_AMBA_BASE 0x40000000
+#define FSL_QSPI_FLASH_SIZE (1 << 24)
+#define FSL_QSPI_FLASH_NUM 2
+
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#endif
+
/*
* Video
*/
#define CONFIG_HAS_ETH2
#endif
+/* PCIe */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 /* PCIE controler 2 */
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
+
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING
+
+#ifdef CONFIG_QSPI_BOOT
+#undef CONFIG_CMD_IMLS
+#else
#define CONFIG_CMD_IMLS
+#endif
+
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_LS102XA_NS_ACCESS
+#define CONFIG_SMP_PEN_ADDR 0x01ee0200
+#define CONFIG_TIMER_CLK_FREQ 12500000
+#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
#define CONFIG_SYS_LOAD_ADDR 0x82000000
+#define CONFIG_LS102XA_STREAM_ID
+
/*
* Stack sizes
* The stack sizes are set up in start.S using the settings below
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
*/
#define CONFIG_ENV_OVERWRITE
+#if defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET 0x100000
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x20000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET 0x100000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#endif
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
#define CONFIG_SYS_FSL_USDHC_NUM 3
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
+
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
#define CONFIG_CMD_PCI
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI
#define CONFIG_ARMV7_PSCI 1
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
#define CONFIG_SYS_CLK_FREQ 24000000
+#define CONFIG_TIMER_CLK_FREQ CONFIG_SYS_CLK_FREQ
/*
* Include common sunxi configuration where most the settings are
#define SDRAM_CFG_2T_EN 0x00008000
#define SDRAM_CFG_BI 0x00000001
+#define SDRAM_CFG2_FRC_SR 0x80000000
#define SDRAM_CFG2_D_INIT 0x00000010
#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
#define SDRAM_CFG2_ODT_NEVER 0
#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
#define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
+#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
#define DDR_CDR_ODT_120ohm 0x6
#endif
+#define DDR_INIT_ADDR_EXT_UIA (1 << 31)
+
/* Record of register values computed */
typedef struct fsl_ddr_cfg_regs_s {
struct {
int board_need_mem_reset(void)
__attribute__((weak, alias("__board_need_mem_reset")));
-void __weak board_mem_sleep_setup(void)
-{
-}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void);
+bool is_warm_boot(void);
+int fsl_dp_resume(void);
+#endif
/*
* The 85xx boards have a common prototype for fixed_sdram so put the
return SVR_SOC_VER(get_svr()) == SVR_T4240 &&
IS_SVR_REV(get_svr(), 2, 0);
}
+
+static inline bool has_erratum_a007792(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ switch (soc) {
+ case SVR_T4240:
+ case SVR_T4160:
+ return IS_SVR_REV(svr, 2, 0);
+ case SVR_T1040:
+ return IS_SVR_REV(svr, 1, 0);
+ case SVR_T2080:
+ case SVR_T2081:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+ }
+ return false;
+}
+
#else
static inline bool has_erratum_a006261(void)
{
return false;
}
+static inline bool has_erratum_a007792(void)
+{
+ return false;
+}
#endif
#endif /*_ASM_FSL_USB_H_ */
#define MXC_EHCI_IPPUE_DOWN (1 << 10)
#define MXC_EHCI_IPPUE_UP (1 << 11)
+int usb_phy_mode(int port);
/* Board-specific initialization */
int board_ehci_hcd_init(int port);
+int board_usb_phy_mode(int port);
#endif /* _EHCI_FSL_H */
COLOUR_RED="\33[31m"
COLOUR_GREEN="\33[32m"
+COLOUR_ORANGE="\33[33m"
COLOUR_DEFAULT="\33[0m"
DIR=./
fi
cp ./$1 $MNT_DIR
- umount $MNT_DIR
+ while true; do
+ umount $MNT_DIR > /dev/null 2>&1
+ if [ $? -eq 0 ]; then
+ break
+ fi
+ printf "$COLOUR_ORANGE\tSleeping to wait for umount...$COLOUR_DEFAULT\n"
+ sleep 1
+ done
echo -n "TX: "
calculate_md5sum $1
/*
- * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "pblimage.h"
#include "pbl_crc32.h"
+#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
+#define PBL_ACS_CONT_CMD 0x81000000
+#define PBL_ADDR_24BIT_MASK 0x00ffffff
+
/*
* Initialize to an invalid value.
*/
static char *fname = "Unknown";
static int lineno = -1;
static struct pbl_header pblimage_header;
+static int uboot_size;
+static int arch_flag;
+
+static uint32_t pbl_cmd_initaddr;
+static uint32_t pbi_crc_cmd1;
+static uint32_t pbi_crc_cmd2;
+static uint32_t pbl_end_cmd[4];
static union
{
* start offset by subtracting the size of the u-boot image from the
* top of the allowable 24-bit range.
*/
-static void init_next_pbl_cmd(FILE *fp_uboot)
-{
- struct stat st;
- int fd = fileno(fp_uboot);
-
- if (fstat(fd, &st) == -1) {
- printf("Error: Could not determine u-boot image size. %s\n",
- strerror(errno));
- exit(EXIT_FAILURE);
- }
-
- next_pbl_cmd = 0x82000000 - st.st_size;
-}
-
static void generate_pbl_cmd(void)
{
uint32_t val = next_pbl_cmd;
static void pbl_fget(size_t size, FILE *stream)
{
- unsigned char c;
+ unsigned char c = 0xff;
int c_temp;
- while (size && (c_temp = fgetc(stream)) != EOF) {
- c = (unsigned char)c_temp;
+ while (size) {
+ c_temp = fgetc(stream);
+ if (c_temp != EOF)
+ c = (unsigned char)c_temp;
+ else if ((c_temp == EOF) && (arch_flag == IH_ARCH_ARM))
+ c = 0xff;
*pmem_buf++ = c;
pbl_size++;
size--;
/* load split u-boot with PBI command 81xxxxxx. */
static void load_uboot(FILE *fp_uboot)
{
- init_next_pbl_cmd(fp_uboot);
- while (next_pbl_cmd < 0x82000000) {
+ next_pbl_cmd = pbl_cmd_initaddr - uboot_size;
+ while (next_pbl_cmd < pbl_cmd_initaddr) {
generate_pbl_cmd();
pbl_fget(64, fp_uboot);
}
/* write end command and crc command to memory. */
static void add_end_cmd(void)
{
- uint32_t pbl_end_cmd[4] = {0x09138000, 0x00000000,
- 0x091380c0, 0x00000000};
uint32_t crc32_pbl;
int i;
unsigned char *p = (unsigned char *)&pbl_end_cmd;
/* Add PBI CRC command. */
*pmem_buf++ = 0x08;
- *pmem_buf++ = 0x13;
- *pmem_buf++ = 0x80;
+ *pmem_buf++ = pbi_crc_cmd1;
+ *pmem_buf++ = pbi_crc_cmd2;
*pmem_buf++ = 0x40;
pbl_size += 4;
*pmem_buf++ = (crc32_pbl >> 8) & 0xff;
*pmem_buf++ = (crc32_pbl) & 0xff;
pbl_size += 4;
-
- if ((pbl_size % 16) != 0) {
- for (i = 0; i < 8; i++) {
- *pmem_buf++ = 0x0;
- pbl_size++;
- }
- }
- if ((pbl_size % 16 != 0)) {
- printf("Error: Bad size of image file\n");
- exit(EXIT_FAILURE);
- }
}
void pbl_load_uboot(int ifd, struct image_tool_params *params)
/*nothing need to do, pbl_load_uboot takes care of whole file. */
}
+int pblimage_check_params(struct image_tool_params *params)
+{
+ FILE *fp_uboot;
+ int fd;
+ struct stat st;
+
+ if (!params)
+ return EXIT_FAILURE;
+
+ fp_uboot = fopen(params->datafile, "r");
+ if (fp_uboot == NULL) {
+ printf("Error: %s open failed\n", params->datafile);
+ exit(EXIT_FAILURE);
+ }
+ fd = fileno(fp_uboot);
+
+ if (fstat(fd, &st) == -1) {
+ printf("Error: Could not determine u-boot image size. %s\n",
+ strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ /* For the variable size, we need to pad it to 64 byte boundary */
+ uboot_size = roundup(st.st_size, 64);
+
+ if (params->arch == IH_ARCH_ARM) {
+ arch_flag = IH_ARCH_ARM;
+ pbi_crc_cmd1 = 0x61;
+ pbi_crc_cmd2 = 0;
+ pbl_cmd_initaddr = params->addr & PBL_ADDR_24BIT_MASK;
+ pbl_cmd_initaddr |= PBL_ACS_CONT_CMD;
+ pbl_cmd_initaddr |= uboot_size;
+ pbl_end_cmd[0] = 0x09610000;
+ pbl_end_cmd[1] = 0x00000000;
+ pbl_end_cmd[2] = 0x096100c0;
+ pbl_end_cmd[3] = 0x00000000;
+ } else if (params->arch == IH_ARCH_PPC) {
+ arch_flag = IH_ARCH_PPC;
+ pbi_crc_cmd1 = 0x13;
+ pbi_crc_cmd2 = 0x80;
+ pbl_cmd_initaddr = 0x82000000;
+ pbl_end_cmd[0] = 0x09138000;
+ pbl_end_cmd[1] = 0x00000000;
+ pbl_end_cmd[2] = 0x091380c0;
+ pbl_end_cmd[3] = 0x00000000;
+ }
+
+ next_pbl_cmd = pbl_cmd_initaddr;
+ return 0;
+};
+
/* pblimage parameters */
static struct image_type_params pblimage_params = {
.name = "Freescale PBL Boot Image support",
.header_size = sizeof(struct pbl_header),
.hdr = (void *)&pblimage_header,
.check_image_type = pblimage_check_image_types,
+ .check_params = pblimage_check_params,
.verify_header = pblimage_verify_header,
.print_header = pblimage_print_header,
.set_header = pblimage_set_header,
projects / oweals / u-boot.git / commitdiff