muas3001: added 64MB SDRAM autodetection.

Signed-off-by: Heiko Schocher <hs@denx.de>

diff --git a/board/muas3001/muas3001.c b/board/muas3001/muas3001.c
index 49aed037c2f76fa42375db1f3b02ffdcdbfde4c3..0ec451fbd5515a2827dd7cc00582b164e8446711 100644 (file)
--- a/board/muas3001/muas3001.c
+++ b/board/muas3001/muas3001.c
@@ -253,8 +253,10 @@ phys_size_t initdram (int board_type)
 {
        volatile immap_t *immap = (immap_t *) CFG_IMMR;
        volatile memctl8260_t *memctl = &immap->im_memctl;
-
        long psize;
+#ifndef CFG_RAMBOOT
+       long sizelittle, sizebig;
+#endif
 
        memctl->memc_psrt = CFG_PSRT;
        memctl->memc_mptpr = CFG_MPTPR;
@@ -262,8 +264,16 @@ phys_size_t initdram (int board_type)
 #ifndef CFG_RAMBOOT
        /* 60x SDRAM setup:
         */
-       psize = try_init (memctl, CFG_PSDMR, CFG_OR1,
+       sizelittle = try_init (memctl, CFG_PSDMR_LITTLE, CFG_OR1_LITTLE,
+                                                 (uchar *) CFG_SDRAM_BASE);
+       sizebig = try_init (memctl, CFG_PSDMR_BIG, CFG_OR1_BIG,
                                                  (uchar *) CFG_SDRAM_BASE);
+       if (sizelittle < sizebig) {
+               psize = sizebig;
+       } else {
+               psize = try_init (memctl, CFG_PSDMR_LITTLE, CFG_OR1_LITTLE,
+                                                 (uchar *) CFG_SDRAM_BASE);
+       }
 #endif /* CFG_RAMBOOT */
 
        icache_enable ();

diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h
index 77e115877057d30c4d357143fa7889cf6e5f3896..5d157b6c1e05aa1071a4451f9e46cfcd887033dc 100644 (file)
--- a/include/configs/muas3001.h
+++ b/include/configs/muas3001.h
@@ -331,8 +331,7 @@
 
 /* Bank 1 - 60x bus SDRAM
  */
-#define SDRAM_MAX_SIZE 0x08000000      /* max. 128 MB          */
-#define CFG_GLOBAL_SDRAM_LIMIT (128 << 20)     /* less than 128 MB */
+#define CFG_GLOBAL_SDRAM_LIMIT (256 << 20)     /* less than 256 MB */
 
 #define CFG_MPTPR       0x2800
 
@@ -348,16 +347,23 @@
                         BRx_MS_SDRAM_P                 |\
                         BRx_V)
 
-#define CFG_OR1_PRELIM CFG_OR1
+#define CFG_OR1_PRELIM CFG_OR1_LITTLE
 
 /* SDRAM initialization values
 */
-#define CFG_OR1    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+#define CFG_OR1_LITTLE ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
                         ORxS_BPD_4                     |\
                         ORxS_ROWST_PBI1_A7             |\
                         ORxS_NUMR_12)
 
-#define CFG_PSDMR      0x004b36a3
+#define CFG_PSDMR_LITTLE       0x004b36a3
+
+#define CFG_OR1_BIG    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+                        ORxS_BPD_4                     |\
+                        ORxS_ROWST_PBI1_A4             |\
+                        ORxS_NUMR_12)
+
+#define CFG_PSDMR_BIG          0x014f36a3
 
 /* IO on CS4 initialization values
 */