mmc: omap_hsmmc: Reduce the max timeout for reset controller fsm

>From OMAP3 SoCs (OMAP3, OMAP4, OMAP5, AM572x, AM571x), the DAT/CMD lines
reset procedure section in TRM suggests to first poll the SRD/SRC bit
until it is set to 0x1. But looks like that bit is never set to 1 and there
is an observable delay of 1sec everytime the driver tries to reset DAT/CMD.
(The same is observed in linux kernel).

Reduce the time the driver waits for the controller to set the SRC/SRD bits
to 1 so that there is no observable delay.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 55232103e08af8946e110ea539fabfef310abc85..ab4a0952333f438b53d607dca97e5c7809529037 100644 (file)
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -108,6 +108,7 @@ struct omap_hsmmc_adma_desc {
 
 /* If we fail after 1 second wait, something is really bad */
 #define MAX_RETRY_MS   1000
+#define MMC_TIMEOUT_MS 20
 
 /* DMA transfers can take a long time if a lot a data is transferred.
  * The timeout must take in account the amount of data. Let's assume
@@ -598,7 +599,7 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
        if (!(readl(&mmc_base->sysctl) & bit)) {
                start = get_timer(0);
                while (!(readl(&mmc_base->sysctl) & bit)) {
-                       if (get_timer(0) - start > MAX_RETRY_MS)
+                       if (get_timer(0) - start > MMC_TIMEOUT_MS)
                                return;
                }
        }