85xx: Add CPU 2 errata workaround to all 8548 boards

All mpc8548-based boards should implement the suggested workaround
to CPU 2 errata. Without the workaround, its possible for the
8548's core to hang while executing a msync or mbar 0 instruction
and a snoopable transaction from an I/O master tagged to make
quick forward progress is present.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>

diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 86986057c274febd63d32754ee809c44887de6b2..ba6bff585c16c4ded11388da42406ec0e150af3f 100644 (file)
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -52,7 +52,6 @@ int checkboard (void)
        uint pci_slot = get_pci_slot ();
 
        uint cpu_board_rev = get_cpu_board_revision ();
-       uint svr;
 
        printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
                get_board_version (), pci_slot);
@@ -65,17 +64,6 @@ int checkboard (void)
         */
        local_bus_init ();
 
-       svr = get_svr();
-
-       /*
-        * Fix CPU2 errata: A core hang possible while executing a
-        * msync instruction and a snoopable transaction from an I/O
-        * master tagged to make quick forward progress is present.
-        * Fixed in Silicon Rev.2.1
-        */
-       if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
-               ecm->eebpcr |= (1 << 16);
-
        /*
         * Hack TSEC 3 and 4 IO voltages.
         */

diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index cfb9ce5144f4dc87d0905a5fb239ca48b511817e..017f6b35cf690d114fc4b72161ee86576a72a396 100644 (file)
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -61,13 +61,6 @@ int checkboard (void)
         */
        local_bus_init ();
 
-       /*
-        * Fix CPU2 errata: A core hang possible while executing a
-        * msync instruction and a snoopable transaction from an I/O
-        * master tagged to make quick forward progress is present.
-        */
-       ecm->eebpcr |= (1 << 16);
-
        /*
         * Hack TSEC 3 and 4 IO voltages.
         */

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 3a8aef20d31516d69f66fd60c4f9c0d1cd9b1c0f..5862bd6ab0732661ddfd9a14aea33c8ba1e024ba 100644 (file)
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -174,6 +174,19 @@ void cpu_init_f (void)
 {
        volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
        extern void m8560_cpm_reset (void);
+#ifdef CONFIG_MPC8548
+       ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+       uint svr = get_svr();
+
+       /*
+        * CPU2 errata workaround: A core hang possible while executing
+        * a msync instruction and a snoopable transaction from an I/O
+        * master tagged to make quick forward progress is present.
+        * Fixed in silicon rev 2.1.
+        */
+       if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
+               out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
+#endif
 
        disable_tlb(14);
        disable_tlb(15);