arm: mvebu: Fix SAR1_CPU_CORE_MASK

SAR1_CPU_CORE_MASK was wrong, probably copy/paste
from another architecture.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h b/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h
index 7500a72403d8b3ef49633cab67a075608ee7a2c4..06d0ab10aa2a8d228c0690e5d12fb8c9cff29df1 100644 (file)
--- a/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h
+++ b/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h
@@ -23,8 +23,8 @@
 
 #define CPU_CONFIGURATION_REG(id)      (0x21800 + (id * 0x100))
 #define CPU_MRVL_ID_OFFSET             0x10
-#define SAR1_CPU_CORE_MASK             0x00000018
-#define SAR1_CPU_CORE_OFFSET           3
+#define SAR1_CPU_CORE_MASK             0x38000000
+#define SAR1_CPU_CORE_OFFSET           27
 
 #define NEW_FABRIC_TWSI_ADDR           0x4e
 #ifdef DB_784MP_GP
@@ -461,7 +461,4 @@
 #define CLK_CPU_2200                   13
 #define CLK_CPU_2400                   14
 
-#define SAR1_CPU_CORE_MASK             0x00000018
-#define SAR1_CPU_CORE_OFFSET           3
-
 #endif /* _DDR3_HWS_HW_TRAINING_DEF_H */