kmp204x: set CPU watchdog reset reason flag

Check the core timer status register (TSR) for watchdog reset,
and and set the QRIO's reset reason flag REASON1[0] accordingly.

This allows the appliction SW to identify the cpu watchdog as a
reset reason, by setting the REASON1[0] flag in the QRIO.

Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
index 6bc8eb85eaa9a9c58ec6da57c054c137c0464e9c..225262e49c8176fd2c297b7e3fb916f23e107446 100644 (file)
--- a/board/keymile/kmp204x/kmp204x.c
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -80,14 +80,26 @@ int get_scl(void)
 
 #define ZL30158_RST    8
 #define BFTIC4_RST     0
+#define RSTRQSR1_WDT_RR        0x00200000
+#define RSTRQSR1_SW_RR 0x00100000
 
 int board_early_init_f(void)
 {
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       bool cpuwd_flag = false;
 
        /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
        setbits_be32(&gur->ddrclkdr, 0x001f000f);
 
+       /* set reset reason according CPU register */
+       if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
+           RSTRQSR1_WDT_RR)
+               cpuwd_flag = true;
+
+       qrio_cpuwd_flag(cpuwd_flag);
+       /* clear CPU bits by writing 1 */
+       setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
+
        /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
        qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
        /* and enable WD on it */