ppc4xx: Allow DTT_I2C_DEV_CODE configured by CFG_I2C_DTT_ADDR
authorVictor Gallardo <vgallardo@amcc.com>
Tue, 9 Sep 2008 22:13:29 +0000 (15:13 -0700)
committerWolfgang Denk <wd@denx.de>
Wed, 10 Sep 2008 09:08:45 +0000 (11:08 +0200)
On AMCC Arches board DTT_I2C_DEV_CODE is different then canyonlands
and glacier.

Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
README
drivers/hwmon/lm75.c

diff --git a/README b/README
index b5e40862b9940da24b1474595a532fe6c6e43095..44b450c6e2379f43c2fc5b5b51eba146e7e868b7 100644 (file)
--- a/README
+++ b/README
@@ -1392,6 +1392,12 @@ The following options need to be configured:
                If defined, then this indicates the I2C bus number for the DTT.
                If not defined, then U-Boot assumes that DTT is on I2C bus 0.
 
+               CFG_I2C_DTT_ADDR:
+
+               If defined, specifies the I2C address of the DTT device.
+               If not defined, then U-Boot uses predefined value for
+               specified DTT device.
+
                CONFIG_FSL_I2C
 
                Define this option if you want to use Freescale's I2C driver in
index 8051cb228c09d6cc410f13d4315ee66a42783e8a..67a18f68d62b88141daf7036ce507d07a1bb17cb 100644 (file)
 /*
  * Device code
  */
+#if defined(CFG_I2C_DTT_ADDR)
+#define DTT_I2C_DEV_CODE CFG_I2C_DTT_ADDR
+#else
 #define DTT_I2C_DEV_CODE 0x48                  /* ON Semi's LM75 device */
+#endif
 #define DTT_READ_TEMP          0x0
 #define DTT_CONFIG             0x1
 #define DTT_TEMP_HYST          0x2