fix build breakage from ppc asm constraints change

due to a mistake in my testing procedure, the changes in the previous
commit were not correctly tested and wrongly assumed to be valid. the
lwarx and stwcx. instructions do not accept general ppc memory address
expressions and thus the argument associated with the memory
constraint cannot be used directly.

instead, the memory constraint can be left as an argument that the asm
does not actually use, and the address can be provided in a separate
register constraint.

(cherry picked from commit bb3a3befeaa01531c273ef9130f3fbcaaf8a25e2)

diff --git a/arch/powerpc/atomic.h b/arch/powerpc/atomic.h
index 05951a2de7055f2695fe34c638e071fd89a0072b..a1049bdb391af733b591417af39173283dc9a60f 100644 (file)
--- a/arch/powerpc/atomic.h
+++ b/arch/powerpc/atomic.h
@@ -25,13 +25,13 @@ static inline int a_ctz_64(uint64_t x)
 
 static inline int a_cas(volatile int *p, int t, int s)
 {
-       __asm__("1:     lwarx %0, 0, %1\n"
+       __asm__("1:     lwarx %0, 0, %4\n"
                "       cmpw %0, %2\n"
                "       bne 1f\n"
-               "       stwcx. %3, 0, %1\n"
+               "       stwcx. %3, 0, %4\n"
                "       bne- 1b\n"
                "1:     \n"
-               : "=&r"(t), "+m"(*p) : "r"(t), "r"(s) : "cc", "memory" );
+               : "=&r"(t), "+m"(*p) : "r"(t), "r"(s), "r"(p) : "cc", "memory" );
         return t;
 }