- Move blackfin serial driver to the generic driver folder.
- Move blackfin serial headers to blackfin arch head folder.
- Update the include path to blackfin serial header in start up code.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
COBJS-$(CONFIG_JTAG_CONSOLE) += jtag-console.o
COBJS-y += os_log.o
COBJS-y += reset.o
-COBJS-y += serial.o
COBJS-y += traps.o
SRCS := $(SEXTRA:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
#include <asm/mach-common/bits/core.h>
#include <asm/mach-common/bits/ebiu.h>
#include <asm/mach-common/bits/trace.h>
+#include <asm/serial.h>
#include "cpu.h"
-#include "serial.h"
#include "initcode.h"
ulong bfin_poweron_retx;
#include <asm/mach-common/bits/watchdog.h>
#include <asm/mach-common/bits/bootrom.h>
#include <asm/mach-common/bits/core.h>
+#include <asm/serial.h>
-#define BUG() while (1) { asm volatile("emuexcpt;"); }
-
-#include "serial.h"
+#define BUG() while (1) asm volatile("emuexcpt;");
#ifndef __ADSPBF60x__
#include <asm/mach-common/bits/ebiu.h>
+++ /dev/null
-/*
- * U-boot - serial.c Blackfin Serial Driver
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
- * BuyWays B.V. (www.buyways.nl)
- *
- * Based heavily on:
- * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
- * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
- * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
- * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
- *
- * Based on code from 68328 version serial driver imlpementation which was:
- * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
- * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
- * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-/* Anomaly notes:
- * 05000086 - we don't support autobaud
- * 05000099 - we only use DR bit, so losing others is not a problem
- * 05000100 - we don't use the UART_IIR register
- * 05000215 - we poll the uart (no dma/interrupts)
- * 05000225 - no workaround possible, but this shouldnt cause errors ...
- * 05000230 - we tweak the baud rate calculation slightly
- * 05000231 - we always use 1 stop bit
- * 05000309 - we always enable the uart before we modify it in anyway
- * 05000350 - we always enable the uart regardless of boot mode
- * 05000363 - we don't support break signals, so don't generate one
- */
-
-#include <common.h>
-#include <post.h>
-#include <watchdog.h>
-#include <serial.h>
-#include <linux/compiler.h>
-#include <asm/blackfin.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_UART_CONSOLE
-
-#include "serial.h"
-
-#ifdef CONFIG_DEBUG_SERIAL
-static uart_lsr_t cached_lsr[256];
-static uart_lsr_t cached_rbr[256];
-static size_t cache_count;
-
-/* The LSR is read-to-clear on some parts, so we have to make sure status
- * bits aren't inadvertently lost when doing various tests. This also
- * works around anomaly 05000099 at the same time by keeping a cumulative
- * tally of all the status bits.
- */
-static uart_lsr_t uart_lsr_save;
-static uart_lsr_t uart_lsr_read(uint32_t uart_base)
-{
- uart_lsr_t lsr = _lsr_read(pUART);
- uart_lsr_save |= (lsr & (OE|PE|FE|BI));
- return lsr | uart_lsr_save;
-}
-/* Just do the clear for everyone since it can't hurt. */
-static void uart_lsr_clear(uint32_t uart_base)
-{
- uart_lsr_save = 0;
- _lsr_write(pUART, -1);
-}
-#else
-/* When debugging is disabled, we only care about the DR bit, so if other
- * bits get set/cleared, we don't really care since we don't read them
- * anyways (and thus anomaly 05000099 is irrelevant).
- */
-static inline uart_lsr_t uart_lsr_read(uint32_t uart_base)
-{
- return _lsr_read(pUART);
-}
-static void uart_lsr_clear(uint32_t uart_base)
-{
- _lsr_write(pUART, -1);
-}
-#endif
-
-static void uart_putc(uint32_t uart_base, const char c)
-{
- /* send a \r for compatibility */
- if (c == '\n')
- serial_putc('\r');
-
- WATCHDOG_RESET();
-
- /* wait for the hardware fifo to clear up */
- while (!(uart_lsr_read(uart_base) & THRE))
- continue;
-
- /* queue the character for transmission */
- bfin_write(&pUART->thr, c);
- SSYNC();
-
- WATCHDOG_RESET();
-}
-
-static int uart_tstc(uint32_t uart_base)
-{
- WATCHDOG_RESET();
- return (uart_lsr_read(uart_base) & DR) ? 1 : 0;
-}
-
-static int uart_getc(uint32_t uart_base)
-{
- uint16_t uart_rbr_val;
-
- /* wait for data ! */
- while (!uart_tstc(uart_base))
- continue;
-
- /* grab the new byte */
- uart_rbr_val = bfin_read(&pUART->rbr);
-
-#ifdef CONFIG_DEBUG_SERIAL
- /* grab & clear the LSR */
- uart_lsr_t uart_lsr_val = uart_lsr_read(uart_base);
-
- cached_lsr[cache_count] = uart_lsr_val;
- cached_rbr[cache_count] = uart_rbr_val;
- cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr);
-
- if (uart_lsr_val & (OE|PE|FE|BI)) {
- printf("\n[SERIAL ERROR]\n");
- do {
- --cache_count;
- printf("\t%3zu: RBR=0x%02x LSR=0x%02x\n", cache_count,
- cached_rbr[cache_count], cached_lsr[cache_count]);
- } while (cache_count > 0);
- return -1;
- }
-#endif
- uart_lsr_clear(uart_base);
-
- return uart_rbr_val;
-}
-
-#if CONFIG_POST & CONFIG_SYS_POST_UART
-# define LOOP(x) x
-#else
-# define LOOP(x)
-#endif
-
-#if BFIN_UART_HW_VER < 4
-
-LOOP(
-static void uart_loop(uint32_t uart_base, int state)
-{
- u16 mcr;
-
- /* Drain the TX fifo first so bytes don't come back */
- while (!(uart_lsr_read(uart_base) & TEMT))
- continue;
-
- mcr = bfin_read(&pUART->mcr);
- if (state)
- mcr |= LOOP_ENA | MRTS;
- else
- mcr &= ~(LOOP_ENA | MRTS);
- bfin_write(&pUART->mcr, mcr);
-}
-)
-
-#else
-
-LOOP(
-static void uart_loop(uint32_t uart_base, int state)
-{
- u32 control;
-
- /* Drain the TX fifo first so bytes don't come back */
- while (!(uart_lsr_read(uart_base) & TEMT))
- continue;
-
- control = bfin_read(&pUART->control);
- if (state)
- control |= LOOP_ENA | MRTS;
- else
- control &= ~(LOOP_ENA | MRTS);
- bfin_write(&pUART->control, control);
-}
-)
-
-#endif
-
-static inline void __serial_set_baud(uint32_t uart_base, uint32_t baud)
-{
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
- serial_early_set_baud(uart_base, baud);
-#else
- uint16_t divisor = (get_uart_clk() + (baud * 8)) / (baud * 16)
- - ANOMALY_05000230;
-
- /* Program the divisor to get the baud rate we want */
- serial_set_divisor(uart_base, divisor);
-#endif
-}
-
-static void uart_puts(uint32_t uart_base, const char *s)
-{
- while (*s)
- uart_putc(uart_base, *s++);
-}
-
-#define DECL_BFIN_UART(n) \
-static int uart##n##_init(void) \
-{ \
- const unsigned short pins[] = { _P_UART(n, RX), _P_UART(n, TX), 0, }; \
- peripheral_request_list(pins, "bfin-uart"); \
- uart_init(MMR_UART(n)); \
- __serial_set_baud(MMR_UART(n), gd->baudrate); \
- uart_lsr_clear(MMR_UART(n)); \
- return 0; \
-} \
-\
-static int uart##n##_uninit(void) \
-{ \
- return serial_early_uninit(MMR_UART(n)); \
-} \
-\
-static void uart##n##_setbrg(void) \
-{ \
- __serial_set_baud(MMR_UART(n), gd->baudrate); \
-} \
-\
-static int uart##n##_getc(void) \
-{ \
- return uart_getc(MMR_UART(n)); \
-} \
-\
-static int uart##n##_tstc(void) \
-{ \
- return uart_tstc(MMR_UART(n)); \
-} \
-\
-static void uart##n##_putc(const char c) \
-{ \
- uart_putc(MMR_UART(n), c); \
-} \
-\
-static void uart##n##_puts(const char *s) \
-{ \
- uart_puts(MMR_UART(n), s); \
-} \
-\
-LOOP( \
-static void uart##n##_loop(int state) \
-{ \
- uart_loop(MMR_UART(n), state); \
-} \
-) \
-\
-struct serial_device bfin_serial##n##_device = { \
- .name = "bfin_uart"#n, \
- .start = uart##n##_init, \
- .stop = uart##n##_uninit, \
- .setbrg = uart##n##_setbrg, \
- .getc = uart##n##_getc, \
- .tstc = uart##n##_tstc, \
- .putc = uart##n##_putc, \
- .puts = uart##n##_puts, \
- LOOP(.loop = uart##n##_loop) \
-};
-
-#ifdef UART0_RBR
-DECL_BFIN_UART(0)
-#endif
-#ifdef UART1_RBR
-DECL_BFIN_UART(1)
-#endif
-#ifdef UART2_RBR
-DECL_BFIN_UART(2)
-#endif
-#ifdef UART3_RBR
-DECL_BFIN_UART(3)
-#endif
-
-__weak struct serial_device *default_serial_console(void)
-{
-#if CONFIG_UART_CONSOLE == 0
- return &bfin_serial0_device;
-#elif CONFIG_UART_CONSOLE == 1
- return &bfin_serial1_device;
-#elif CONFIG_UART_CONSOLE == 2
- return &bfin_serial2_device;
-#elif CONFIG_UART_CONSOLE == 3
- return &bfin_serial3_device;
-#endif
-}
-
-void bfin_serial_initialize(void)
-{
-#ifdef UART0_RBR
- serial_register(&bfin_serial0_device);
-#endif
-#ifdef UART1_RBR
- serial_register(&bfin_serial1_device);
-#endif
-#ifdef UART2_RBR
- serial_register(&bfin_serial2_device);
-#endif
-#ifdef UART3_RBR
- serial_register(&bfin_serial3_device);
-#endif
-}
-
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
-inline void uart_early_putc(uint32_t uart_base, const char c)
-{
- /* send a \r for compatibility */
- if (c == '\n')
- uart_early_putc(uart_base, '\r');
-
- /* wait for the hardware fifo to clear up */
- while (!(_lsr_read(pUART) & THRE))
- continue;
-
- /* queue the character for transmission */
- bfin_write(&pUART->thr, c);
- SSYNC();
-}
-
-void uart_early_puts(const char *s)
-{
- while (*s)
- uart_early_putc(UART_BASE, *s++);
-}
-
-/* Symbol for our assembly to call. */
-void _serial_early_set_baud(uint32_t baud)
-{
- serial_early_set_baud(UART_BASE, baud);
-}
-
-/* Symbol for our assembly to call. */
-void _serial_early_init(void)
-{
- serial_early_init(UART_BASE);
-}
-#endif
-
-#elif defined(CONFIG_UART_MEM)
-
-char serial_logbuf[CONFIG_UART_MEM];
-char *serial_logbuf_head = serial_logbuf;
-
-int serial_mem_init(void)
-{
- serial_logbuf_head = serial_logbuf;
- return 0;
-}
-
-void serial_mem_setbrg(void)
-{
-}
-
-int serial_mem_tstc(void)
-{
- return 0;
-}
-
-int serial_mem_getc(void)
-{
- return 0;
-}
-
-void serial_mem_putc(const char c)
-{
- *serial_logbuf_head = c;
- if (++serial_logbuf_head == serial_logbuf + CONFIG_UART_MEM)
- serial_logbuf_head = serial_logbuf;
-}
-
-void serial_mem_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
-struct serial_device bfin_serial_mem_device = {
- .name = "bfin_uart_mem",
- .start = serial_mem_init,
- .setbrg = serial_mem_setbrg,
- .getc = serial_mem_getc,
- .tstc = serial_mem_tstc,
- .putc = serial_mem_putc,
- .puts = serial_mem_puts,
-};
-
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &bfin_serial_mem_device;
-}
-
-void bfin_serial_initialize(void)
-{
- serial_register(&bfin_serial_mem_device);
-}
-#endif /* CONFIG_UART_MEM */
+++ /dev/null
-/*
- * serial.h - common serial defines for early debug and serial driver.
- * any functions defined here must be always_inline since
- * initcode cannot have function calls.
- *
- * Copyright (c) 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_CPU_SERIAL_H__
-#define __BFIN_CPU_SERIAL_H__
-
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-
-#ifndef CONFIG_UART_CONSOLE
-# define CONFIG_UART_CONSOLE 0
-#endif
-
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
-# define BFIN_DEBUG_EARLY_SERIAL 1
-#else
-# define BFIN_DEBUG_EARLY_SERIAL 0
-#endif
-
-#if defined(__ADSPBF60x__)
-# define BFIN_UART_HW_VER 4
-#elif defined(__ADSPBF50x__) || defined(__ADSPBF54x__)
-# define BFIN_UART_HW_VER 2
-#else
-# define BFIN_UART_HW_VER 1
-#endif
-
-#define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx
-#define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx)
-#define _P_UART(n, pin) _PASTE_UART(n, P_UART, pin)
-#define P_UART(pin) _P_UART(CONFIG_UART_CONSOLE, pin)
-
-#define pUART ((volatile struct bfin_mmr_serial *)uart_base)
-
-#ifndef __ASSEMBLY__
-__attribute__((always_inline))
-static inline void serial_do_portmux(void);
-#endif
-
-#if BFIN_UART_HW_VER < 4
-# include "serial1.h"
-#else
-# include "serial4.h"
-#endif
-
-#ifndef __ASSEMBLY__
-
-__attribute__((always_inline))
-static inline void serial_do_portmux(void)
-{
- if (!BFIN_DEBUG_EARLY_SERIAL) {
- const unsigned short pins[] = { P_UART(RX), P_UART(TX), 0, };
- peripheral_request_list(pins, "bfin-uart");
- return;
- }
-
- serial_early_do_portmux();
-}
-
-#ifndef BFIN_IN_INITCODE
-__attribute__((always_inline))
-static inline void serial_early_puts(const char *s)
-{
- if (BFIN_DEBUG_EARLY_SERIAL) {
- serial_puts("Early: ");
- serial_puts(s);
- }
-}
-#endif
-
-#else
-
-.macro serial_early_init
-#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM)
- call __serial_early_init;
-#endif
-.endm
-
-.macro serial_early_set_baud
-#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM)
- R0.L = LO(CONFIG_BAUDRATE);
- R0.H = HI(CONFIG_BAUDRATE);
- call __serial_early_set_baud;
-#endif
-.endm
-
-#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
-#define update_serial_early_string_addr \
- R1.L = _start; \
- R1.H = _start; \
- R0 = R0 - R1; \
- R1.L = 0; \
- R1.H = 0x2000; \
- R0 = R0 + R1;
-#else
-#define update_serial_early_string_addr
-#endif
-
-/* Since we embed the string right into our .text section, we need
- * to find its address. We do this by getting our PC and adding 2
- * bytes (which is the length of the jump instruction). Then we
- * pass this address to serial_puts().
- */
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
-# define serial_early_puts(str) \
- .section .rodata; \
- 7: \
- .ascii "Early:"; \
- .ascii __FILE__; \
- .ascii ": "; \
- .ascii str; \
- .asciz "\n"; \
- .previous; \
- R0.L = 7b; \
- R0.H = 7b; \
- update_serial_early_string_addr \
- call _uart_early_puts;
-#else
-# define serial_early_puts(str)
-#endif
-
-#endif
-
-#endif
+++ /dev/null
-/*
- * serial.h - common serial defines for early debug and serial driver.
- * any functions defined here must be always_inline since
- * initcode cannot have function calls.
- *
- * Copyright (c) 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_CPU_SERIAL1_H__
-#define __BFIN_CPU_SERIAL1_H__
-
-#include <asm/mach-common/bits/uart.h>
-
-#ifndef __ASSEMBLY__
-
-#include <asm/clock.h>
-
-#define MMR_UART(n) _PASTE_UART(n, UART, DLL)
-#ifdef UART_DLL
-# define UART0_DLL UART_DLL
-# if CONFIG_UART_CONSOLE != 0
-# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
-# endif
-#endif
-#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE)
-
-#define LOB(x) ((x) & 0xFF)
-#define HIB(x) (((x) >> 8) & 0xFF)
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-struct bfin_mmr_serial {
-#if BFIN_UART_HW_VER == 2
- u16 dll;
- u16 __pad_0;
- u16 dlh;
- u16 __pad_1;
- u16 gctl;
- u16 __pad_2;
- u16 lcr;
- u16 __pad_3;
- u16 mcr;
- u16 __pad_4;
- u16 lsr;
- u16 __pad_5;
- u16 msr;
- u16 __pad_6;
- u16 scr;
- u16 __pad_7;
- u16 ier_set;
- u16 __pad_8;
- u16 ier_clear;
- u16 __pad_9;
- u16 thr;
- u16 __pad_10;
- u16 rbr;
- u16 __pad_11;
-#else
- union {
- u16 dll;
- u16 thr;
- const u16 rbr;
- };
- const u16 __spad0;
- union {
- u16 dlh;
- u16 ier;
- };
- const u16 __spad1;
- const u16 iir;
- u16 __pad_0;
- u16 lcr;
- u16 __pad_1;
- u16 mcr;
- u16 __pad_2;
- u16 lsr;
- u16 __pad_3;
- u16 msr;
- u16 __pad_4;
- u16 scr;
- u16 __pad_5;
- const u32 __spad2;
- u16 gctl;
- u16 __pad_6;
-#endif
-};
-
-#define uart_lsr_t uint32_t
-#define _lsr_read(p) bfin_read(&p->lsr)
-#define _lsr_write(p, v) bfin_write(&p->lsr, v)
-
-#if BFIN_UART_HW_VER == 2
-# define ACCESS_LATCH()
-# define ACCESS_PORT_IER()
-#else
-# define ACCESS_LATCH() bfin_write_or(&pUART->lcr, DLAB)
-# define ACCESS_PORT_IER() bfin_write_and(&pUART->lcr, ~DLAB)
-#endif
-
-__attribute__((always_inline))
-static inline void serial_early_do_mach_portmux(char port, int mux_mask,
- int mux_func, int port_pin)
-{
- switch (port) {
-#if defined(__ADSPBF54x__)
- case 'B':
- bfin_write_PORTB_MUX((bfin_read_PORTB_MUX() &
- ~mux_mask) | mux_func);
- bfin_write_PORTB_FER(bfin_read_PORTB_FER() | port_pin);
- break;
- case 'E':
- bfin_write_PORTE_MUX((bfin_read_PORTE_MUX() &
- ~mux_mask) | mux_func);
- bfin_write_PORTE_FER(bfin_read_PORTE_FER() | port_pin);
- break;
-#endif
-#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF52x__)
- case 'F':
- bfin_write_PORTF_MUX((bfin_read_PORTF_MUX() &
- ~mux_mask) | mux_func);
- bfin_write_PORTF_FER(bfin_read_PORTF_FER() | port_pin);
- break;
- case 'G':
- bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() &
- ~mux_mask) | mux_func);
- bfin_write_PORTG_FER(bfin_read_PORTG_FER() | port_pin);
- break;
- case 'H':
- bfin_write_PORTH_MUX((bfin_read_PORTH_MUX() &
- ~mux_mask) | mux_func);
- bfin_write_PORTH_FER(bfin_read_PORTH_FER() | port_pin);
- break;
-#endif
- default:
- break;
- }
-}
-
-__attribute__((always_inline))
-static inline void serial_early_do_portmux(void)
-{
-#if defined(__ADSPBF50x__)
- switch (CONFIG_UART_CONSOLE) {
- case 0:
- serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK,
- PORT_x_MUX_7_FUNC_1, PG12); /* TX: G; mux 7; func 1; PG12 */
- serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK,
- PORT_x_MUX_7_FUNC_1, PG13); /* RX: G; mux 7; func 1; PG13 */
- break;
- case 1:
- serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK,
- PORT_x_MUX_3_FUNC_1, PF7); /* TX: F; mux 3; func 1; PF6 */
- serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK,
- PORT_x_MUX_3_FUNC_1, PF6); /* RX: F; mux 3; func 1; PF7 */
- break;
- }
-#elif defined(__ADSPBF51x__)
- switch (CONFIG_UART_CONSOLE) {
- case 0:
- serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK,
- PORT_x_MUX_5_FUNC_2, PG9); /* TX: G; mux 5; func 2; PG9 */
- serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK,
- PORT_x_MUX_5_FUNC_2, PG10); /* RX: G; mux 5; func 2; PG10 */
- break;
- case 1:
- serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK,
- PORT_x_MUX_3_FUNC_2, PH7); /* TX: H; mux 3; func 2; PH6 */
- serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK,
- PORT_x_MUX_3_FUNC_2, PH6); /* RX: H; mux 3; func 2; PH7 */
- break;
- }
-#elif defined(__ADSPBF52x__)
- switch (CONFIG_UART_CONSOLE) {
- case 0:
- serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK,
- PORT_x_MUX_2_FUNC_3, PG7); /* TX: G; mux 2; func 3; PG7 */
- serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK,
- PORT_x_MUX_2_FUNC_3, PG8); /* RX: G; mux 2; func 3; PG8 */
- break;
- case 1:
- serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK,
- PORT_x_MUX_5_FUNC_3, PF14); /* TX: F; mux 5; func 3; PF14 */
- serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK,
- PORT_x_MUX_5_FUNC_3, PF15); /* RX: F; mux 5; func 3; PF15 */
- break;
- }
-#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
- const uint16_t func[] = { PFDE, PFTE, };
- bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]);
- bfin_write_PORTF_FER(bfin_read_PORTF_FER() |
- (1 << P_IDENT(P_UART(RX))) |
- (1 << P_IDENT(P_UART(TX))));
-#elif defined(__ADSPBF54x__)
- switch (CONFIG_UART_CONSOLE) {
- case 0:
- serial_early_do_mach_portmux('E', PORT_x_MUX_7_MASK,
- PORT_x_MUX_7_FUNC_1, PE7); /* TX: E; mux 7; func 1; PE7 */
- serial_early_do_mach_portmux('E', PORT_x_MUX_8_MASK,
- PORT_x_MUX_8_FUNC_1, PE8); /* RX: E; mux 8; func 1; PE8 */
- break;
- case 1:
- serial_early_do_mach_portmux('H', PORT_x_MUX_0_MASK,
- PORT_x_MUX_0_FUNC_1, PH0); /* TX: H; mux 0; func 1; PH0 */
- serial_early_do_mach_portmux('H', PORT_x_MUX_1_MASK,
- PORT_x_MUX_1_FUNC_1, PH1); /* RX: H; mux 1; func 1; PH1 */
- break;
- case 2:
- serial_early_do_mach_portmux('B', PORT_x_MUX_4_MASK,
- PORT_x_MUX_4_FUNC_1, PB4); /* TX: B; mux 4; func 1; PB4 */
- serial_early_do_mach_portmux('B', PORT_x_MUX_5_MASK,
- PORT_x_MUX_5_FUNC_1, PB5); /* RX: B; mux 5; func 1; PB5 */
- break;
- case 3:
- serial_early_do_mach_portmux('B', PORT_x_MUX_6_MASK,
- PORT_x_MUX_6_FUNC_1, PB6); /* TX: B; mux 6; func 1; PB6 */
- serial_early_do_mach_portmux('B', PORT_x_MUX_7_MASK,
- PORT_x_MUX_7_FUNC_1, PB7); /* RX: B; mux 7; func 1; PB7 */
- break;
- }
-#elif defined(__ADSPBF561__)
- /* UART pins could be GPIO, but they aren't pin muxed. */
-#else
-# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
-# error "missing portmux logic for UART"
-# endif
-#endif
- SSYNC();
-}
-
-__attribute__((always_inline))
-static inline int uart_init(uint32_t uart_base)
-{
- /* always enable UART -- avoids anomalies 05000309 and 05000350 */
- bfin_write(&pUART->gctl, UCEN);
-
- /* Set LCR to Word Lengh 8-bit word select */
- bfin_write(&pUART->lcr, WLS_8);
-
- SSYNC();
-
- return 0;
-}
-
-__attribute__((always_inline))
-static inline int serial_early_init(uint32_t uart_base)
-{
- /* handle portmux crap on different Blackfins */
- serial_do_portmux();
-
- return uart_init(uart_base);
-}
-
-__attribute__((always_inline))
-static inline int serial_early_uninit(uint32_t uart_base)
-{
- /* disable the UART by clearing UCEN */
- bfin_write(&pUART->gctl, 0);
-
- return 0;
-}
-
-__attribute__((always_inline))
-static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor)
-{
- /* Set DLAB in LCR to Access DLL and DLH */
- ACCESS_LATCH();
- SSYNC();
-
- /* Program the divisor to get the baud rate we want */
- bfin_write(&pUART->dll, LOB(divisor));
- bfin_write(&pUART->dlh, HIB(divisor));
- SSYNC();
-
- /* Clear DLAB in LCR to Access THR RBR IER */
- ACCESS_PORT_IER();
- SSYNC();
-}
-
-__attribute__((always_inline))
-static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
-{
- /* Translate from baud into divisor in terms of SCLK. The
- * weird multiplication is to make sure we over sample just
- * a little rather than under sample the incoming signals.
- */
-#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
- uint16_t divisor = (early_get_uart_clk() + baud * 8) / (baud * 16)
- - ANOMALY_05000230;
-#else
- uint16_t divisor = early_division(early_get_uart_clk() + (baud * 8),
- baud * 16) - ANOMALY_05000230;
-#endif
-
- serial_set_divisor(uart_base, divisor);
-}
-
-__attribute__((always_inline))
-static inline void serial_early_put_div(uint16_t divisor)
-{
- uint32_t uart_base = UART_BASE;
-
- /* Set DLAB in LCR to Access DLL and DLH */
- ACCESS_LATCH();
- SSYNC();
-
- /* Program the divisor to get the baud rate we want */
- bfin_write(&pUART->dll, LOB(divisor));
- bfin_write(&pUART->dlh, HIB(divisor));
- SSYNC();
-
- /* Clear DLAB in LCR to Access THR RBR IER */
- ACCESS_PORT_IER();
- SSYNC();
-}
-
-__attribute__((always_inline))
-static inline uint16_t serial_early_get_div(void)
-{
- uint32_t uart_base = UART_BASE;
-
- /* Set DLAB in LCR to Access DLL and DLH */
- ACCESS_LATCH();
- SSYNC();
-
- uint8_t dll = bfin_read(&pUART->dll);
- uint8_t dlh = bfin_read(&pUART->dlh);
- uint16_t divisor = (dlh << 8) | dll;
-
- /* Clear DLAB in LCR to Access THR RBR IER */
- ACCESS_PORT_IER();
- SSYNC();
-
- return divisor;
-}
-
-#endif
-
-#endif
+++ /dev/null
-/*
- * serial.h - common serial defines for early debug and serial driver.
- * any functions defined here must be always_inline since
- * initcode cannot have function calls.
- *
- * Copyright (c) 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_CPU_SERIAL4_H__
-#define __BFIN_CPU_SERIAL4_H__
-
-#include <asm/mach-common/bits/uart4.h>
-
-#ifndef __ASSEMBLY__
-
-#include <asm/clock.h>
-
-#define MMR_UART(n) _PASTE_UART(n, UART, REVID)
-#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE)
-
-struct bfin_mmr_serial {
- u32 revid;
- u32 control;
- u32 status;
- u32 scr;
- u32 clock;
- u32 emask;
- u32 emaskst;
- u32 emaskcl;
- u32 rbr;
- u32 thr;
- u32 taip;
- u32 tsr;
- u32 rsr;
- u32 txdiv_cnt;
- u32 rxdiv_cnt;
-};
-#define uart_lsr_t uint32_t
-#define _lsr_read(p) bfin_read(&p->status)
-#define _lsr_write(p, v) bfin_write(&p->status, v)
-
-__attribute__((always_inline))
-static inline void serial_early_do_mach_portmux(char port, int mux_mask,
- int mux_func, int port_pin)
-{
- switch (port) {
- case 'D':
- bfin_write_PORTD_MUX((bfin_read_PORTD_MUX() &
- ~mux_mask) | mux_func);
- bfin_write_PORTD_FER_SET(port_pin);
- break;
- case 'G':
- bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() &
- ~mux_mask) | mux_func);
- bfin_write_PORTG_FER_SET(port_pin);
- break;
- }
-}
-
-__attribute__((always_inline))
-static inline void serial_early_do_portmux(void)
-{
-#if defined(__ADSPBF60x__)
- switch (CONFIG_UART_CONSOLE) {
- case 0:
- serial_early_do_mach_portmux('D', PORT_x_MUX_7_MASK,
- PORT_x_MUX_7_FUNC_2, PD7); /* TX: D; mux 7; func 2; PD7 */
- serial_early_do_mach_portmux('D', PORT_x_MUX_8_MASK,
- PORT_x_MUX_8_FUNC_2, PD8); /* RX: D; mux 8; func 2; PD8 */
- break;
- case 1:
- serial_early_do_mach_portmux('G', PORT_x_MUX_15_MASK,
- PORT_x_MUX_15_FUNC_1, PG15); /* TX: G; mux 15; func 1; PG15 */
- serial_early_do_mach_portmux('G', PORT_x_MUX_14_MASK,
- PORT_x_MUX_14_FUNC_1, PG14); /* RX: G; mux 14; func 1; PG14 */
- break;
- }
-#else
-# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
-# error "missing portmux logic for UART"
-# endif
-#endif
- SSYNC();
-}
-
-__attribute__((always_inline))
-static inline int uart_init(uint32_t uart_base)
-{
- /* always enable UART to 8-bit mode */
- bfin_write(&pUART->control, UEN | UMOD_UART | WLS_8);
-
- SSYNC();
-
- return 0;
-}
-
-__attribute__((always_inline))
-static inline int serial_early_init(uint32_t uart_base)
-{
- /* handle portmux crap on different Blackfins */
- serial_do_portmux();
-
- return uart_init(uart_base);
-}
-
-__attribute__((always_inline))
-static inline int serial_early_uninit(uint32_t uart_base)
-{
- /* disable the UART by clearing UEN */
- bfin_write(&pUART->control, 0);
-
- return 0;
-}
-
-__attribute__((always_inline))
-static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor)
-{
- /* Program the divisor to get the baud rate we want */
- bfin_write(&pUART->clock, divisor);
- SSYNC();
-}
-
-__attribute__((always_inline))
-static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
-{
- uint16_t divisor = early_division(early_get_uart_clk(), baud * 16);
-
- /* Program the divisor to get the baud rate we want */
- serial_set_divisor(uart_base, divisor);
-}
-
-__attribute__((always_inline))
-static inline void serial_early_put_div(uint32_t divisor)
-{
- uint32_t uart_base = UART_BASE;
- bfin_write(&pUART->clock, divisor);
-}
-
-__attribute__((always_inline))
-static inline uint32_t serial_early_get_div(void)
-{
- uint32_t uart_base = UART_BASE;
- return bfin_read(&pUART->clock);
-}
-
-#endif
-
-#endif
#include <asm/mach-common/bits/watchdog.h>
#include <asm/mach-common/bits/core.h>
#include <asm/mach-common/bits/pll.h>
-
-#include "serial.h"
+#include <asm/serial.h>
/* It may seem odd that we make calls to functions even though we haven't
* relocated ourselves yet out of {flash,ram,wherever}. This is OK because
--- /dev/null
+/*
+ * serial.h - common serial defines for early debug and serial driver.
+ * any functions defined here must be always_inline since
+ * initcode cannot have function calls.
+ *
+ * Copyright (c) 2004-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_CPU_SERIAL_H__
+#define __BFIN_CPU_SERIAL_H__
+
+#include <asm/blackfin.h>
+#include <asm/portmux.h>
+
+#ifndef CONFIG_UART_CONSOLE
+# define CONFIG_UART_CONSOLE 0
+#endif
+
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+# define BFIN_DEBUG_EARLY_SERIAL 1
+#else
+# define BFIN_DEBUG_EARLY_SERIAL 0
+#endif
+
+#if defined(__ADSPBF60x__)
+# define BFIN_UART_HW_VER 4
+#elif defined(__ADSPBF50x__) || defined(__ADSPBF54x__)
+# define BFIN_UART_HW_VER 2
+#else
+# define BFIN_UART_HW_VER 1
+#endif
+
+#define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx
+#define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx)
+#define _P_UART(n, pin) _PASTE_UART(n, P_UART, pin)
+#define P_UART(pin) _P_UART(CONFIG_UART_CONSOLE, pin)
+
+#define pUART ((volatile struct bfin_mmr_serial *)uart_base)
+
+#ifndef __ASSEMBLY__
+__attribute__((always_inline))
+static inline void serial_do_portmux(void);
+#endif
+
+#if BFIN_UART_HW_VER < 4
+# include "serial1.h"
+#else
+# include "serial4.h"
+#endif
+
+#ifndef __ASSEMBLY__
+
+__attribute__((always_inline))
+static inline void serial_do_portmux(void)
+{
+ if (!BFIN_DEBUG_EARLY_SERIAL) {
+ const unsigned short pins[] = { P_UART(RX), P_UART(TX), 0, };
+ peripheral_request_list(pins, "bfin-uart");
+ return;
+ }
+
+ serial_early_do_portmux();
+}
+
+#ifndef BFIN_IN_INITCODE
+__attribute__((always_inline))
+static inline void serial_early_puts(const char *s)
+{
+ if (BFIN_DEBUG_EARLY_SERIAL) {
+ serial_puts("Early: ");
+ serial_puts(s);
+ }
+}
+#endif
+
+#else
+
+.macro serial_early_init
+#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM)
+ call __serial_early_init;
+#endif
+.endm
+
+.macro serial_early_set_baud
+#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM)
+ R0.L = LO(CONFIG_BAUDRATE);
+ R0.H = HI(CONFIG_BAUDRATE);
+ call __serial_early_set_baud;
+#endif
+.endm
+
+#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
+#define update_serial_early_string_addr \
+ R1.L = _start; \
+ R1.H = _start; \
+ R0 = R0 - R1; \
+ R1.L = 0; \
+ R1.H = 0x2000; \
+ R0 = R0 + R1;
+#else
+#define update_serial_early_string_addr
+#endif
+
+/* Since we embed the string right into our .text section, we need
+ * to find its address. We do this by getting our PC and adding 2
+ * bytes (which is the length of the jump instruction). Then we
+ * pass this address to serial_puts().
+ */
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+# define serial_early_puts(str) \
+ .section .rodata; \
+ 7: \
+ .ascii "Early:"; \
+ .ascii __FILE__; \
+ .ascii ": "; \
+ .ascii str; \
+ .asciz "\n"; \
+ .previous; \
+ R0.L = 7b; \
+ R0.H = 7b; \
+ update_serial_early_string_addr \
+ call _uart_early_puts;
+#else
+# define serial_early_puts(str)
+#endif
+
+#endif
+
+#endif
--- /dev/null
+/*
+ * serial.h - common serial defines for early debug and serial driver.
+ * any functions defined here must be always_inline since
+ * initcode cannot have function calls.
+ *
+ * Copyright (c) 2004-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_CPU_SERIAL1_H__
+#define __BFIN_CPU_SERIAL1_H__
+
+#include <asm/mach-common/bits/uart.h>
+
+#ifndef __ASSEMBLY__
+
+#include <asm/clock.h>
+
+#define MMR_UART(n) _PASTE_UART(n, UART, DLL)
+#ifdef UART_DLL
+# define UART0_DLL UART_DLL
+# if CONFIG_UART_CONSOLE != 0
+# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
+# endif
+#endif
+#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE)
+
+#define LOB(x) ((x) & 0xFF)
+#define HIB(x) (((x) >> 8) & 0xFF)
+
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits. So use a helper macro to streamline this.
+ */
+struct bfin_mmr_serial {
+#if BFIN_UART_HW_VER == 2
+ u16 dll;
+ u16 __pad_0;
+ u16 dlh;
+ u16 __pad_1;
+ u16 gctl;
+ u16 __pad_2;
+ u16 lcr;
+ u16 __pad_3;
+ u16 mcr;
+ u16 __pad_4;
+ u16 lsr;
+ u16 __pad_5;
+ u16 msr;
+ u16 __pad_6;
+ u16 scr;
+ u16 __pad_7;
+ u16 ier_set;
+ u16 __pad_8;
+ u16 ier_clear;
+ u16 __pad_9;
+ u16 thr;
+ u16 __pad_10;
+ u16 rbr;
+ u16 __pad_11;
+#else
+ union {
+ u16 dll;
+ u16 thr;
+ const u16 rbr;
+ };
+ const u16 __spad0;
+ union {
+ u16 dlh;
+ u16 ier;
+ };
+ const u16 __spad1;
+ const u16 iir;
+ u16 __pad_0;
+ u16 lcr;
+ u16 __pad_1;
+ u16 mcr;
+ u16 __pad_2;
+ u16 lsr;
+ u16 __pad_3;
+ u16 msr;
+ u16 __pad_4;
+ u16 scr;
+ u16 __pad_5;
+ const u32 __spad2;
+ u16 gctl;
+ u16 __pad_6;
+#endif
+};
+
+#define uart_lsr_t uint32_t
+#define _lsr_read(p) bfin_read(&p->lsr)
+#define _lsr_write(p, v) bfin_write(&p->lsr, v)
+
+#if BFIN_UART_HW_VER == 2
+# define ACCESS_LATCH()
+# define ACCESS_PORT_IER()
+#else
+# define ACCESS_LATCH() bfin_write_or(&pUART->lcr, DLAB)
+# define ACCESS_PORT_IER() bfin_write_and(&pUART->lcr, ~DLAB)
+#endif
+
+__attribute__((always_inline))
+static inline void serial_early_do_mach_portmux(char port, int mux_mask,
+ int mux_func, int port_pin)
+{
+ switch (port) {
+#if defined(__ADSPBF54x__)
+ case 'B':
+ bfin_write_PORTB_MUX((bfin_read_PORTB_MUX() &
+ ~mux_mask) | mux_func);
+ bfin_write_PORTB_FER(bfin_read_PORTB_FER() | port_pin);
+ break;
+ case 'E':
+ bfin_write_PORTE_MUX((bfin_read_PORTE_MUX() &
+ ~mux_mask) | mux_func);
+ bfin_write_PORTE_FER(bfin_read_PORTE_FER() | port_pin);
+ break;
+#endif
+#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF52x__)
+ case 'F':
+ bfin_write_PORTF_MUX((bfin_read_PORTF_MUX() &
+ ~mux_mask) | mux_func);
+ bfin_write_PORTF_FER(bfin_read_PORTF_FER() | port_pin);
+ break;
+ case 'G':
+ bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() &
+ ~mux_mask) | mux_func);
+ bfin_write_PORTG_FER(bfin_read_PORTG_FER() | port_pin);
+ break;
+ case 'H':
+ bfin_write_PORTH_MUX((bfin_read_PORTH_MUX() &
+ ~mux_mask) | mux_func);
+ bfin_write_PORTH_FER(bfin_read_PORTH_FER() | port_pin);
+ break;
+#endif
+ default:
+ break;
+ }
+}
+
+__attribute__((always_inline))
+static inline void serial_early_do_portmux(void)
+{
+#if defined(__ADSPBF50x__)
+ switch (CONFIG_UART_CONSOLE) {
+ case 0:
+ serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK,
+ PORT_x_MUX_7_FUNC_1, PG12); /* TX: G; mux 7; func 1; PG12 */
+ serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK,
+ PORT_x_MUX_7_FUNC_1, PG13); /* RX: G; mux 7; func 1; PG13 */
+ break;
+ case 1:
+ serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK,
+ PORT_x_MUX_3_FUNC_1, PF7); /* TX: F; mux 3; func 1; PF6 */
+ serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK,
+ PORT_x_MUX_3_FUNC_1, PF6); /* RX: F; mux 3; func 1; PF7 */
+ break;
+ }
+#elif defined(__ADSPBF51x__)
+ switch (CONFIG_UART_CONSOLE) {
+ case 0:
+ serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK,
+ PORT_x_MUX_5_FUNC_2, PG9); /* TX: G; mux 5; func 2; PG9 */
+ serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK,
+ PORT_x_MUX_5_FUNC_2, PG10); /* RX: G; mux 5; func 2; PG10 */
+ break;
+ case 1:
+ serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK,
+ PORT_x_MUX_3_FUNC_2, PH7); /* TX: H; mux 3; func 2; PH6 */
+ serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK,
+ PORT_x_MUX_3_FUNC_2, PH6); /* RX: H; mux 3; func 2; PH7 */
+ break;
+ }
+#elif defined(__ADSPBF52x__)
+ switch (CONFIG_UART_CONSOLE) {
+ case 0:
+ serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK,
+ PORT_x_MUX_2_FUNC_3, PG7); /* TX: G; mux 2; func 3; PG7 */
+ serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK,
+ PORT_x_MUX_2_FUNC_3, PG8); /* RX: G; mux 2; func 3; PG8 */
+ break;
+ case 1:
+ serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK,
+ PORT_x_MUX_5_FUNC_3, PF14); /* TX: F; mux 5; func 3; PF14 */
+ serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK,
+ PORT_x_MUX_5_FUNC_3, PF15); /* RX: F; mux 5; func 3; PF15 */
+ break;
+ }
+#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
+ const uint16_t func[] = { PFDE, PFTE, };
+ bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]);
+ bfin_write_PORTF_FER(bfin_read_PORTF_FER() |
+ (1 << P_IDENT(P_UART(RX))) |
+ (1 << P_IDENT(P_UART(TX))));
+#elif defined(__ADSPBF54x__)
+ switch (CONFIG_UART_CONSOLE) {
+ case 0:
+ serial_early_do_mach_portmux('E', PORT_x_MUX_7_MASK,
+ PORT_x_MUX_7_FUNC_1, PE7); /* TX: E; mux 7; func 1; PE7 */
+ serial_early_do_mach_portmux('E', PORT_x_MUX_8_MASK,
+ PORT_x_MUX_8_FUNC_1, PE8); /* RX: E; mux 8; func 1; PE8 */
+ break;
+ case 1:
+ serial_early_do_mach_portmux('H', PORT_x_MUX_0_MASK,
+ PORT_x_MUX_0_FUNC_1, PH0); /* TX: H; mux 0; func 1; PH0 */
+ serial_early_do_mach_portmux('H', PORT_x_MUX_1_MASK,
+ PORT_x_MUX_1_FUNC_1, PH1); /* RX: H; mux 1; func 1; PH1 */
+ break;
+ case 2:
+ serial_early_do_mach_portmux('B', PORT_x_MUX_4_MASK,
+ PORT_x_MUX_4_FUNC_1, PB4); /* TX: B; mux 4; func 1; PB4 */
+ serial_early_do_mach_portmux('B', PORT_x_MUX_5_MASK,
+ PORT_x_MUX_5_FUNC_1, PB5); /* RX: B; mux 5; func 1; PB5 */
+ break;
+ case 3:
+ serial_early_do_mach_portmux('B', PORT_x_MUX_6_MASK,
+ PORT_x_MUX_6_FUNC_1, PB6); /* TX: B; mux 6; func 1; PB6 */
+ serial_early_do_mach_portmux('B', PORT_x_MUX_7_MASK,
+ PORT_x_MUX_7_FUNC_1, PB7); /* RX: B; mux 7; func 1; PB7 */
+ break;
+ }
+#elif defined(__ADSPBF561__)
+ /* UART pins could be GPIO, but they aren't pin muxed. */
+#else
+# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
+# error "missing portmux logic for UART"
+# endif
+#endif
+ SSYNC();
+}
+
+__attribute__((always_inline))
+static inline int uart_init(uint32_t uart_base)
+{
+ /* always enable UART -- avoids anomalies 05000309 and 05000350 */
+ bfin_write(&pUART->gctl, UCEN);
+
+ /* Set LCR to Word Lengh 8-bit word select */
+ bfin_write(&pUART->lcr, WLS_8);
+
+ SSYNC();
+
+ return 0;
+}
+
+__attribute__((always_inline))
+static inline int serial_early_init(uint32_t uart_base)
+{
+ /* handle portmux crap on different Blackfins */
+ serial_do_portmux();
+
+ return uart_init(uart_base);
+}
+
+__attribute__((always_inline))
+static inline int serial_early_uninit(uint32_t uart_base)
+{
+ /* disable the UART by clearing UCEN */
+ bfin_write(&pUART->gctl, 0);
+
+ return 0;
+}
+
+__attribute__((always_inline))
+static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor)
+{
+ /* Set DLAB in LCR to Access DLL and DLH */
+ ACCESS_LATCH();
+ SSYNC();
+
+ /* Program the divisor to get the baud rate we want */
+ bfin_write(&pUART->dll, LOB(divisor));
+ bfin_write(&pUART->dlh, HIB(divisor));
+ SSYNC();
+
+ /* Clear DLAB in LCR to Access THR RBR IER */
+ ACCESS_PORT_IER();
+ SSYNC();
+}
+
+__attribute__((always_inline))
+static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
+{
+ /* Translate from baud into divisor in terms of SCLK. The
+ * weird multiplication is to make sure we over sample just
+ * a little rather than under sample the incoming signals.
+ */
+#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
+ uint16_t divisor = (early_get_uart_clk() + baud * 8) / (baud * 16)
+ - ANOMALY_05000230;
+#else
+ uint16_t divisor = early_division(early_get_uart_clk() + (baud * 8),
+ baud * 16) - ANOMALY_05000230;
+#endif
+
+ serial_set_divisor(uart_base, divisor);
+}
+
+__attribute__((always_inline))
+static inline void serial_early_put_div(uint16_t divisor)
+{
+ uint32_t uart_base = UART_BASE;
+
+ /* Set DLAB in LCR to Access DLL and DLH */
+ ACCESS_LATCH();
+ SSYNC();
+
+ /* Program the divisor to get the baud rate we want */
+ bfin_write(&pUART->dll, LOB(divisor));
+ bfin_write(&pUART->dlh, HIB(divisor));
+ SSYNC();
+
+ /* Clear DLAB in LCR to Access THR RBR IER */
+ ACCESS_PORT_IER();
+ SSYNC();
+}
+
+__attribute__((always_inline))
+static inline uint16_t serial_early_get_div(void)
+{
+ uint32_t uart_base = UART_BASE;
+
+ /* Set DLAB in LCR to Access DLL and DLH */
+ ACCESS_LATCH();
+ SSYNC();
+
+ uint8_t dll = bfin_read(&pUART->dll);
+ uint8_t dlh = bfin_read(&pUART->dlh);
+ uint16_t divisor = (dlh << 8) | dll;
+
+ /* Clear DLAB in LCR to Access THR RBR IER */
+ ACCESS_PORT_IER();
+ SSYNC();
+
+ return divisor;
+}
+
+#endif
+
+#endif
--- /dev/null
+/*
+ * serial.h - common serial defines for early debug and serial driver.
+ * any functions defined here must be always_inline since
+ * initcode cannot have function calls.
+ *
+ * Copyright (c) 2004-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_CPU_SERIAL4_H__
+#define __BFIN_CPU_SERIAL4_H__
+
+#include <asm/mach-common/bits/uart4.h>
+
+#ifndef __ASSEMBLY__
+
+#include <asm/clock.h>
+
+#define MMR_UART(n) _PASTE_UART(n, UART, REVID)
+#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE)
+
+struct bfin_mmr_serial {
+ u32 revid;
+ u32 control;
+ u32 status;
+ u32 scr;
+ u32 clock;
+ u32 emask;
+ u32 emaskst;
+ u32 emaskcl;
+ u32 rbr;
+ u32 thr;
+ u32 taip;
+ u32 tsr;
+ u32 rsr;
+ u32 txdiv_cnt;
+ u32 rxdiv_cnt;
+};
+#define uart_lsr_t uint32_t
+#define _lsr_read(p) bfin_read(&p->status)
+#define _lsr_write(p, v) bfin_write(&p->status, v)
+
+__attribute__((always_inline))
+static inline void serial_early_do_mach_portmux(char port, int mux_mask,
+ int mux_func, int port_pin)
+{
+ switch (port) {
+ case 'D':
+ bfin_write_PORTD_MUX((bfin_read_PORTD_MUX() &
+ ~mux_mask) | mux_func);
+ bfin_write_PORTD_FER_SET(port_pin);
+ break;
+ case 'G':
+ bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() &
+ ~mux_mask) | mux_func);
+ bfin_write_PORTG_FER_SET(port_pin);
+ break;
+ }
+}
+
+__attribute__((always_inline))
+static inline void serial_early_do_portmux(void)
+{
+#if defined(__ADSPBF60x__)
+ switch (CONFIG_UART_CONSOLE) {
+ case 0:
+ serial_early_do_mach_portmux('D', PORT_x_MUX_7_MASK,
+ PORT_x_MUX_7_FUNC_2, PD7); /* TX: D; mux 7; func 2; PD7 */
+ serial_early_do_mach_portmux('D', PORT_x_MUX_8_MASK,
+ PORT_x_MUX_8_FUNC_2, PD8); /* RX: D; mux 8; func 2; PD8 */
+ break;
+ case 1:
+ serial_early_do_mach_portmux('G', PORT_x_MUX_15_MASK,
+ PORT_x_MUX_15_FUNC_1, PG15); /* TX: G; mux 15; func 1; PG15 */
+ serial_early_do_mach_portmux('G', PORT_x_MUX_14_MASK,
+ PORT_x_MUX_14_FUNC_1, PG14); /* RX: G; mux 14; func 1; PG14 */
+ break;
+ }
+#else
+# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
+# error "missing portmux logic for UART"
+# endif
+#endif
+ SSYNC();
+}
+
+__attribute__((always_inline))
+static inline int uart_init(uint32_t uart_base)
+{
+ /* always enable UART to 8-bit mode */
+ bfin_write(&pUART->control, UEN | UMOD_UART | WLS_8);
+
+ SSYNC();
+
+ return 0;
+}
+
+__attribute__((always_inline))
+static inline int serial_early_init(uint32_t uart_base)
+{
+ /* handle portmux crap on different Blackfins */
+ serial_do_portmux();
+
+ return uart_init(uart_base);
+}
+
+__attribute__((always_inline))
+static inline int serial_early_uninit(uint32_t uart_base)
+{
+ /* disable the UART by clearing UEN */
+ bfin_write(&pUART->control, 0);
+
+ return 0;
+}
+
+__attribute__((always_inline))
+static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor)
+{
+ /* Program the divisor to get the baud rate we want */
+ bfin_write(&pUART->clock, divisor);
+ SSYNC();
+}
+
+__attribute__((always_inline))
+static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
+{
+ uint16_t divisor = early_division(early_get_uart_clk(), baud * 16);
+
+ /* Program the divisor to get the baud rate we want */
+ serial_set_divisor(uart_base, divisor);
+}
+
+__attribute__((always_inline))
+static inline void serial_early_put_div(uint32_t divisor)
+{
+ uint32_t uart_base = UART_BASE;
+ bfin_write(&pUART->clock, divisor);
+}
+
+__attribute__((always_inline))
+static inline uint32_t serial_early_get_div(void)
+{
+ uint32_t uart_base = UART_BASE;
+ return bfin_read(&pUART->clock);
+}
+
+#endif
+
+#endif
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
+COBJS-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
--- /dev/null
+/*
+ * U-boot - serial.c Blackfin Serial Driver
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
+ * BuyWays B.V. (www.buyways.nl)
+ *
+ * Based heavily on:
+ * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
+ * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
+ * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
+ * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
+ *
+ * Based on code from 68328 version serial driver imlpementation which was:
+ * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
+ * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+/* Anomaly notes:
+ * 05000086 - we don't support autobaud
+ * 05000099 - we only use DR bit, so losing others is not a problem
+ * 05000100 - we don't use the UART_IIR register
+ * 05000215 - we poll the uart (no dma/interrupts)
+ * 05000225 - no workaround possible, but this shouldnt cause errors ...
+ * 05000230 - we tweak the baud rate calculation slightly
+ * 05000231 - we always use 1 stop bit
+ * 05000309 - we always enable the uart before we modify it in anyway
+ * 05000350 - we always enable the uart regardless of boot mode
+ * 05000363 - we don't support break signals, so don't generate one
+ */
+
+#include <common.h>
+#include <post.h>
+#include <watchdog.h>
+#include <serial.h>
+#include <linux/compiler.h>
+#include <asm/blackfin.h>
+#include <asm/serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_UART_CONSOLE
+
+#ifdef CONFIG_DEBUG_SERIAL
+static uart_lsr_t cached_lsr[256];
+static uart_lsr_t cached_rbr[256];
+static size_t cache_count;
+
+/* The LSR is read-to-clear on some parts, so we have to make sure status
+ * bits aren't inadvertently lost when doing various tests. This also
+ * works around anomaly 05000099 at the same time by keeping a cumulative
+ * tally of all the status bits.
+ */
+static uart_lsr_t uart_lsr_save;
+static uart_lsr_t uart_lsr_read(uint32_t uart_base)
+{
+ uart_lsr_t lsr = _lsr_read(pUART);
+ uart_lsr_save |= (lsr & (OE|PE|FE|BI));
+ return lsr | uart_lsr_save;
+}
+/* Just do the clear for everyone since it can't hurt. */
+static void uart_lsr_clear(uint32_t uart_base)
+{
+ uart_lsr_save = 0;
+ _lsr_write(pUART, -1);
+}
+#else
+/* When debugging is disabled, we only care about the DR bit, so if other
+ * bits get set/cleared, we don't really care since we don't read them
+ * anyways (and thus anomaly 05000099 is irrelevant).
+ */
+static inline uart_lsr_t uart_lsr_read(uint32_t uart_base)
+{
+ return _lsr_read(pUART);
+}
+static void uart_lsr_clear(uint32_t uart_base)
+{
+ _lsr_write(pUART, -1);
+}
+#endif
+
+static void uart_putc(uint32_t uart_base, const char c)
+{
+ /* send a \r for compatibility */
+ if (c == '\n')
+ serial_putc('\r');
+
+ WATCHDOG_RESET();
+
+ /* wait for the hardware fifo to clear up */
+ while (!(uart_lsr_read(uart_base) & THRE))
+ continue;
+
+ /* queue the character for transmission */
+ bfin_write(&pUART->thr, c);
+ SSYNC();
+
+ WATCHDOG_RESET();
+}
+
+static int uart_tstc(uint32_t uart_base)
+{
+ WATCHDOG_RESET();
+ return (uart_lsr_read(uart_base) & DR) ? 1 : 0;
+}
+
+static int uart_getc(uint32_t uart_base)
+{
+ uint16_t uart_rbr_val;
+
+ /* wait for data ! */
+ while (!uart_tstc(uart_base))
+ continue;
+
+ /* grab the new byte */
+ uart_rbr_val = bfin_read(&pUART->rbr);
+
+#ifdef CONFIG_DEBUG_SERIAL
+ /* grab & clear the LSR */
+ uart_lsr_t uart_lsr_val = uart_lsr_read(uart_base);
+
+ cached_lsr[cache_count] = uart_lsr_val;
+ cached_rbr[cache_count] = uart_rbr_val;
+ cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr);
+
+ if (uart_lsr_val & (OE|PE|FE|BI)) {
+ printf("\n[SERIAL ERROR]\n");
+ do {
+ --cache_count;
+ printf("\t%3zu: RBR=0x%02x LSR=0x%02x\n", cache_count,
+ cached_rbr[cache_count], cached_lsr[cache_count]);
+ } while (cache_count > 0);
+ return -1;
+ }
+#endif
+ uart_lsr_clear(uart_base);
+
+ return uart_rbr_val;
+}
+
+#if CONFIG_POST & CONFIG_SYS_POST_UART
+# define LOOP(x) x
+#else
+# define LOOP(x)
+#endif
+
+#if BFIN_UART_HW_VER < 4
+
+LOOP(
+static void uart_loop(uint32_t uart_base, int state)
+{
+ u16 mcr;
+
+ /* Drain the TX fifo first so bytes don't come back */
+ while (!(uart_lsr_read(uart_base) & TEMT))
+ continue;
+
+ mcr = bfin_read(&pUART->mcr);
+ if (state)
+ mcr |= LOOP_ENA | MRTS;
+ else
+ mcr &= ~(LOOP_ENA | MRTS);
+ bfin_write(&pUART->mcr, mcr);
+}
+)
+
+#else
+
+LOOP(
+static void uart_loop(uint32_t uart_base, int state)
+{
+ u32 control;
+
+ /* Drain the TX fifo first so bytes don't come back */
+ while (!(uart_lsr_read(uart_base) & TEMT))
+ continue;
+
+ control = bfin_read(&pUART->control);
+ if (state)
+ control |= LOOP_ENA | MRTS;
+ else
+ control &= ~(LOOP_ENA | MRTS);
+ bfin_write(&pUART->control, control);
+}
+)
+
+#endif
+
+static inline void __serial_set_baud(uint32_t uart_base, uint32_t baud)
+{
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+ serial_early_set_baud(uart_base, baud);
+#else
+ uint16_t divisor = (get_uart_clk() + (baud * 8)) / (baud * 16)
+ - ANOMALY_05000230;
+
+ /* Program the divisor to get the baud rate we want */
+ serial_set_divisor(uart_base, divisor);
+#endif
+}
+
+static void uart_puts(uint32_t uart_base, const char *s)
+{
+ while (*s)
+ uart_putc(uart_base, *s++);
+}
+
+#define DECL_BFIN_UART(n) \
+static int uart##n##_init(void) \
+{ \
+ const unsigned short pins[] = { _P_UART(n, RX), _P_UART(n, TX), 0, }; \
+ peripheral_request_list(pins, "bfin-uart"); \
+ uart_init(MMR_UART(n)); \
+ __serial_set_baud(MMR_UART(n), gd->baudrate); \
+ uart_lsr_clear(MMR_UART(n)); \
+ return 0; \
+} \
+\
+static int uart##n##_uninit(void) \
+{ \
+ return serial_early_uninit(MMR_UART(n)); \
+} \
+\
+static void uart##n##_setbrg(void) \
+{ \
+ __serial_set_baud(MMR_UART(n), gd->baudrate); \
+} \
+\
+static int uart##n##_getc(void) \
+{ \
+ return uart_getc(MMR_UART(n)); \
+} \
+\
+static int uart##n##_tstc(void) \
+{ \
+ return uart_tstc(MMR_UART(n)); \
+} \
+\
+static void uart##n##_putc(const char c) \
+{ \
+ uart_putc(MMR_UART(n), c); \
+} \
+\
+static void uart##n##_puts(const char *s) \
+{ \
+ uart_puts(MMR_UART(n), s); \
+} \
+\
+LOOP( \
+static void uart##n##_loop(int state) \
+{ \
+ uart_loop(MMR_UART(n), state); \
+} \
+) \
+\
+struct serial_device bfin_serial##n##_device = { \
+ .name = "bfin_uart"#n, \
+ .start = uart##n##_init, \
+ .stop = uart##n##_uninit, \
+ .setbrg = uart##n##_setbrg, \
+ .getc = uart##n##_getc, \
+ .tstc = uart##n##_tstc, \
+ .putc = uart##n##_putc, \
+ .puts = uart##n##_puts, \
+ LOOP(.loop = uart##n##_loop) \
+};
+
+#ifdef UART0_RBR
+DECL_BFIN_UART(0)
+#endif
+#ifdef UART1_RBR
+DECL_BFIN_UART(1)
+#endif
+#ifdef UART2_RBR
+DECL_BFIN_UART(2)
+#endif
+#ifdef UART3_RBR
+DECL_BFIN_UART(3)
+#endif
+
+__weak struct serial_device *default_serial_console(void)
+{
+#if CONFIG_UART_CONSOLE == 0
+ return &bfin_serial0_device;
+#elif CONFIG_UART_CONSOLE == 1
+ return &bfin_serial1_device;
+#elif CONFIG_UART_CONSOLE == 2
+ return &bfin_serial2_device;
+#elif CONFIG_UART_CONSOLE == 3
+ return &bfin_serial3_device;
+#endif
+}
+
+void bfin_serial_initialize(void)
+{
+#ifdef UART0_RBR
+ serial_register(&bfin_serial0_device);
+#endif
+#ifdef UART1_RBR
+ serial_register(&bfin_serial1_device);
+#endif
+#ifdef UART2_RBR
+ serial_register(&bfin_serial2_device);
+#endif
+#ifdef UART3_RBR
+ serial_register(&bfin_serial3_device);
+#endif
+}
+
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+inline void uart_early_putc(uint32_t uart_base, const char c)
+{
+ /* send a \r for compatibility */
+ if (c == '\n')
+ uart_early_putc(uart_base, '\r');
+
+ /* wait for the hardware fifo to clear up */
+ while (!(_lsr_read(pUART) & THRE))
+ continue;
+
+ /* queue the character for transmission */
+ bfin_write(&pUART->thr, c);
+ SSYNC();
+}
+
+void uart_early_puts(const char *s)
+{
+ while (*s)
+ uart_early_putc(UART_BASE, *s++);
+}
+
+/* Symbol for our assembly to call. */
+void _serial_early_set_baud(uint32_t baud)
+{
+ serial_early_set_baud(UART_BASE, baud);
+}
+
+/* Symbol for our assembly to call. */
+void _serial_early_init(void)
+{
+ serial_early_init(UART_BASE);
+}
+#endif
+
+#elif defined(CONFIG_UART_MEM)
+
+char serial_logbuf[CONFIG_UART_MEM];
+char *serial_logbuf_head = serial_logbuf;
+
+int serial_mem_init(void)
+{
+ serial_logbuf_head = serial_logbuf;
+ return 0;
+}
+
+void serial_mem_setbrg(void)
+{
+}
+
+int serial_mem_tstc(void)
+{
+ return 0;
+}
+
+int serial_mem_getc(void)
+{
+ return 0;
+}
+
+void serial_mem_putc(const char c)
+{
+ *serial_logbuf_head = c;
+ if (++serial_logbuf_head == serial_logbuf + CONFIG_UART_MEM)
+ serial_logbuf_head = serial_logbuf;
+}
+
+void serial_mem_puts(const char *s)
+{
+ while (*s)
+ serial_putc(*s++);
+}
+
+struct serial_device bfin_serial_mem_device = {
+ .name = "bfin_uart_mem",
+ .start = serial_mem_init,
+ .setbrg = serial_mem_setbrg,
+ .getc = serial_mem_getc,
+ .tstc = serial_mem_tstc,
+ .putc = serial_mem_putc,
+ .puts = serial_mem_puts,
+};
+
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &bfin_serial_mem_device;
+}
+
+void bfin_serial_initialize(void)
+{
+ serial_register(&bfin_serial_mem_device);
+}
+#endif /* CONFIG_UART_MEM */
#ifndef CONFIG_BAUDRATE
# define CONFIG_BAUDRATE 57600
#endif
+#ifdef CONFIG_UART_CONSOLE
+# define CONFIG_BFIN_SERIAL
+#endif
/*
* Debug Settings
projects / oweals / u-boot.git / commitdiff