armv8: ls1012a: Add support of ls1012aqds board
authorPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Fri, 3 Jun 2016 13:11:34 +0000 (18:41 +0530)
committerYork Sun <york.sun@nxp.com>
Fri, 3 Jun 2016 21:12:51 +0000 (14:12 -0700)
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
14 files changed:
arch/arm/Kconfig
arch/arm/dts/Makefile
arch/arm/dts/fsl-ls1012a-qds.dts [new file with mode: 0644]
arch/arm/dts/fsl-ls1012a-qds.dtsi [new file with mode: 0644]
arch/arm/dts/fsl-ls1012a.dtsi [new file with mode: 0644]
board/freescale/ls1012aqds/Kconfig [new file with mode: 0644]
board/freescale/ls1012aqds/MAINTAINERS [new file with mode: 0644]
board/freescale/ls1012aqds/Makefile [new file with mode: 0644]
board/freescale/ls1012aqds/README [new file with mode: 0644]
board/freescale/ls1012aqds/ls1012aqds.c [new file with mode: 0644]
board/freescale/ls1012aqds/ls1012aqds_qixis.h [new file with mode: 0644]
configs/ls1012aqds_qspi_defconfig [new file with mode: 0644]
include/configs/ls1012a_common.h [new file with mode: 0644]
include/configs/ls1012aqds.h [new file with mode: 0644]

index 7a77b6a03701749dae3c1e3027d4602a43fcb606..30fc32a853f6891b5a2c4a437f6d9655717896d1 100644 (file)
@@ -696,6 +696,15 @@ config TARGET_HIKEY
          Support for HiKey 96boards platform. It features a HI6220
          SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
 
+config TARGET_LS1012AQDS
+       bool "Support ls1012aqds"
+       select ARM64
+       help
+         Support for Freescale LS1012AQDS platform.
+         The LS1012A Development System (QDS) is a high-performance
+         development platform that supports the QorIQ LS1012A
+         Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
        bool "Support ls1021aqds"
        select CPU_V7
@@ -852,6 +861,7 @@ source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
index 92c7545bb5a2d583f26607d2bab3381f5fb4f1c0..47ec7a28ec5f19bbca08ab29baa63d6a0d71daf3 100644 (file)
@@ -120,7 +120,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
        fsl-ls2080a-rdb.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
        fsl-ls1043a-qds-lpuart.dtb \
-       fsl-ls1043a-rdb.dtb
+       fsl-ls1043a-rdb.dtb \
+       fsl-ls1012a-qds.dtb
 
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
 
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dts b/arch/arm/dts/fsl-ls1012a-qds.dts
new file mode 100644 (file)
index 0000000..76db36c
--- /dev/null
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-qds.dtsi"
+
+/ {
+       chosen {
+               stdout-path = &duart0;
+       };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi
new file mode 100644 (file)
index 0000000..dde7134
--- /dev/null
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+       model = "LS1012A QDS Board";
+       aliases {
+               spi0 = &qspi;
+               spi1 = &dspi0;
+       };
+};
+
+&dspi0 {
+       bus-num = <0>;
+       status = "okay";
+
+       dflash0: n25q128a {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               reg = <0>;
+               spi-max-frequency = <1000000>; /* input clock */
+       };
+
+       dflash1: sst25wf040b {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               spi-max-frequency = <3500000>;
+               reg = <1>;
+       };
+
+       dflash2: en25s64 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               spi-max-frequency = <3500000>;
+               reg = <2>;
+       };
+};
+
+&qspi {
+       bus-num = <0>;
+       status = "okay";
+
+       qflash0: s25fl128s@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               spi-max-frequency = <20000000>;
+               reg = <0>;
+       };
+};
+
+&i2c0 {
+       status = "okay";
+       pca9547@77 {
+               compatible = "philips,pca9547";
+               reg = <0x77>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               i2c@0 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0>;
+
+                       rtc@68 {
+                               compatible = "dallas,ds3232";
+                               reg = <0x68>;
+                               /* IRQ10_B */
+                               interrupts = <0 150 0x4>;
+                       };
+               };
+
+               i2c@2 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x2>;
+
+                       ina220@40 {
+                               compatible = "ti,ina220";
+                               reg = <0x40>;
+                               shunt-resistor = <1000>;
+                       };
+
+                       ina220@41 {
+                               compatible = "ti,ina220";
+                               reg = <0x41>;
+                               shunt-resistor = <1000>;
+                       };
+               };
+
+               i2c@3 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x3>;
+
+                       eeprom@56 {
+                               compatible = "at24,24c512";
+                               reg = <0x56>;
+                       };
+
+                       eeprom@57 {
+                               compatible = "at24,24c512";
+                               reg = <0x57>;
+                       };
+
+                       adt7461a@4c {
+                               compatible = "adt7461a";
+                               reg = <0x4c>;
+                       };
+               };
+       };
+};
+
+&duart0 {
+       status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
new file mode 100644 (file)
index 0000000..546a87a
--- /dev/null
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/include/ "skeleton64.dtsi"
+
+/ {
+       compatible = "fsl,ls1012a";
+       interrupt-parent = <&gic>;
+       cpus {
+               #address-cells = <2>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x0>;
+                       clocks = <&clockgen 1 0>;
+               };
+
+       };
+
+       sysclk: sysclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <100000000>;
+               clock-output-names = "sysclk";
+       };
+
+       gic: interrupt-controller@1400000 {
+               compatible = "arm,gic-400";
+               #interrupt-cells = <3>;
+               interrupt-controller;
+               reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+                     <0x0 0x1402000 0 0x2000>, /* GICC */
+                     <0x0 0x1404000 0 0x2000>, /* GICH */
+                     <0x0 0x1406000 0 0x2000>; /* GICV */
+               interrupts = <1 9 0xf08>;
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               clockgen: clocking@1ee1000 {
+                       compatible = "fsl,ls1012a-clockgen";
+                       reg = <0x0 0x1ee1000 0x0 0x1000>;
+                       #clock-cells = <2>;
+                       clocks = <&sysclk>;
+               };
+
+               dspi0: dspi@2100000 {
+                       compatible = "fsl,vf610-dspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x2100000 0x0 0x10000>;
+                       interrupts = <0 64 0x4>;
+                       clock-names = "dspi";
+                       clocks = <&clockgen 4 0>;
+                       num-cs = <6>;
+                       big-endian;
+                       status = "disabled";
+               };
+
+
+               i2c0: i2c@2180000 {
+                       compatible = "fsl,vf610-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x2180000 0x0 0x10000>;
+                       interrupts = <0 56 0x4>;
+                       clock-names = "i2c";
+                       clocks = <&clockgen 4 0>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@2190000 {
+                       compatible = "fsl,vf610-i2c";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x2190000 0x0 0x10000>;
+                       interrupts = <0 57 0x4>;
+                       clock-names = "i2c";
+                       clocks = <&clockgen 4 0>;
+                       status = "disabled";
+               };
+
+               duart0: serial@21c0500 {
+                       compatible = "fsl,ns16550", "ns16550a";
+                       reg = <0x00 0x21c0500 0x0 0x100>;
+                       interrupts = <0 54 0x4>;
+                       clocks = <&clockgen 4 0>;
+               };
+
+               duart1: serial@21c0600 {
+                       compatible = "fsl,ns16550", "ns16550a";
+                       reg = <0x00 0x21c0600 0x0 0x100>;
+                       interrupts = <0 54 0x4>;
+                       clocks = <&clockgen 4 0>;
+               };
+
+               qspi: quadspi@1550000 {
+                       compatible = "fsl,vf610-qspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0x1550000 0x0 0x10000>,
+                               <0x0 0x40000000 0x0 0x4000000>;
+                       reg-names = "QuadSPI", "QuadSPI-memory";
+                       num-cs = <2>;
+                       big-endian;
+                       status = "disabled";
+               };
+
+       };
+};
diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
new file mode 100644 (file)
index 0000000..1257ec8
--- /dev/null
@@ -0,0 +1,15 @@
+if TARGET_LS1012AQDS
+
+config SYS_BOARD
+       default "ls1012aqds"
+
+config SYS_VENDOR
+       default "freescale"
+
+config SYS_SOC
+       default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+       default "ls1012aqds"
+
+endif
diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS
new file mode 100644 (file)
index 0000000..27c4aff
--- /dev/null
@@ -0,0 +1,6 @@
+LS1012AQDS BOARD
+M:     Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S:     Maintained
+F:     board/freescale/ls1012aqds/
+F:     include/configs/ls1012aqds.h
+F:     configs/ls1012aqds_qspi_defconfig
diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
new file mode 100644 (file)
index 0000000..0b813f9
--- /dev/null
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012aqds.o
diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README
new file mode 100644 (file)
index 0000000..dee4b30
--- /dev/null
@@ -0,0 +1,59 @@
+Overview
+--------
+QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012AQDS board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
+SoC overview.
+
+LS1012AQDS board Overview
+-----------------------
+ - SERDES Connections, 4 lanes supporting:
+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - SATA 3.0
+ - DDR Controller
+     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ - QSPI Controller
+     - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+       signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
+       emulator
+ - USB 3.0
+    - One USB 3.0 controller with integrated PHY
+    - One high-speed USB 3.0 port
+ - USB 2.0
+    - One USB 2.0 controller with ULPI interface
+ - Two enhanced secure digital host controllers:
+    - SDHC1 controller can be connected to onboard SDHC connector
+    - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - 5 SAI
+    - One SAI port with audio codec SGTL5000:
+       â€¢ Provides MIC bias
+       â€¢ Provides headphone and line output
+    - One SAI port terminated at 2x6 header
+    - Three SAI Tx/Rx ports terminated at 2x3 headers
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images         | Size  |QSPI Flash Address
+------------------------------------------
+RCW + PBI      | 1MB   | 0x4000_0000
+U-boot                 | 1MB   | 0x4010_0000
+U-boot Env     | 1MB   | 0x4020_0000
+PPA FIT image  | 2MB   | 0x4050_0000
+Linux ITB      | ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
new file mode 100644 (file)
index 0000000..71eea82
--- /dev/null
@@ -0,0 +1,234 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
+#include <ahci.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_mmdc.h>
+#include <spl.h>
+#include <netdev.h>
+
+#include "../common/qixis.h"
+#include "ls1012aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+       int timeout = 1000;
+
+       out_be32(ptr, value);
+
+       while (in_be32(ptr) & bits) {
+               udelay(100);
+               timeout--;
+       }
+       if (timeout <= 0)
+               puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+       char buf[64];
+       u8 sw;
+
+       sw = QIXIS_READ(arch);
+       printf("Board Arch: V%d, ", sw >> 4);
+       printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+       sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
+
+       if (sw & QIXIS_LBMAP_ALTBANK)
+               printf("flash: 2\n");
+       else
+               printf("flash: 1\n");
+
+       printf("FPGA: v%d (%s), build %d",
+              (int)QIXIS_READ(scver), qixis_read_tag(buf),
+              (int)qixis_read_minor());
+
+       /* the timestamp string contains "\n" at the end */
+       printf(" on %s", qixis_read_time(buf));
+       return 0;
+}
+
+void mmdc_init(void)
+{
+       struct mmdc_p_regs *mmdc =
+               (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+       out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+       /* configure timing parms */
+       out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+       out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+       out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+       out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+       /* other parms  */
+       out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
+       out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+       out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+       out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+       /* out of reset delays */
+       out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+       /* physical parms */
+       out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+       out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+       /* Enable MMDC */
+       out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+       /* dram init sequence: update MRs */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+       out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+                               CMD_BANK_ADDR_3));
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+       out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+                               CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+       /* dram init sequence: ZQCL */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+                               CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+       set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+                               CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+                               FORCE_ZQ_AUTO_CALIBRATION);
+
+       /* Calibrations now: wr lvl */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+                               CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+                               CMD_BANK_ADDR_1));
+       out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+       set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+       mdelay(1);
+
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+       out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+       mdelay(1);
+
+       /* Calibrations now: Read DQS gating calibration */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+                               CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+       out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+       out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+       set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+                               AUTO_RD_DQS_GATING_CALIBRATION_EN,
+                               AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+       out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+                               CMD_BANK_ADDR_3));
+
+       /* Calibrations now: Read calibration */
+       out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+                               CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+       out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+                               CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+       out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
+       set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+                               AUTO_RD_CALIBRATION_EN,
+                               AUTO_RD_CALIBRATION_EN);
+
+       out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+                               CMD_BANK_ADDR_3));
+
+       /* PD, SR */
+       out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+       out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+       /* refresh scheme */
+       set_wait_for_bits_clear(&mmdc->mdref,
+                               CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+                               START_REFRESH);
+
+       /* disable CON_REQ */
+       out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+       mmdc_init();
+
+       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+       return 0;
+}
+
+int board_early_init_f(void)
+{
+       fsl_lsch2_early_init_f();
+
+       return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+       u8 mux_sdhc_cd = 0x80;
+
+       i2c_set_bus_num(0);
+
+       i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
+       return 0;
+}
+#endif
+
+int board_init(void)
+{
+       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
+                                  CONFIG_SYS_CCI400_ADDR;
+
+       /* Set CCI-400 control override register to enable barrier
+        * transaction */
+       out_le32(&cci->ctrl_ord,
+                CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+       enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+       gd->env_addr = (ulong)&default_environment[0];
+#endif
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+       arch_fixup_fdt(blob);
+
+       ft_cpu_setup(blob, bd);
+
+       return 0;
+}
+#endif
diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
new file mode 100644 (file)
index 0000000..584f604
--- /dev/null
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __LS1043AQDS_QIXIS_H__
+#define __LS1043AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1043AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK            0xe0
+#define BRDCFG4_EMISEL_SHIFT           5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66                        0x0
+#define QIXIS_SYSCLK_83                        0x1
+#define QIXIS_SYSCLK_100               0x2
+#define QIXIS_SYSCLK_125               0x3
+#define QIXIS_SYSCLK_133               0x4
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66                        0x0
+#define QIXIS_DDRCLK_100               0x1
+#define QIXIS_DDRCLK_125               0x2
+#define QIXIS_DDRCLK_133               0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100               0x0
+#define QIXIS_SDCLK1_125               0x1
+#define QIXIS_SDCLK1_165               0x2
+#define QIXIS_SDCLK1_100_SP            0x3
+
+#endif
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
new file mode 100644 (file)
index 0000000..2bc178c
--- /dev/null
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AQDS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
new file mode 100644 (file)
index 0000000..ccd94ec
--- /dev/null
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __LS1012A_COMMON_H
+#define __LS1012A_COMMON_H
+
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_FSL_LSCH2
+#define CONFIG_LS1012A
+#define CONFIG_GICV2
+
+#define        CONFIG_SYS_HAS_SERDES
+
+#include <asm/arch/config.h>
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define CONFIG_SYS_TEXT_BASE           0x40100000
+
+#define CONFIG_SYS_FSL_CLK
+#define CONFIG_SYS_CLK_FREQ            100000000
+#define CONFIG_DDR_CLK_FREQ            125000000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F      1
+
+#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#define CONFIG_SYS_LOAD_ADDR   (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY      0
+#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY              CONFIG_SYS_CLK_FREQ/4   /* 25MHz */
+
+/* CSU */
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 128 * 1024)
+
+/*SPI device */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR                0x400d0000
+#define CONFIG_ENV_SPI_BUS             0
+#define CONFIG_ENV_SPI_CS              0
+#define CONFIG_ENV_SPI_MAX_HZ          1000000
+#define CONFIG_ENV_SPI_MODE            0x03
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_FSL_SPI_INTERFACE
+#define CONFIG_SF_DATAFLASH
+
+#define CONFIG_FSL_QSPI
+#define QSPI0_AMBA_BASE                0x40000000
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_BAR
+
+#define FSL_QSPI_FLASH_SIZE            (1 << 24)
+#define FSL_QSPI_FLASH_NUM             2
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE                        0x40000          /* 256KB */
+#define CONFIG_ENV_OFFSET              0x200000        /* 2MB */
+#define CONFIG_ENV_SECT_SIZE           0x40000
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
+
+#define CONFIG_CONS_INDEX       1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE     1
+#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
+
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+
+/* Command line configuration */
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define CONFIG_SYS_HZ                  1000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE           128
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS              \
+       "initrd_high=0xffffffff\0"              \
+       "verify=no\0"                           \
+       "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
+       "loadaddr=0x80100000\0"                 \
+       "kernel_addr=0x100000\0"                \
+       "ramdisk_addr=0x800000\0"               \
+       "ramdisk_size=0x2000000\0"              \
+       "fdt_high=0xffffffffffffffff\0"         \
+       "initrd_high=0xffffffffffffffff\0"      \
+       "kernel_start=0xa00000\0"               \
+       "kernel_load=0xa0000000\0"              \
+       "kernel_size=0x2800000\0"               \
+       "console=ttyAMA0,38400n8\0"
+
+#define CONFIG_BOOTARGS                "console=ttyS0,115200 root=/dev/ram0 " \
+                               "earlycon=uart8250,mmio,0x21c0500"
+#define CONFIG_BOOTCOMMAND             "sf probe 0:0; sf read $kernel_load "\
+                                       "$kernel_start $kernel_size && "\
+                                       "bootm $kernel_load"
+#define CONFIG_BOOTDELAY               10
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE              512     /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+                                       sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING         1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS             64      /* max command args */
+
+#define CONFIG_PANIC_HANG
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1012A_COMMON_H */
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
new file mode 100644 (file)
index 0000000..2d84095
--- /dev/null
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __LS1012AQDS_H__
+#define __LS1012AQDS_H__
+
+#include "ls1012a_common.h"
+
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR     1
+#define CONFIG_CHIP_SELECTS_PER_CTRL   1
+#define CONFIG_NR_DRAM_BANKS           2
+#define CONFIG_SYS_SDRAM_SIZE          0x40000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1         0x05180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2         0x85180000
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR       0x66
+#define QIXIS_LBMAP_BRDCFG_REG         0x04
+#define QIXIS_LBMAP_SWITCH             6
+#define QIXIS_LBMAP_MASK               0xf7
+#define QIXIS_LBMAP_SHIFT              0
+#define QIXIS_LBMAP_DFLTBANK           0x00
+#define QIXIS_LBMAP_ALTBANK            0x08
+#define QIXIS_RST_CTL_RESET            0x41
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START  0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
+#endif
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI           0x77
+#define I2C_MUX_PCA_ADDR_SEC           0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR               0x18
+#define I2C_MUX_CH_DEFAULT             0x8
+#define I2C_MUX_CH_CH7301              0xC
+#define I2C_MUX_CH5                    0xD
+#define I2C_MUX_CH7                    0xF
+
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+
+/*
+* RTC configuration
+*/
+#define RTC
+#define CONFIG_RTC_PCF8563 1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
+#define CONFIG_CMD_DATE
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM    0
+#define CONFIG_SYS_I2C_EEPROM_ADDR   0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN     1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR           0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
+
+/* DSPI */
+#define CONFIG_FSL_DSPI1
+#define CONFIG_DEFAULT_SPI_BUS 1
+
+#define CONFIG_CMD_SPI
+#define MMAP_DSPI          DSPI1_BASE_ADDR
+
+#define CONFIG_SYS_DSPI_CTAR0   1
+
+#define CONFIG_SYS_DSPI_CTAR1  (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+                               DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+                               DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+                               DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_SST /* cs1 */
+
+#define CONFIG_SYS_DSPI_CTAR2  (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+                               DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+                               DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
+                               DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
+
+#define CONFIG_SYS_DSPI_CTAR3  (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+                               DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+                               DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+                               DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_EON /* cs3 */
+
+#define CONFIG_SF_DEFAULT_SPEED      10000000
+#define CONFIG_SF_DEFAULT_MODE       SPI_MODE_0
+#define CONFIG_SF_DEFAULT_BUS        1
+#define CONFIG_SF_DEFAULT_CS         0
+
+/*
+* USB
+*/
+/* EHCI Support - disbaled by default */
+/*#define CONFIG_HAS_FSL_DR_USB*/
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+/*XHCI Support - enabled by default*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
+#define CONFIG_USB_STORAGE
+#endif
+
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define        CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA                                AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID            1
+#define CONFIG_SYS_SCSI_MAX_LUN                        1
+#define CONFIG_SYS_SCSI_MAX_DEVICE             (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+                                               CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_PCI             /* Enable PCI/PCIE */
+#define CONFIG_PCIE1           /* PCIE controller 1 */
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF  0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE      0x00001000      /* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF  0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE      0x00001000      /* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS         0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF    0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE                0x00010000      /* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START       0x80000000
+#define CONFIG_SYS_MEMTEST_END         0x9fffffff
+
+#define CONFIG_MISC_INIT_R
+
+#endif /* __LS1012AQDS_H__ */