Coding style cleanup. Update CHANGELOG.
authorWolfgang Denk <wd@denx.de>
Mon, 6 Aug 2007 00:17:36 +0000 (02:17 +0200)
committerWolfgang Denk <wd@denx.de>
Mon, 6 Aug 2007 00:17:36 +0000 (02:17 +0200)
Signed-off-by: Wolfgang Denk <wd@denx.de>
16 files changed:
CHANGELOG
drivers/ati_ids.h
drivers/ati_radeon_fb.c
drivers/ati_radeon_fb.h
drivers/bios_emulator/atibios.c
drivers/bios_emulator/besys.c
drivers/bios_emulator/biosemu.c
drivers/bios_emulator/biosemui.h
drivers/bios_emulator/include/x86emu/debug.h
drivers/bios_emulator/include/x86emu/prim_ops.h
drivers/bios_emulator/include/x86emu/regs.h
drivers/bios_emulator/x86emu/decode.c
drivers/bios_emulator/x86emu/ops.c
drivers/bios_emulator/x86emu/ops2.c
drivers/bios_emulator/x86emu/prim_ops.c
include/radeon.h

index 58ef66ecdc4c2e0caba7dc343f6aaa5775050457..e07d243bf3f1e981c3ec59b6a145e1d9e745c996 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,64 @@
+commit 221838cc7eb178370ff62aa05920a582e12ac322
+Author: Jason Jin <Jason.jin@freescale.com>
+Date:  Tue Jul 10 09:03:22 2007 +0800
+
+    Remove the bios emulator from MAI board.
+
+    The bios emulator in the MAI board can not pass compile
+    and have a lot of crap in it. remove it and will have a
+    clean and small bios emulator in the drivers directory
+    which can be uesed for every board.
+
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit 5618332409bb96f4448d1712899369fc80c0b489
+Author: Jason Jin <Jason.jin@freescale.com>
+Date:  Fri Jul 13 12:14:59 2007 +0800
+
+    Fix some compile issues for MAI board.
+
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit 0f460a1ee148b648ee242c3157650287d4296260
+Author: Jason Jin <Jason.jin@freescale.com>
+Date:  Fri Jul 13 12:14:58 2007 +0800
+
+    Configurations for ATI video card BIOS emulator
+
+    This patch add definition of the BIOS emulator and the ATI framebuffer
+    driver for MPC8641HPCN board.
+
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+    Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
+
+commit ece92f85053b8df613edcf05b26a416cbc3d629c
+Author: Jason Jin <Jason.jin@freescale.com>
+Date:  Fri Jul 6 08:34:56 2007 +0800
+
+    This is a BIOS emulator, porting from SciTech for u-boot, mainly for
+    ATI video card BIOS. and can be used for x86 code emulation by some
+    modifications.
+
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit 5072188acabde3178fac7f5a597150e6e74fd40c
+Author: Jason Jin <Jason.jin@freescale.com>
+Date:  Fri Jul 6 08:33:33 2007 +0800
+
+    This is a framebuffer driver for ATI video card, can work for PCI9200,
+    X300, X700, X800 ATI video cards.
+
+    Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
+    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
+
+commit 5728be389e65fd47f34b33c2596271eb4db751ae
+Author: Wolfgang Denk <wd@denx.de>
+Date:  Mon Aug 6 01:01:49 2007 +0200
+
+    Coding style cleanup. Update CHANGELOG.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit 8092fef4c29b395958bb649647da7e3775731517
 Author: Martin Krause <Martin.Krause@tqs.de>
 Date:  Tue Dec 12 14:26:01 2006 +0100
index 35fe505735ff95134af6859b0846d3801e456e7f..3e72a7dd4c0d6426d10168ceca222e04d545b9d2 100644 (file)
 #define PCI_CHIP_R423_5D57              0x5D57
 #define PCI_CHIP_RS350_7834             0x7834
 #define PCI_CHIP_RS350_7835             0x7835
-
index e15140ab38de2317d34548d4245f2f38518cbf2f..c174f37b3fa99b88e32dec7c8be7b3129bc6fdff 100644 (file)
@@ -137,7 +137,7 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo)
                }
        } else {
                tmp = INREG(CONFIG_MEMSIZE);
-        }
+       }
 
        /* mem size is bits [28:0], mask off the rest */
        rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
@@ -209,13 +209,13 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg
 #if 0
        /* Workaround from XFree */
        if (rinfo->is_mobility) {
-               /* A temporal workaround for the occational blanking on certain laptop
+               /* A temporal workaround for the occational blanking on certain laptop
                 * panels. This appears to related to the PLL divider registers
                 * (fail to lock?). It occurs even when all dividers are the same
                 * with their old settings. In this case we really don't need to
                 * fiddle with PLL registers. By doing this we can avoid the blanking
                 * problem with some panels.
-                */
+                */
                if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
                    (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
                                          (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
index 1c3ba64cfb0ca254e68e35a1eee679781b374375..b5c4b8b5779eda798f031c81cbaeef4057acc72b 100644 (file)
@@ -5,7 +5,6 @@
  * Most of the definitions here are adapted right from XFree86 *
  ***************************************************************/
 
-
 /*
  * Chip families. Must fit in the low 16 bits of a long word
  */
@@ -38,14 +37,12 @@ enum radeon_family {
                                 ((rinfo)->family == CHIP_FAMILY_RV280)  || \
                                 ((rinfo)->family == CHIP_FAMILY_RS300))
 
-
 #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300)  || \
                                ((rinfo)->family == CHIP_FAMILY_RV350) || \
                                ((rinfo)->family == CHIP_FAMILY_R350)  || \
                                ((rinfo)->family == CHIP_FAMILY_RV380) || \
                                ((rinfo)->family == CHIP_FAMILY_R420))
 
-
 struct radeonfb_info {
        char name[20];
 
@@ -86,7 +83,6 @@ static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
 
 #define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
 
-
 /*
  * 2D Engine helper routines
  */
@@ -106,7 +102,6 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
        printf("radeonfb: Flush Timeout !\n");
 }
 
-
 static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
 {
        int i;
@@ -119,7 +114,6 @@ static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
        printf("radeonfb: FIFO Timeout !\n");
 }
 
-
 static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
 {
        int i;
@@ -137,7 +131,6 @@ static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
        printf("radeonfb: Idle Timeout !\n");
 }
 
-
 #define radeon_engine_idle()           _radeon_engine_idle(rinfo)
 #define radeon_fifo_wait(entries)      _radeon_fifo_wait(rinfo,entries)
 #define radeon_msleep(ms)              _radeon_msleep(rinfo,ms)
@@ -255,9 +248,9 @@ static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
        u32 data;
 
        OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
-       //radeon_pll_errata_after_index(rinfo);
+       /* radeon_pll_errata_after_index(rinfo); */
        data = INREG(CLOCK_CNTL_DATA);
-       //radeon_pll_errata_after_data(rinfo);
+       /* radeon_pll_errata_after_data(rinfo); */
        return data;
 }
 
@@ -266,12 +259,11 @@ static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
 {
 
        OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
-       //radeon_pll_errata_after_index(rinfo);
+       /* radeon_pll_errata_after_index(rinfo); */
        OUTREG(CLOCK_CNTL_DATA, val);
-       //radeon_pll_errata_after_data(rinfo);
+       /* radeon_pll_errata_after_data(rinfo); */
 }
 
-
 static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
                             u32 val, u32 mask)
 {
@@ -283,11 +275,8 @@ static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
        __OUTPLL(rinfo, index, tmp);
 }
 
-
 #define INPLL(addr)                    __INPLL(rinfo, addr)
 #define OUTPLL(index, val)             __OUTPLL(rinfo, index, val)
 #define OUTPLLP(index, val, mask)      __OUTPLLP(rinfo, index, val, mask)
 
-
-
 #endif
index 084339c1b29af6c3b2f1c615aa307c7983414c13..5779f99f1f617cfb8bfc425e389f7d803492968e 100644 (file)
@@ -1,6 +1,6 @@
 /****************************************************************************
 *
-*                    Video BOOT Graphics Card POST Module
+*                   Video BOOT Graphics Card POST Module
 *
 *  ========================================================================
 *   Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
 *
 *  ========================================================================
 *
-* Language:     ANSI C
-* Environment:  Linux Kernel
-* Developer:    Kendall Bennett
+* Language:    ANSI C
+* Environment: Linux Kernel
+* Developer:   Kendall Bennett
 *
-* Description:  Module to implement booting PCI/AGP controllers on the
-*               bus. We use the x86 real mode emulator to run the BIOS on
-*               graphics controllers to bring the cards up.
+* Description: Module to implement booting PCI/AGP controllers on the
+*              bus. We use the x86 real mode emulator to run the BIOS on
+*              graphics controllers to bring the cards up.
 *
-*               Note that at present this module does *not* support
-*               multiple controllers.
+*              Note that at present this module does *not* support
+*              multiple controllers.
 *
-*               The orignal name of this file is warmboot.c.
-*               Jason ported this file to u-boot to run the ATI video card
-*               BIOS in u-boot.
+*              The orignal name of this file is warmboot.c.
+*              Jason ported this file to u-boot to run the ATI video card
+*              BIOS in u-boot.
 ****************************************************************************/
 #include <common.h>
 
 #include <malloc.h>
 
 /* Length of the BIOS image */
-#define MAX_BIOSLEN         (128 * 1024L)
+#define MAX_BIOSLEN        (128 * 1024L)
 
 /* Define some useful types and macros */
-#define true                1
-#define false               0
+#define true               1
+#define false              0
 
 /* Place to save PCI BAR's that we change and later restore */
 static u32 saveROMBaseAddress;
@@ -68,7 +68,7 @@ static u32 saveBaseAddress20;
 
 /****************************************************************************
 PARAMETERS:
-pcidev  - PCI device info for the video card on the bus to boot
+pcidev - PCI device info for the video card on the bus to boot
 VGAInfo - BIOS emulator VGA info structure
 
 REMARKS:
@@ -102,8 +102,8 @@ static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo * VGAInfo)
 
 /****************************************************************************
 PARAMETERS:
-pcidev  - PCI device info for the video card on the bus
-bar     - Place to return the base address register offset to use
+pcidev - PCI device info for the video card on the bus
+bar    - Place to return the base address register offset to use
 
 RETURNS:
 The address to use to map the secondary BIOS (AGP devices)
@@ -166,7 +166,7 @@ static void PCI_fixupIObase(pci_dev_t pcidev, int reg, u32 * base)
 
 /****************************************************************************
 PARAMETERS:
-pcidev  - PCI device info for the video card on the bus
+pcidev - PCI device info for the video card on the bus
 
 RETURNS:
 Pointers to the mapped BIOS image
@@ -196,7 +196,7 @@ void *PCI_mapBIOSImage(pci_dev_t pcidev)
        /* Some cards have problems that stop us from being able to read the
         BIOS image from the ROM BAR. To fix this we have to do some chipset
         specific programming for different cards to solve this problem.
-        */
+       */
 
        if ((BIOSImagePhys = PCI_findBIOSAddr(pcidev, &BIOSImageBAR)) == 0) {
                printf("Find bios addr error\n");
@@ -223,7 +223,7 @@ void *PCI_mapBIOSImage(pci_dev_t pcidev)
 
 /****************************************************************************
 PARAMETERS:
-pcidev  - PCI device info for the video card on the bus
+pcidev - PCI device info for the video card on the bus
 
 REMARKS:
 Unmaps the BIOS image for the device and restores framebuffer mappings
@@ -239,7 +239,7 @@ void PCI_unmapBIOSImage(pci_dev_t pcidev, void *BIOSImage)
 
 /****************************************************************************
 PARAMETERS:
-pcidev  - PCI device info for the video card on the bus to boot
+pcidev - PCI device info for the video card on the bus to boot
 VGAInfo - BIOS emulator VGA info structure
 
 RETURNS:
@@ -294,9 +294,9 @@ static int PCI_postController(pci_dev_t pcidev, BE_VGAInfo * VGAInfo)
 
 /****************************************************************************
 PARAMETERS:
-pcidev      - PCI device info for the video card on the bus to boot
+pcidev     - PCI device info for the video card on the bus to boot
 pVGAInfo    - Place to return VGA info structure is requested
-cleanUp     - True to clean up on exit, false to leave emulator active
+cleanUp            - True to clean up on exit, false to leave emulator active
 
 REMARKS:
 Boots the PCI/AGP video card on the bus using the Video ROM BIOS image
index 894012fa898acd0226b077bd47f4c1a0edf19152..2a8e1a01c1fc948be61fd86f749764e332f748dc 100644 (file)
@@ -251,71 +251,69 @@ hardware does not support mapping the VGA I/O and memory (such as some
 PowerPC systems), we emulate the VGA so that the BIOS will still be able to
 set NonVGA display modes such as on ATI hardware.
 ****************************************************************************/
-static u8 VGA_inpb(
-    const int port)
+static u8 VGA_inpb (const int port)
 {
-    u8 val = 0xff;
-
-    switch (port) {
-        case 0x3C0:
-            /* 3C0 has funky characteristics because it can act as either
-               a data register or index register depending on the state
-               of an internal flip flop in the hardware. Hence we have
-               to emulate that functionality in here. */
-            if (_BE_env.flipFlop3C0 == 0) {
-                /* Access 3C0 as index register*/
-                val = _BE_env.emu3C0;
-                }
-            else {
-                /* Access 3C0 as data register*/
-                if (_BE_env.emu3C0 < ATT_C)
-                    val = _BE_env.emu3C1[_BE_env.emu3C0];
-                }
-            _BE_env.flipFlop3C0 ^= 1;
-            break;
-        case 0x3C1:
-            if (_BE_env.emu3C0 < ATT_C)
-                return _BE_env.emu3C1[_BE_env.emu3C0];
-            break;
-        case 0x3CC:
-            return _BE_env.emu3C2;
-        case 0x3C4:
-            return _BE_env.emu3C4;
-        case 0x3C5:
-            if (_BE_env.emu3C4 < ATT_C)
-                return _BE_env.emu3C5[_BE_env.emu3C4];
-            break;
-        case 0x3C6:
-            return _BE_env.emu3C6;
-        case 0x3C7:
-            return _BE_env.emu3C7;
-        case 0x3C8:
-            return _BE_env.emu3C8;
-        case 0x3C9:
-            if (_BE_env.emu3C7 < PAL_C)
-                return _BE_env.emu3C9[_BE_env.emu3C7++];
-            break;
-        case 0x3CE:
-            return _BE_env.emu3CE;
-        case 0x3CF:
-            if (_BE_env.emu3CE < GRA_C)
-                return _BE_env.emu3CF[_BE_env.emu3CE];
-            break;
-        case 0x3D4:
-            if (_BE_env.emu3C2 & 0x1)
-                return _BE_env.emu3D4;
-            break;
-        case 0x3D5:
-            if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C))
-                return _BE_env.emu3D5[_BE_env.emu3D4];
-            break;
-        case 0x3DA:
-            _BE_env.flipFlop3C0 = 0;
-            val = _BE_env.emu3DA;
-            _BE_env.emu3DA ^= 0x9;
-            break;
-        }
-    return val;
+       u8 val = 0xff;
+
+       switch (port) {
+       case 0x3C0:
+               /* 3C0 has funky characteristics because it can act as either
+                  a data register or index register depending on the state
+                  of an internal flip flop in the hardware. Hence we have
+                  to emulate that functionality in here. */
+               if (_BE_env.flipFlop3C0 == 0) {
+                       /* Access 3C0 as index register */
+                       val = _BE_env.emu3C0;
+               } else {
+                       /* Access 3C0 as data register */
+                       if (_BE_env.emu3C0 < ATT_C)
+                               val = _BE_env.emu3C1[_BE_env.emu3C0];
+               }
+               _BE_env.flipFlop3C0 ^= 1;
+               break;
+       case 0x3C1:
+               if (_BE_env.emu3C0 < ATT_C)
+                       return _BE_env.emu3C1[_BE_env.emu3C0];
+               break;
+       case 0x3CC:
+               return _BE_env.emu3C2;
+       case 0x3C4:
+               return _BE_env.emu3C4;
+       case 0x3C5:
+               if (_BE_env.emu3C4 < ATT_C)
+                       return _BE_env.emu3C5[_BE_env.emu3C4];
+               break;
+       case 0x3C6:
+               return _BE_env.emu3C6;
+       case 0x3C7:
+               return _BE_env.emu3C7;
+       case 0x3C8:
+               return _BE_env.emu3C8;
+       case 0x3C9:
+               if (_BE_env.emu3C7 < PAL_C)
+                       return _BE_env.emu3C9[_BE_env.emu3C7++];
+               break;
+       case 0x3CE:
+               return _BE_env.emu3CE;
+       case 0x3CF:
+               if (_BE_env.emu3CE < GRA_C)
+                       return _BE_env.emu3CF[_BE_env.emu3CE];
+               break;
+       case 0x3D4:
+               if (_BE_env.emu3C2 & 0x1)
+                       return _BE_env.emu3D4;
+               break;
+       case 0x3D5:
+               if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C))
+                       return _BE_env.emu3D5[_BE_env.emu3D4];
+               break;
+       case 0x3DA:
+               _BE_env.flipFlop3C0 = 0;
+               val = _BE_env.emu3DA;
+               _BE_env.emu3DA ^= 0x9;
+               break;
+       }
+       return val;
 }
 
 /****************************************************************************
@@ -328,66 +326,65 @@ Performs an emulated write to one of the 8253 timer registers. For now
 we only emulate timer 0 which is the only timer that the BIOS code appears
 to use.
 ****************************************************************************/
-static void VGA_outpb(
-    int port,
-    u8 val)
+static void VGA_outpb (int port, u8 val)
 {
-    switch (port) {
-        case 0x3C0:
-            /* 3C0 has funky characteristics because it can act as either
-             a data register or index register depending on the state
-             of an internal flip flop in the hardware. Hence we have
-             to emulate that functionality in here.*/
-            if (_BE_env.flipFlop3C0 == 0) {
-                /* Access 3C0 as index register*/
-                _BE_env.emu3C0 = val;
-                }
-            else {
-                /* Access 3C0 as data register*/
-                if (_BE_env.emu3C0 < ATT_C)
-                    _BE_env.emu3C1[_BE_env.emu3C0] = val;
-                }
-            _BE_env.flipFlop3C0 ^= 1;
-            break;
-        case 0x3C2:
-            _BE_env.emu3C2 = val;
-            break;
-        case 0x3C4:
-            _BE_env.emu3C4 = val;
-            break;
-        case 0x3C5:
-            if (_BE_env.emu3C4 < ATT_C)
-                _BE_env.emu3C5[_BE_env.emu3C4] = val;
-            break;
-        case 0x3C6:
-            _BE_env.emu3C6 = val;
-            break;
-        case 0x3C7:
-            _BE_env.emu3C7 = (int)val * 3;
-            break;
-        case 0x3C8:
-            _BE_env.emu3C8 = (int)val * 3;
-            break;
-        case 0x3C9:
-            if (_BE_env.emu3C8 < PAL_C)
-                _BE_env.emu3C9[_BE_env.emu3C8++] = val;
-            break;
-        case 0x3CE:
-            _BE_env.emu3CE = val;
-            break;
-        case 0x3CF:
-            if (_BE_env.emu3CE < GRA_C)
-                _BE_env.emu3CF[_BE_env.emu3CE] = val;
-            break;
-        case 0x3D4:
-            if (_BE_env.emu3C2 & 0x1)
-                _BE_env.emu3D4 = val;
-            break;
-        case 0x3D5:
-            if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C))
-                _BE_env.emu3D5[_BE_env.emu3D4] = val;
-            break;
-        }
+       switch (port) {
+       case 0x3C0:
+               /* 3C0 has funky characteristics because it can act as either
+                  a data register or index register depending on the state
+                  of an internal flip flop in the hardware. Hence we have
+                  to emulate that functionality in here. */
+               if (_BE_env.flipFlop3C0 == 0) {
+                       /* Access 3C0 as index register */
+                       _BE_env.emu3C0 = val;
+               } else {
+                       /* Access 3C0 as data register */
+                       if (_BE_env.emu3C0 < ATT_C)
+                               _BE_env.emu3C1[_BE_env.emu3C0] = val;
+               }
+               _BE_env.flipFlop3C0 ^= 1;
+               break;
+       case 0x3C2:
+               _BE_env.emu3C2 = val;
+               break;
+       case 0x3C4:
+               _BE_env.emu3C4 = val;
+               break;
+       case 0x3C5:
+               if (_BE_env.emu3C4 < ATT_C)
+                       _BE_env.emu3C5[_BE_env.emu3C4] = val;
+               break;
+       case 0x3C6:
+               _BE_env.emu3C6 = val;
+               break;
+       case 0x3C7:
+               _BE_env.emu3C7 = (int) val *3;
+
+               break;
+       case 0x3C8:
+               _BE_env.emu3C8 = (int) val *3;
+
+               break;
+       case 0x3C9:
+               if (_BE_env.emu3C8 < PAL_C)
+                       _BE_env.emu3C9[_BE_env.emu3C8++] = val;
+               break;
+       case 0x3CE:
+               _BE_env.emu3CE = val;
+               break;
+       case 0x3CF:
+               if (_BE_env.emu3CE < GRA_C)
+                       _BE_env.emu3CF[_BE_env.emu3CE] = val;
+               break;
+       case 0x3D4:
+               if (_BE_env.emu3C2 & 0x1)
+                       _BE_env.emu3D4 = val;
+               break;
+       case 0x3D5:
+               if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C))
+                       _BE_env.emu3D5[_BE_env.emu3D4] = val;
+               break;
+       }
 }
 
 /****************************************************************************
index aca594ce711606392e94315617a88442aa37150c..06d4ad380f3e4ed6676e53a33e64352331052cd9 100644 (file)
@@ -1,12 +1,12 @@
 /****************************************************************************
 *
-*                        BIOS emulator and interface
-*                      to Realmode X86 Emulator Library
+*                       BIOS emulator and interface
+*                     to Realmode X86 Emulator Library
 *
 *  Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
 *  Jason Jin <Jason.jin@freescale.com>
 *
-*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*              Copyright (C) 1996-1999 SciTech Software, Inc.
 *
 *  ========================================================================
 *
@@ -16,7 +16,7 @@
 *  both that copyright notice and this permission notice appear in
 *  supporting documentation, and that the name of the authors not be used
 *  in advertising or publicity pertaining to distribution of the software
-*  without specific, written prior permission.  The authors makes no
+*  without specific, written prior permission. The authors makes no
 *  representations about the suitability of this software for any purpose.
 *  It is provided "as is" without express or implied warranty.
 *
 *
 *  ========================================================================
 *
-* Language:     ANSI C
-* Environment:  Any
-* Developer:    Kendall Bennett
+* Language:    ANSI C
+* Environment: Any
+* Developer:   Kendall Bennett
 *
-* Description:  Module implementing the system specific functions. This
-*               module is always compiled and linked in the OS depedent
-*               libraries, and never in a binary portable driver.
+* Description: Module implementing the system specific functions. This
+*              module is always compiled and linked in the OS depedent
+*              libraries, and never in a binary portable driver.
 *
-*               Jason ported this file to u-boot to run the ATI video card BIOS
-*               in u-boot. Made all the video memory be emulated during the
-*               BIOS runing process which may affect the VGA function but the
-*               frambuffer function can work after run the BIOS.
+*              Jason ported this file to u-boot to run the ATI video card BIOS
+*              in u-boot. Made all the video memory be emulated during the
+*              BIOS runing process which may affect the VGA function but the
+*              frambuffer function can work after run the BIOS.
 *
 ****************************************************************************/
 
@@ -67,14 +67,14 @@ static X86EMU_pioFuncs _BE_pio __attribute__((section(".got2"))) = {
        BE_outl,
        };
 
-#define OFF(addr)       (u16)(((addr) >> 0) & 0xffff)
-#define SEG(addr)       (u16)(((addr) >> 4) & 0xf000)
+#define OFF(addr)      (u16)(((addr) >> 0) & 0xffff)
+#define SEG(addr)      (u16)(((addr) >> 4) & 0xf000)
 
 /****************************************************************************
 PARAMETERS:
 debugFlags  - Flags to enable debugging options (debug builds only)
-memSize     - Amount of memory to allocate for real mode machine
-info        - Pointer to default VGA device information
+memSize            - Amount of memory to allocate for real mode machine
+info       - Pointer to default VGA device information
 
 REMARKS:
 This functions initialises the BElib, and uses the passed in
@@ -116,7 +116,7 @@ int X86API BE_init(u32 debugFlags, int memSize, BE_VGAInfo * info, int shared)
 
 /****************************************************************************
 PARAMETERS:
-info        - Pointer to VGA device information to make current
+info       - Pointer to VGA device information to make current
 
 REMARKS:
 This function sets the VGA BIOS functions in the emulator to point to the
@@ -150,7 +150,7 @@ void X86API BE_setVGA(BE_VGAInfo * info)
 
 /****************************************************************************
 PARAMETERS:
-info        - Pointer to VGA device information to retrieve current
+info       - Pointer to VGA device information to retrieve current
 
 REMARKS:
 This function returns the VGA BIOS functions currently active in the
@@ -172,16 +172,16 @@ void X86API BE_getVGA(BE_VGAInfo * info)
 
 /****************************************************************************
 PARAMETERS:
-r_seg   - Segment for pointer to convert
-r_off   - Offset for pointer to convert
+r_seg  - Segment for pointer to convert
+r_off  - Offset for pointer to convert
 
 REMARKS:
 This function maps a real mode pointer in the emulator memory to a protected
 mode pointer that can be used to directly access the memory.
 
-NOTE:   The memory is *always* in little endian format, son on non-x86
-        systems you will need to do endian translations to access this
-        memory.
+NOTE:  The memory is *always* in little endian format, son on non-x86
+       systems you will need to do endian translations to access this
+       memory.
 ****************************************************************************/
 void *X86API BE_mapRealPointer(uint r_seg, uint r_off)
 {
@@ -197,9 +197,9 @@ void *X86API BE_mapRealPointer(uint r_seg, uint r_off)
 
 /****************************************************************************
 PARAMETERS:
-len     - Return the length of the VESA buffer
-rseg    - Place to store VESA buffer segment
-roff    - Place to store VESA buffer offset
+len    - Return the length of the VESA buffer
+rseg   - Place to store VESA buffer segment
+roff   - Place to store VESA buffer offset
 
 REMARKS:
 This function returns the address of the VESA transfer buffer in real
@@ -207,9 +207,9 @@ _BE_piomode emulator memory. The VESA transfer buffer is always 1024 bytes long,
 and located at 15Kb into the start of the real mode memory (16Kb is where
 we put the real mode code we execute for issuing interrupts).
 
-NOTE:   The memory is *always* in little endian format, son on non-x86
-        systems you will need to do endian translations to access this
-        memory.
+NOTE:  The memory is *always* in little endian format, son on non-x86
+       systems you will need to do endian translations to access this
+       memory.
 ****************************************************************************/
 void *X86API BE_getVESABuf(uint * len, uint * rseg, uint * roff)
 {
@@ -231,10 +231,10 @@ void X86API BE_exit(void)
 
 /****************************************************************************
 PARAMETERS:
-seg     - Segment of code to call
-off     - Offset of code to call
-regs    - Real mode registers to load
-sregs   - Real mode segment registers to load
+seg    - Segment of code to call
+off    - Offset of code to call
+regs   - Real mode registers to load
+sregs  - Real mode segment registers to load
 
 REMARKS:
 This functions calls a real mode far function at the specified address,
@@ -284,9 +284,9 @@ void X86API BE_callRealMode(uint seg, uint off, RMREGS * regs, RMSREGS * sregs)
 
 /****************************************************************************
 PARAMETERS:
-intno   - Interrupt number to execute
-in      - Real mode registers to load
-out     - Place to store resulting real mode registers
+intno  - Interrupt number to execute
+in     - Real mode registers to load
+out    - Place to store resulting real mode registers
 
 REMARKS:
 This functions calls a real mode interrupt function at the specified address,
@@ -323,10 +323,10 @@ int X86API BE_int86(int intno, RMREGS * in, RMREGS * out)
 
 /****************************************************************************
 PARAMETERS:
-intno   - Interrupt number to execute
-in      - Real mode registers to load
-out     - Place to store resulting real mode registers
-sregs   - Real mode segment registers to load
+intno  - Interrupt number to execute
+in     - Real mode registers to load
+out    - Place to store resulting real mode registers
+sregs  - Real mode segment registers to load
 
 REMARKS:
 This functions calls a real mode interrupt function at the specified address,
index 3265ac15cb6df3fe6000f7d34ad1c6d9a98048c9..e85e656cb45f7c2b810dc91ea0d918dcc81c8f76 100644 (file)
@@ -1,12 +1,12 @@
 /****************************************************************************
 *
-*                        BIOS emulator and interface
-*                      to Realmode X86 Emulator Library
+*                       BIOS emulator and interface
+*                     to Realmode X86 Emulator Library
 *
 *  Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
 *  Jason Jin <Jason.jin@freescale.com>
 *
-*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*              Copyright (C) 1996-1999 SciTech Software, Inc.
 *
 *  ========================================================================
 *
@@ -16,7 +16,7 @@
 *  both that copyright notice and this permission notice appear in
 *  supporting documentation, and that the name of the authors not be used
 *  in advertising or publicity pertaining to distribution of the software
-*  without specific, written prior permission.  The authors makes no
+*  without specific, written prior permission. The authors makes no
 *  representations about the suitability of this software for any purpose.
 *  It is provided "as is" without express or implied warranty.
 *
 *
 *  ========================================================================
 *
-* Language:     ANSI C
-* Environment:  Any
-* Developer:    Kendall Bennett
+* Language:    ANSI C
+* Environment: Any
+* Developer:   Kendall Bennett
 *
-* Description:  Internal header file for the BIOS emulator library.
+* Description: Internal header file for the BIOS emulator library.
 *
-*              Jason ported this file to u-boot, Added some architecture
-*              related Macro.
+*              Jason ported this file to u-boot, Added some architecture
+*              related Macro.
 *
 ****************************************************************************/
 
 /*---------------------- Macros and type definitions ----------------------*/
 
 #ifdef DEBUG
-#define DB(x)   x
+#define DB(x)  x
 #else
-#define DB(x)   do{}while(0);
+#define DB(x)  do{}while(0);
 #endif
 
-#define BIOS_SEG        0xfff0
+#define BIOS_SEG       0xfff0
 extern X86EMU_sysEnv _X86EMU_env;
-#define M               _X86EMU_env
+#define M              _X86EMU_env
 
 /* Macros to read and write values to x86 emulator memory. Memory is always
  * considered to be little endian, so we use macros to do endian swapping
@@ -64,21 +64,21 @@ extern X86EMU_sysEnv _X86EMU_env;
  */
 
 #ifdef __BIG_ENDIAN__
-#define readb_le(base)      *((u8*)(base))
-#define readw_le(base)      ((u16)readb_le(base) | ((u16)readb_le((base) + 1) << 8))
-#define readl_le(base)      ((u32)readb_le((base) + 0) | ((u32)readb_le((base) + 1) << 8) | \
-                            ((u32)readb_le((base) + 2) << 16) | ((u32)readb_le((base) + 3) << 24))
+#define readb_le(base)     *((u8*)(base))
+#define readw_le(base)     ((u16)readb_le(base) | ((u16)readb_le((base) + 1) << 8))
+#define readl_le(base)     ((u32)readb_le((base) + 0) | ((u32)readb_le((base) + 1) << 8) | \
+                           ((u32)readb_le((base) + 2) << 16) | ((u32)readb_le((base) + 3) << 24))
 #define writeb_le(base, v)  *((u8*)(base)) = (v)
-#define writew_le(base, v)  writeb_le(base + 0, (v >> 0) & 0xff),       \
-                            writeb_le(base + 1, (v >> 8) & 0xff)
-#define writel_le(base, v)  writeb_le(base + 0, (v >> 0) & 0xff),       \
-                            writeb_le(base + 1, (v >> 8) & 0xff),       \
-                            writeb_le(base + 2, (v >> 16) & 0xff),      \
-                            writeb_le(base + 3, (v >> 24) & 0xff)
+#define writew_le(base, v)  writeb_le(base + 0, (v >> 0) & 0xff),      \
+                           writeb_le(base + 1, (v >> 8) & 0xff)
+#define writel_le(base, v)  writeb_le(base + 0, (v >> 0) & 0xff),      \
+                           writeb_le(base + 1, (v >> 8) & 0xff),       \
+                           writeb_le(base + 2, (v >> 16) & 0xff),      \
+                           writeb_le(base + 3, (v >> 24) & 0xff)
 #else
-#define readb_le(base)      *((u8*)(base))
-#define readw_le(base)      *((u16*)(base))
-#define readl_le(base)      *((u32*)(base))
+#define readb_le(base)     *((u8*)(base))
+#define readw_le(base)     *((u16*)(base))
+#define readl_le(base)     *((u32*)(base))
 #define writeb_le(base, v)  *((u8*)(base)) = (v)
 #define writew_le(base, v)  *((u16*)(base)) = (v)
 #define writel_le(base, v)  *((u32*)(base)) = (v)
@@ -118,8 +118,8 @@ HEADER:
 biosemu.h
 
 MEMBERS:
-type        - Type of port access (1 = byte, 2 = word, 3 = dword)
-defVal      - Default power on value
+type       - Type of port access (1 = byte, 2 = word, 3 = dword)
+defVal     - Default power on value
 finalVal    - Final value
 ****************************************************************************/
 typedef struct {
index 35e1e9a92fb7a1677a4d0340deef529a83827806..268c9d391e239a1ebdc4a61d369fa287d9722d96 100644 (file)
@@ -1,10 +1,10 @@
 /****************************************************************************
 *
-*                       Realmode X86 Emulator Library
+*                      Realmode X86 Emulator Library
 *
-*               Copyright (C) 1991-2004 SciTech Software, Inc.
-*                    Copyright (C) David Mosberger-Tang
-*                      Copyright (C) 1999 Egbert Eich
+*              Copyright (C) 1991-2004 SciTech Software, Inc.
+*                   Copyright (C) David Mosberger-Tang
+*                     Copyright (C) 1999 Egbert Eich
 *
 *  ========================================================================
 *
@@ -14,7 +14,7 @@
 *  both that copyright notice and this permission notice appear in
 *  supporting documentation, and that the name of the authors not be used
 *  in advertising or publicity pertaining to distribution of the software
-*  without specific, written prior permission.  The authors makes no
+*  without specific, written prior permission. The authors makes no
 *  representations about the suitability of this software for any purpose.
 *  It is provided "as is" without express or implied warranty.
 *
 *
 *  ========================================================================
 *
-* Language:     ANSI C
-* Environment:  Any
-* Developer:    Kendall Bennett
+* Language:    ANSI C
+* Environment: Any
+* Developer:   Kendall Bennett
 *
-* Description:  Header file for debug definitions.
+* Description: Header file for debug definitions.
 *
 ****************************************************************************/
 
 
 /* checks to be enabled for "runtime" */
 
-#define CHECK_IP_FETCH_F                0x1
-#define CHECK_SP_ACCESS_F               0x2
-#define CHECK_MEM_ACCESS_F              0x4    /*using regular linear pointer */
-#define CHECK_DATA_ACCESS_F             0x8    /*using segment:offset */
+#define CHECK_IP_FETCH_F               0x1
+#define CHECK_SP_ACCESS_F              0x2
+#define CHECK_MEM_ACCESS_F             0x4     /*using regular linear pointer */
+#define CHECK_DATA_ACCESS_F            0x8     /*using segment:offset */
 
 #ifdef DEBUG
-# define CHECK_IP_FETCH()               (M.x86.check & CHECK_IP_FETCH_F)
-# define CHECK_SP_ACCESS()              (M.x86.check & CHECK_SP_ACCESS_F)
-# define CHECK_MEM_ACCESS()             (M.x86.check & CHECK_MEM_ACCESS_F)
-# define CHECK_DATA_ACCESS()            (M.x86.check & CHECK_DATA_ACCESS_F)
+# define CHECK_IP_FETCH()              (M.x86.check & CHECK_IP_FETCH_F)
+# define CHECK_SP_ACCESS()             (M.x86.check & CHECK_SP_ACCESS_F)
+# define CHECK_MEM_ACCESS()            (M.x86.check & CHECK_MEM_ACCESS_F)
+# define CHECK_DATA_ACCESS()           (M.x86.check & CHECK_DATA_ACCESS_F)
 #else
 # define CHECK_IP_FETCH()
 # define CHECK_SP_ACCESS()
 #endif
 
 #ifdef DEBUG
-# define DEBUG_INSTRUMENT()     (M.x86.debug & DEBUG_INSTRUMENT_F)
-# define DEBUG_DECODE()         (M.x86.debug & DEBUG_DECODE_F)
-# define DEBUG_TRACE()          (M.x86.debug & DEBUG_TRACE_F)
-# define DEBUG_STEP()           (M.x86.debug & DEBUG_STEP_F)
-# define DEBUG_DISASSEMBLE()    (M.x86.debug & DEBUG_DISASSEMBLE_F)
-# define DEBUG_BREAK()          (M.x86.debug & DEBUG_BREAK_F)
-# define DEBUG_SVC()            (M.x86.debug & DEBUG_SVC_F)
-# define DEBUG_SAVE_IP_CS()     (M.x86.debug & DEBUG_SAVE_CS_IP)
-
-# define DEBUG_FS()             (M.x86.debug & DEBUG_FS_F)
-# define DEBUG_PROC()           (M.x86.debug & DEBUG_PROC_F)
-# define DEBUG_SYSINT()         (M.x86.debug & DEBUG_SYSINT_F)
-# define DEBUG_TRACECALL()      (M.x86.debug & DEBUG_TRACECALL_F)
-# define DEBUG_TRACECALLREGS()  (M.x86.debug & DEBUG_TRACECALL_REGS_F)
-# define DEBUG_SYS()            (M.x86.debug & DEBUG_SYS_F)
-# define DEBUG_MEM_TRACE()      (M.x86.debug & DEBUG_MEM_TRACE_F)
-# define DEBUG_IO_TRACE()       (M.x86.debug & DEBUG_IO_TRACE_F)
+# define DEBUG_INSTRUMENT()    (M.x86.debug & DEBUG_INSTRUMENT_F)
+# define DEBUG_DECODE()                (M.x86.debug & DEBUG_DECODE_F)
+# define DEBUG_TRACE()         (M.x86.debug & DEBUG_TRACE_F)
+# define DEBUG_STEP()          (M.x86.debug & DEBUG_STEP_F)
+# define DEBUG_DISASSEMBLE()   (M.x86.debug & DEBUG_DISASSEMBLE_F)
+# define DEBUG_BREAK()         (M.x86.debug & DEBUG_BREAK_F)
+# define DEBUG_SVC()           (M.x86.debug & DEBUG_SVC_F)
+# define DEBUG_SAVE_IP_CS()    (M.x86.debug & DEBUG_SAVE_CS_IP)
+
+# define DEBUG_FS()            (M.x86.debug & DEBUG_FS_F)
+# define DEBUG_PROC()          (M.x86.debug & DEBUG_PROC_F)
+# define DEBUG_SYSINT()                (M.x86.debug & DEBUG_SYSINT_F)
+# define DEBUG_TRACECALL()     (M.x86.debug & DEBUG_TRACECALL_F)
+# define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F)
+# define DEBUG_SYS()           (M.x86.debug & DEBUG_SYS_F)
+# define DEBUG_MEM_TRACE()     (M.x86.debug & DEBUG_MEM_TRACE_F)
+# define DEBUG_IO_TRACE()      (M.x86.debug & DEBUG_IO_TRACE_F)
 # define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F)
 #else
-# define DEBUG_INSTRUMENT()     0
-# define DEBUG_DECODE()         0
-# define DEBUG_TRACE()          0
-# define DEBUG_STEP()           0
-# define DEBUG_DISASSEMBLE()    0
-# define DEBUG_BREAK()          0
-# define DEBUG_SVC()            0
-# define DEBUG_SAVE_IP_CS()     0
-# define DEBUG_FS()             0
-# define DEBUG_PROC()           0
-# define DEBUG_SYSINT()         0
-# define DEBUG_TRACECALL()      0
-# define DEBUG_TRACECALLREGS()  0
-# define DEBUG_SYS()            0
-# define DEBUG_MEM_TRACE()      0
-# define DEBUG_IO_TRACE()       0
+# define DEBUG_INSTRUMENT()    0
+# define DEBUG_DECODE()                0
+# define DEBUG_TRACE()         0
+# define DEBUG_STEP()          0
+# define DEBUG_DISASSEMBLE()   0
+# define DEBUG_BREAK()         0
+# define DEBUG_SVC()           0
+# define DEBUG_SAVE_IP_CS()    0
+# define DEBUG_FS()            0
+# define DEBUG_PROC()          0
+# define DEBUG_SYSINT()                0
+# define DEBUG_TRACECALL()     0
+# define DEBUG_TRACECALLREGS() 0
+# define DEBUG_SYS()           0
+# define DEBUG_MEM_TRACE()     0
+# define DEBUG_IO_TRACE()      0
 # define DEBUG_DECODE_NOPRINT() 0
 #endif
 
 #ifdef DEBUG
 
-# define DECODE_PRINTF(x)       if (DEBUG_DECODE()) \
-                                    x86emu_decode_printf(x)
-# define DECODE_PRINTF2(x,y)    if (DEBUG_DECODE()) \
-                                    x86emu_decode_printf2(x,y)
+# define DECODE_PRINTF(x)      if (DEBUG_DECODE()) \
+                                   x86emu_decode_printf(x)
+# define DECODE_PRINTF2(x,y)   if (DEBUG_DECODE()) \
+                                   x86emu_decode_printf2(x,y)
 
 /*
  * The following allow us to look at the bytes of an instruction.  The
  * the decoding process.  The SAVE_IP_CS is called initially when the
  * major opcode of the instruction is accessed.
  */
-#define INC_DECODED_INST_LEN(x)                     \
-    if (DEBUG_DECODE())                             \
-        x86emu_inc_decoded_inst_len(x)
+#define INC_DECODED_INST_LEN(x)                            \
+    if (DEBUG_DECODE())                                    \
+       x86emu_inc_decoded_inst_len(x)
 
-#define SAVE_IP_CS(x,y)                                         \
+#define SAVE_IP_CS(x,y)                                                \
     if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \
-              | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \
-        M.x86.saved_cs = x;                                     \
-        M.x86.saved_ip = y;                                     \
+             | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \
+       M.x86.saved_cs = x;                                     \
+       M.x86.saved_ip = y;                                     \
     }
 #else
 # define INC_DECODED_INST_LEN(x)
 #endif
 
 #ifdef DEBUG
-#define TRACE_REGS()                                        \
-    if (DEBUG_DISASSEMBLE()) {                              \
-        x86emu_just_disassemble();                          \
-        goto EndOfTheInstructionProcedure;                  \
-    }                                                       \
+#define TRACE_REGS()                                       \
+    if (DEBUG_DISASSEMBLE()) {                             \
+       x86emu_just_disassemble();                          \
+       goto EndOfTheInstructionProcedure;                  \
+    }                                                      \
     if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs()
 #else
 # define TRACE_REGS()
 #endif
 
 #ifdef DEBUG
-# define SINGLE_STEP()      if (DEBUG_STEP()) x86emu_single_step()
+# define SINGLE_STEP()     if (DEBUG_STEP()) x86emu_single_step()
 #else
 # define SINGLE_STEP()
 #endif
 
 #define TRACE_AND_STEP()    \
-    TRACE_REGS();           \
+    TRACE_REGS();          \
     SINGLE_STEP()
 
 #ifdef DEBUG
 # define START_OF_INSTR()
-# define END_OF_INSTR()     EndOfTheInstructionProcedure: x86emu_end_instr();
+# define END_OF_INSTR()            EndOfTheInstructionProcedure: x86emu_end_instr();
 # define END_OF_INSTR_NO_TRACE()    x86emu_end_instr();
 #else
 # define START_OF_INSTR()
 #endif
 
 #ifdef DEBUG
-# define  CALL_TRACE(u,v,w,x,s)                                 \
-    if (DEBUG_TRACECALLREGS())                                  \
-        x86emu_dump_regs();                                     \
-    if (DEBUG_TRACECALL())                                      \
-        printk("%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x);
-# define RETURN_TRACE(n,u,v)                                    \
-    if (DEBUG_TRACECALLREGS())                                  \
-        x86emu_dump_regs();                                     \
-    if (DEBUG_TRACECALL())                                      \
-        printk("%04x:%04x: %s\n",u,v,n);
+# define  CALL_TRACE(u,v,w,x,s)                                        \
+    if (DEBUG_TRACECALLREGS())                                 \
+       x86emu_dump_regs();                                     \
+    if (DEBUG_TRACECALL())                                     \
+       printk("%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x);
+# define RETURN_TRACE(n,u,v)                                   \
+    if (DEBUG_TRACECALLREGS())                                 \
+       x86emu_dump_regs();                                     \
+    if (DEBUG_TRACECALL())                                     \
+       printk("%04x:%04x: %s\n",u,v,n);
 #else
 # define CALL_TRACE(u,v,w,x,s)
 # define RETURN_TRACE(n,u,v)
 #endif
 
 #ifdef DEBUG
-#define DB(x)   x
+#define DB(x)  x
 #else
 #define DB(x)
 #endif
 
 /*-------------------------- Function Prototypes --------------------------*/
 
-#ifdef  __cplusplus
+#ifdef __cplusplus
 extern "C" {                   /* Use "C" linkage when in C++ mode */
 #endif
 
@@ -203,7 +203,7 @@ extern "C" {                        /* Use "C" linkage when in C++ mode */
        extern void x86emu_check_mem_access(u32 p);
        extern void x86emu_check_data_access(uint s, uint o);
 
-#ifdef  __cplusplus
-}                              /* End of "C" linkage for C++       */
+#ifdef __cplusplus
+}                              /* End of "C" linkage for C++       */
 #endif
 #endif                         /* __X86EMU_DEBUG_H */
index 0ea825d3c1a74796a4869c18829236514c2173f6..2291e8488a5afbd9aba3e556cf43584cf2000e4e 100644 (file)
@@ -139,4 +139,3 @@ u32     pop_long (void);
 #endif
 
 #endif /* __X86EMU_PRIM_OPS_H */
-
index 9dbed503175e9572bed334f283b0e84618cc9e98..a7fedd2f6ca1caa7d56de1cf54bec54300bdb872 100644 (file)
@@ -1,10 +1,10 @@
 /****************************************************************************
 *
-*                       Realmode X86 Emulator Library
+*                      Realmode X86 Emulator Library
 *
-*               Copyright (C) 1991-2004 SciTech Software, Inc.
-*                    Copyright (C) David Mosberger-Tang
-*                      Copyright (C) 1999 Egbert Eich
+*              Copyright (C) 1991-2004 SciTech Software, Inc.
+*                   Copyright (C) David Mosberger-Tang
+*                     Copyright (C) 1999 Egbert Eich
 *
 *  ========================================================================
 *
@@ -14,7 +14,7 @@
 *  both that copyright notice and this permission notice appear in
 *  supporting documentation, and that the name of the authors not be used
 *  in advertising or publicity pertaining to distribution of the software
-*  without specific, written prior permission.  The authors makes no
+*  without specific, written prior permission. The authors makes no
 *  representations about the suitability of this software for any purpose.
 *  It is provided "as is" without express or implied warranty.
 *
 *
 *  ========================================================================
 *
-* Language:     ANSI C
-* Environment:  Any
-* Developer:    Kendall Bennett
+* Language:    ANSI C
+* Environment: Any
+* Developer:   Kendall Bennett
 *
-* Description:  Header file for x86 register definitions.
+* Description: Header file for x86 register definitions.
 *
 ****************************************************************************/
 
  * EAX & 0xff  === AL
  * EAX & 0xffff == AX
  *
- * etc.  The result is that alot of the calculations can then be
+ * etc.         The result is that alot of the calculations can then be
  * done using the native instruction set fully.
  */
 
-#ifdef  __BIG_ENDIAN__
+#ifdef __BIG_ENDIAN__
 
 typedef struct {
        u32 e_reg;
@@ -178,7 +178,7 @@ struct i386_segment_regs {
 /* flag conditions   */
 #define FB_CF 0x0001           /* CARRY flag  */
 #define FB_PF 0x0004           /* PARITY flag */
-#define FB_AF 0x0010           /* AUX  flag   */
+#define FB_AF 0x0010           /* AUX  flag   */
 #define FB_ZF 0x0040           /* ZERO flag   */
 #define FB_SF 0x0080           /* SIGN flag   */
 #define FB_TF 0x0100           /* TRAP flag   */
@@ -199,7 +199,7 @@ struct i386_segment_regs {
 
 #define F_CF 0x0001            /* CARRY flag  */
 #define F_PF 0x0004            /* PARITY flag */
-#define F_AF 0x0010            /* AUX  flag   */
+#define F_AF 0x0010            /* AUX  flag   */
 #define F_ZF 0x0040            /* ZERO flag   */
 #define F_SF 0x0080            /* SIGN flag   */
 #define F_TF 0x0100            /* TRAP flag   */
@@ -207,60 +207,60 @@ struct i386_segment_regs {
 #define F_DF 0x0400            /* DIR flag    */
 #define F_OF 0x0800            /* OVERFLOW flag */
 
-#define TOGGLE_FLAG(flag)       (M.x86.R_FLG ^= (flag))
-#define SET_FLAG(flag)          (M.x86.R_FLG |= (flag))
-#define CLEAR_FLAG(flag)        (M.x86.R_FLG &= ~(flag))
-#define ACCESS_FLAG(flag)       (M.x86.R_FLG & (flag))
-#define CLEARALL_FLAG(m)        (M.x86.R_FLG = 0)
+#define TOGGLE_FLAG(flag)      (M.x86.R_FLG ^= (flag))
+#define SET_FLAG(flag)         (M.x86.R_FLG |= (flag))
+#define CLEAR_FLAG(flag)       (M.x86.R_FLG &= ~(flag))
+#define ACCESS_FLAG(flag)      (M.x86.R_FLG & (flag))
+#define CLEARALL_FLAG(m)       (M.x86.R_FLG = 0)
 
 #define CONDITIONAL_SET_FLAG(COND,FLAG) \
   if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG)
 
-#define F_PF_CALC 0x010000     /* PARITY flag has been calced    */
-#define F_ZF_CALC 0x020000     /* ZERO flag has been calced      */
-#define F_SF_CALC 0x040000     /* SIGN flag has been calced      */
+#define F_PF_CALC 0x010000     /* PARITY flag has been calced    */
+#define F_ZF_CALC 0x020000     /* ZERO flag has been calced      */
+#define F_SF_CALC 0x040000     /* SIGN flag has been calced      */
 
-#define F_ALL_CALC      0xff0000       /* All have been calced   */
+#define F_ALL_CALC     0xff0000        /* All have been calced   */
 
 /*
  * Emulator machine state.
  * Segment usage control.
  */
-#define SYSMODE_SEG_DS_SS       0x00000001
-#define SYSMODE_SEGOVR_CS       0x00000002
-#define SYSMODE_SEGOVR_DS       0x00000004
-#define SYSMODE_SEGOVR_ES       0x00000008
-#define SYSMODE_SEGOVR_FS       0x00000010
-#define SYSMODE_SEGOVR_GS       0x00000020
-#define SYSMODE_SEGOVR_SS       0x00000040
-#define SYSMODE_PREFIX_REPE     0x00000080
-#define SYSMODE_PREFIX_REPNE    0x00000100
-#define SYSMODE_PREFIX_DATA     0x00000200
-#define SYSMODE_PREFIX_ADDR     0x00000400
-#define SYSMODE_INTR_PENDING    0x10000000
-#define SYSMODE_EXTRN_INTR      0x20000000
-#define SYSMODE_HALTED          0x40000000
-
-#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS      | \
-                         SYSMODE_SEGOVR_CS      | \
-                         SYSMODE_SEGOVR_DS      | \
-                         SYSMODE_SEGOVR_ES      | \
-                         SYSMODE_SEGOVR_FS      | \
-                         SYSMODE_SEGOVR_GS      | \
-                         SYSMODE_SEGOVR_SS)
-#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS      | \
-                         SYSMODE_SEGOVR_CS      | \
-                         SYSMODE_SEGOVR_DS      | \
-                         SYSMODE_SEGOVR_ES      | \
-                         SYSMODE_SEGOVR_FS      | \
-                         SYSMODE_SEGOVR_GS      | \
-                         SYSMODE_SEGOVR_SS      | \
-                         SYSMODE_PREFIX_DATA    | \
-                         SYSMODE_PREFIX_ADDR)
-
-#define  INTR_SYNCH           0x1
-#define  INTR_ASYNCH          0x2
-#define  INTR_HALTED          0x4
+#define SYSMODE_SEG_DS_SS      0x00000001
+#define SYSMODE_SEGOVR_CS      0x00000002
+#define SYSMODE_SEGOVR_DS      0x00000004
+#define SYSMODE_SEGOVR_ES      0x00000008
+#define SYSMODE_SEGOVR_FS      0x00000010
+#define SYSMODE_SEGOVR_GS      0x00000020
+#define SYSMODE_SEGOVR_SS      0x00000040
+#define SYSMODE_PREFIX_REPE    0x00000080
+#define SYSMODE_PREFIX_REPNE   0x00000100
+#define SYSMODE_PREFIX_DATA    0x00000200
+#define SYSMODE_PREFIX_ADDR    0x00000400
+#define SYSMODE_INTR_PENDING   0x10000000
+#define SYSMODE_EXTRN_INTR     0x20000000
+#define SYSMODE_HALTED         0x40000000
+
+#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS     | \
+                        SYSMODE_SEGOVR_CS      | \
+                        SYSMODE_SEGOVR_DS      | \
+                        SYSMODE_SEGOVR_ES      | \
+                        SYSMODE_SEGOVR_FS      | \
+                        SYSMODE_SEGOVR_GS      | \
+                        SYSMODE_SEGOVR_SS)
+#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS     | \
+                        SYSMODE_SEGOVR_CS      | \
+                        SYSMODE_SEGOVR_DS      | \
+                        SYSMODE_SEGOVR_ES      | \
+                        SYSMODE_SEGOVR_FS      | \
+                        SYSMODE_SEGOVR_GS      | \
+                        SYSMODE_SEGOVR_SS      | \
+                        SYSMODE_PREFIX_DATA    | \
+                        SYSMODE_PREFIX_ADDR)
+
+#define         INTR_SYNCH           0x1
+#define         INTR_ASYNCH          0x2
+#define         INTR_HALTED          0x4
 
 typedef struct {
        struct i386_general_regs gen;
@@ -268,15 +268,15 @@ typedef struct {
        struct i386_segment_regs seg;
        /*
         * MODE contains information on:
-        *  REPE prefix             2 bits  repe,repne
-        *  SEGMENT overrides       5 bits  normal,DS,SS,CS,ES
-        *  Delayed flag set        3 bits  (zero, signed, parity)
-        *  reserved                6 bits
-        *  interrupt #             8 bits  instruction raised interrupt
-        *  BIOS video segregs      4 bits
-        *  Interrupt Pending       1 bits
-        *  Extern interrupt        1 bits
-        *  Halted                  1 bits
+        *  REPE prefix             2 bits  repe,repne
+        *  SEGMENT overrides       5 bits  normal,DS,SS,CS,ES
+        *  Delayed flag set        3 bits  (zero, signed, parity)
+        *  reserved                6 bits
+        *  interrupt #             8 bits  instruction raised interrupt
+        *  BIOS video segregs      4 bits
+        *  Interrupt Pending       1 bits
+        *  Extern interrupt        1 bits
+        *  Halted                  1 bits
         */
        long mode;
        u8 intno;
@@ -288,7 +288,7 @@ typedef struct {
        u16 saved_cs;
        int enc_pos;
        int enc_str_pos;
-       char decode_buf[32];    /* encoded byte stream  */
+       char decode_buf[32];    /* encoded byte stream  */
        char decoded_buf[256];  /* disassembled strings */
 #endif
 } X86EMU_regs;
@@ -298,9 +298,9 @@ REMARKS:
 Structure maintaining the emulator machine state.
 
 MEMBERS:
-x86             - X86 registers
-mem_base        - Base real mode memory for the emulator
-mem_size        - Size of the real mode memory block for the emulator
+x86            - X86 registers
+mem_base       - Base real mode memory for the emulator
+mem_size       - Size of the real mode memory block for the emulator
 ****************************************************************************/
 #undef x86
 typedef struct {
@@ -314,7 +314,7 @@ typedef struct {
 
 /*----------------------------- Global Variables --------------------------*/
 
-#ifdef  __cplusplus
+#ifdef __cplusplus
 extern "C" {                   /* Use "C" linkage when in C++ mode */
 #endif
 
@@ -324,7 +324,7 @@ extern "C" {                        /* Use "C" linkage when in C++ mode */
  */
 
        extern X86EMU_sysEnv _X86EMU_env;
-#define   M             _X86EMU_env
+#define          M             _X86EMU_env
 
 /*-------------------------- Function Prototypes --------------------------*/
 
@@ -334,7 +334,7 @@ extern "C" {                        /* Use "C" linkage when in C++ mode */
        void printk(const char *fmt, ...);
 #endif
 
-#ifdef  __cplusplus
-}                              /* End of "C" linkage for C++       */
+#ifdef __cplusplus
+}                              /* End of "C" linkage for C++       */
 #endif
 #endif                         /* __X86EMU_REGS_H */
index b4dbb20797d6a60b83a771d061d0418c7ccdd249..1e2dcfe4b2b5e90ce10d76a30e9d09ea72ad52a5 100644 (file)
@@ -1,10 +1,10 @@
 /****************************************************************************
 *
-*                       Realmode X86 Emulator Library
+*                      Realmode X86 Emulator Library
 *
-*               Copyright (C) 1991-2004 SciTech Software, Inc.
-*                    Copyright (C) David Mosberger-Tang
-*                      Copyright (C) 1999 Egbert Eich
+*              Copyright (C) 1991-2004 SciTech Software, Inc.
+*                   Copyright (C) David Mosberger-Tang
+*                     Copyright (C) 1999 Egbert Eich
 *
 *  ========================================================================
 *
@@ -14,7 +14,7 @@
 *  both that copyright notice and this permission notice appear in
 *  supporting documentation, and that the name of the authors not be used
 *  in advertising or publicity pertaining to distribution of the software
-*  without specific, written prior permission.  The authors makes no
+*  without specific, written prior permission. The authors makes no
 *  representations about the suitability of this software for any purpose.
 *  It is provided "as is" without express or implied warranty.
 *
 *
 *  ========================================================================
 *
-* Language:     ANSI C
-* Environment:  Any
-* Developer:    Kendall Bennett
+* Language:    ANSI C
+* Environment: Any
+* Developer:   Kendall Bennett
 *
-* Description:  This file includes subroutines which are related to
-*               instruction decoding and accessess of immediate data via IP.  etc.
+* Description: This file includes subroutines which are related to
+*              instruction decoding and accessess of immediate data via IP.  etc.
 *
 ****************************************************************************/
 
@@ -47,22 +47,22 @@ Handles any pending asychronous interrupts.
 ****************************************************************************/
 static void x86emu_intr_handle(void)
 {
-    u8  intno;
+    u8 intno;
 
     if (M.x86.intr & INTR_SYNCH) {
-        intno = M.x86.intno;
-        if (_X86EMU_intrTab[intno]) {
-            (*_X86EMU_intrTab[intno])(intno);
-        } else {
-            push_word((u16)M.x86.R_FLG);
-            CLEAR_FLAG(F_IF);
-            CLEAR_FLAG(F_TF);
-            push_word(M.x86.R_CS);
-            M.x86.R_CS = mem_access_word(intno * 4 + 2);
-            push_word(M.x86.R_IP);
-            M.x86.R_IP = mem_access_word(intno * 4);
-            M.x86.intr = 0;
-        }
+       intno = M.x86.intno;
+       if (_X86EMU_intrTab[intno]) {
+           (*_X86EMU_intrTab[intno])(intno);
+       } else {
+           push_word((u16)M.x86.R_FLG);
+           CLEAR_FLAG(F_IF);
+           CLEAR_FLAG(F_TF);
+           push_word(M.x86.R_CS);
+           M.x86.R_CS = mem_access_word(intno * 4 + 2);
+           push_word(M.x86.R_IP);
+           M.x86.R_IP = mem_access_word(intno * 4);
+           M.x86.intr = 0;
+       }
     }
 }
 
@@ -95,34 +95,34 @@ void X86EMU_exec(void)
     DB(x86emu_end_instr();)
 
     for (;;) {
-DB(     if (CHECK_IP_FETCH())
-            x86emu_check_ip_access();)
-        /* If debugging, save the IP and CS values. */
-        SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP);
-        INC_DECODED_INST_LEN(1);
-        if (M.x86.intr) {
-            if (M.x86.intr & INTR_HALTED) {
-DB(             if (M.x86.R_SP != 0) {
-                    printk("halted\n");
-                    X86EMU_trace_regs();
-                    }
-                else {
-                    if (M.x86.debug)
-                        printk("Service completed successfully\n");
-                    })
-                return;
-            }
-            if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) ||
-                !ACCESS_FLAG(F_IF)) {
-                x86emu_intr_handle();
-            }
-        }
-        op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++));
-        (*x86emu_optab[op1])(op1);
-        if (M.x86.debug & DEBUG_EXIT) {
-            M.x86.debug &= ~DEBUG_EXIT;
-            return;
-        }
+DB(    if (CHECK_IP_FETCH())
+           x86emu_check_ip_access();)
+       /* If debugging, save the IP and CS values. */
+       SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP);
+       INC_DECODED_INST_LEN(1);
+       if (M.x86.intr) {
+           if (M.x86.intr & INTR_HALTED) {
+DB(            if (M.x86.R_SP != 0) {
+                   printk("halted\n");
+                   X86EMU_trace_regs();
+                   }
+               else {
+                   if (M.x86.debug)
+                       printk("Service completed successfully\n");
+                   })
+               return;
+           }
+           if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) ||
+               !ACCESS_FLAG(F_IF)) {
+               x86emu_intr_handle();
+           }
+       }
+       op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++));
+       (*x86emu_optab[op1])(op1);
+       if (M.x86.debug & DEBUG_EXIT) {
+           M.x86.debug &= ~DEBUG_EXIT;
+           return;
+       }
     }
 }
 
@@ -137,9 +137,9 @@ void X86EMU_halt_sys(void)
 
 /****************************************************************************
 PARAMETERS:
-mod     - Mod value from decoded byte
-regh    - Reg h value from decoded byte
-regl    - Reg l value from decoded byte
+mod    - Mod value from decoded byte
+regh   - Reg h value from decoded byte
+regl   - Reg l value from decoded byte
 
 REMARKS:
 Raise the specified interrupt to be handled before the execution of the
@@ -155,7 +155,7 @@ void fetch_decode_modrm(
     int fetched;
 
 DB( if (CHECK_IP_FETCH())
-        x86emu_check_ip_access();)
+       x86emu_check_ip_access();)
     fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++));
     INC_DECODED_INST_LEN(1);
     *mod  = (fetched >> 6) & 0x03;
@@ -178,7 +178,7 @@ u8 fetch_byte_imm(void)
     u8 fetched;
 
 DB( if (CHECK_IP_FETCH())
-        x86emu_check_ip_access();)
+       x86emu_check_ip_access();)
     fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++));
     INC_DECODED_INST_LEN(1);
     return fetched;
@@ -199,7 +199,7 @@ u16 fetch_word_imm(void)
     u16 fetched;
 
 DB( if (CHECK_IP_FETCH())
-        x86emu_check_ip_access();)
+       x86emu_check_ip_access();)
     fetched = (*sys_rdw)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP));
     M.x86.R_IP += 2;
     INC_DECODED_INST_LEN(2);
@@ -221,7 +221,7 @@ u32 fetch_long_imm(void)
     u32 fetched;
 
 DB( if (CHECK_IP_FETCH())
-        x86emu_check_ip_access();)
+       x86emu_check_ip_access();)
     fetched = (*sys_rdl)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP));
     M.x86.R_IP += 4;
     INC_DECODED_INST_LEN(4);
@@ -261,39 +261,39 @@ _INLINE u32 get_data_segment(void)
 {
 #define GET_SEGMENT(segment)
     switch (M.x86.mode & SYSMODE_SEGMASK) {
-      case 0:                   /* default case: use ds register */
+      case 0:                  /* default case: use ds register */
       case SYSMODE_SEGOVR_DS:
       case SYSMODE_SEGOVR_DS | SYSMODE_SEG_DS_SS:
-        return  M.x86.R_DS;
-      case SYSMODE_SEG_DS_SS:   /* non-overridden, use ss register */
-        return  M.x86.R_SS;
+       return  M.x86.R_DS;
+      case SYSMODE_SEG_DS_SS:  /* non-overridden, use ss register */
+       return  M.x86.R_SS;
       case SYSMODE_SEGOVR_CS:
       case SYSMODE_SEGOVR_CS | SYSMODE_SEG_DS_SS:
-        return  M.x86.R_CS;
+       return  M.x86.R_CS;
       case SYSMODE_SEGOVR_ES:
       case SYSMODE_SEGOVR_ES | SYSMODE_SEG_DS_SS:
-        return  M.x86.R_ES;
+       return  M.x86.R_ES;
       case SYSMODE_SEGOVR_FS:
       case SYSMODE_SEGOVR_FS | SYSMODE_SEG_DS_SS:
-        return  M.x86.R_FS;
+       return  M.x86.R_FS;
       case SYSMODE_SEGOVR_GS:
       case SYSMODE_SEGOVR_GS | SYSMODE_SEG_DS_SS:
-        return  M.x86.R_GS;
+       return  M.x86.R_GS;
       case SYSMODE_SEGOVR_SS:
       case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS:
-        return  M.x86.R_SS;
+       return  M.x86.R_SS;
       default:
-#ifdef  DEBUG
-        printk("error: should not happen:  multiple overrides.\n");
+#ifdef DEBUG
+       printk("error: should not happen:  multiple overrides.\n");
 #endif
-        HALT_SYS();
-        return 0;
+       HALT_SYS();
+       return 0;
     }
 }
 
 /****************************************************************************
 PARAMETERS:
-offset  - Offset to load data from
+offset - Offset to load data from
 
 RETURNS:
 Byte value read from the absolute memory location.
@@ -305,14 +305,14 @@ u8 fetch_data_byte(
 {
 #ifdef DEBUG
     if (CHECK_DATA_ACCESS())
-        x86emu_check_data_access((u16)get_data_segment(), offset);
+       x86emu_check_data_access((u16)get_data_segment(), offset);
 #endif
     return (*sys_rdb)((get_data_segment() << 4) + offset);
 }
 
 /****************************************************************************
 PARAMETERS:
-offset  - Offset to load data from
+offset - Offset to load data from
 
 RETURNS:
 Word value read from the absolute memory location.
@@ -324,14 +324,14 @@ u16 fetch_data_word(
 {
 #ifdef DEBUG
     if (CHECK_DATA_ACCESS())
-        x86emu_check_data_access((u16)get_data_segment(), offset);
+       x86emu_check_data_access((u16)get_data_segment(), offset);
 #endif
     return (*sys_rdw)((get_data_segment() << 4) + offset);
 }
 
 /****************************************************************************
 PARAMETERS:
-offset  - Offset to load data from
+offset - Offset to load data from
 
 RETURNS:
 Long value read from the absolute memory location.
@@ -343,7 +343,7 @@ u32 fetch_data_long(
 {
 #ifdef DEBUG
     if (CHECK_DATA_ACCESS())
-        x86emu_check_data_access((u16)get_data_segment(), offset);
+       x86emu_check_data_access((u16)get_data_segment(), offset);
 #endif
     return (*sys_rdl)((get_data_segment() << 4) + offset);
 }
@@ -351,7 +351,7 @@ u32 fetch_data_long(
 /****************************************************************************
 PARAMETERS:
 segment - Segment to load data from
-offset  - Offset to load data from
+offset - Offset to load data from
 
 RETURNS:
 Byte value read from the absolute memory location.
@@ -364,7 +364,7 @@ u8 fetch_data_byte_abs(
 {
 #ifdef DEBUG
     if (CHECK_DATA_ACCESS())
-        x86emu_check_data_access(segment, offset);
+       x86emu_check_data_access(segment, offset);
 #endif
     return (*sys_rdb)(((u32)segment << 4) + offset);
 }
@@ -372,7 +372,7 @@ u8 fetch_data_byte_abs(
 /****************************************************************************
 PARAMETERS:
 segment - Segment to load data from
-offset  - Offset to load data from
+offset - Offset to load data from
 
 RETURNS:
 Word value read from the absolute memory location.
@@ -385,7 +385,7 @@ u16 fetch_data_word_abs(
 {
 #ifdef DEBUG
     if (CHECK_DATA_ACCESS())
-        x86emu_check_data_access(segment, offset);
+       x86emu_check_data_access(segment, offset);
 #endif
     return (*sys_rdw)(((u32)segment << 4) + offset);
 }
@@ -393,7 +393,7 @@ u16 fetch_data_word_abs(
 /****************************************************************************
 PARAMETERS:
 segment - Segment to load data from
-offset  - Offset to load data from
+offset - Offset to load data from
 
 RETURNS:
 Long value read from the absolute memory location.
@@ -406,15 +406,15 @@ u32 fetch_data_long_abs(
 {
 #ifdef DEBUG
     if (CHECK_DATA_ACCESS())
-        x86emu_check_data_access(segment, offset);
+       x86emu_check_data_access(segment, offset);
 #endif
     return (*sys_rdl)(((u32)segment << 4) + offset);
 }
 
 /****************************************************************************
 PARAMETERS:
-offset  - Offset to store data at
-val     - Value to store
+offset - Offset to store data at
+val    - Value to store
 
 REMARKS:
 Writes a word value to an segmented memory location. The segment used is
@@ -428,15 +428,15 @@ void store_data_byte(
 {
 #ifdef DEBUG
     if (CHECK_DATA_ACCESS())
-        x86emu_check_data_access((u16)get_data_segment(), offset);
+       x86emu_check_data_access((u16)get_data_segment(), offset);
 #endif
     (*sys_wrb)((get_data_segment() << 4) + offset, val);
 }
 
 /****************************************************************************
 PARAMETERS:
-offset  - Offset to store data at
-val     - Value to store
+offset - Offset to store data at
+val    - Value to store
 
 REMARKS:
 Writes a word value to an segmented memory location. The segment used is
@@ -450,15 +450,15 @@ void store_data_word(
 {
 #ifdef DEBUG
     if (CHECK_DATA_ACCESS())
-        x86emu_check_data_access((u16)get_data_segment(), offset);
+       x86emu_check_data_access((u16)get_data_segment(), offset);
 #endif
     (*sys_wrw)((get_data_segment() << 4) + offset, val);
 }
 
 /****************************************************************************
 PARAMETERS:
-offset  - Offset to store data at
-val     - Value to store
+offset - Offset to store data at
+val    - Value to store
 
 REMARKS:
 Writes a long value to an segmented memory location. The segment used is
@@ -472,7 +472,7 @@ void store_data_long(
 {
 #ifdef DEBUG
     if (CHECK_DATA_ACCESS())
-        x86emu_check_data_access((u16)get_data_segment(), offset);
+       x86emu_check_data_access((u16)get_data_segment(), offset);
 #endif
     (*sys_wrl)((get_data_segment() << 4) + offset, val);
 }
@@ -480,8 +480,8 @@ void store_data_long(
 /****************************************************************************
 PARAMETERS:
 segment - Segment to store data at
-offset  - Offset to store data at
-val     - Value to store
+offset - Offset to store data at
+val    - Value to store
 
 REMARKS:
 Writes a byte value to an absolute memory location.
@@ -495,7 +495,7 @@ void store_data_byte_abs(
 {
 #ifdef DEBUG
     if (CHECK_DATA_ACCESS())
-        x86emu_check_data_access(segment, offset);
+       x86emu_check_data_access(segment, offset);
 #endif
     (*sys_wrb)(((u32)segment << 4) + offset, val);
 }
@@ -503,8 +503,8 @@ void store_data_byte_abs(
 /****************************************************************************
 PARAMETERS:
 segment - Segment to store data at
-offset  - Offset to store data at
-val     - Value to store
+offset - Offset to store data at
+val    - Value to store
 
 REMARKS:
 Writes a word value to an absolute memory location.
@@ -518,7 +518,7 @@ void store_data_word_abs(
 {
 #ifdef DEBUG
     if (CHECK_DATA_ACCESS())
-        x86emu_check_data_access(segment, offset);
+       x86emu_check_data_access(segment, offset);
 #endif
     (*sys_wrw)(((u32)segment << 4) + offset, val);
 }
@@ -526,8 +526,8 @@ void store_data_word_abs(
 /****************************************************************************
 PARAMETERS:
 segment - Segment to store data at
-offset  - Offset to store data at
-val     - Value to store
+offset - Offset to store data at
+val    - Value to store
 
 REMARKS:
 Writes a long value to an absolute memory location.
@@ -541,7 +541,7 @@ void store_data_long_abs(
 {
 #ifdef DEBUG
     if (CHECK_DATA_ACCESS())
-        x86emu_check_data_access(segment, offset);
+       x86emu_check_data_access(segment, offset);
 #endif
     (*sys_wrl)(((u32)segment << 4) + offset, val);
 }
@@ -562,32 +562,32 @@ u8* decode_rm_byte_register(
 {
     switch (reg) {
       case 0:
-        DECODE_PRINTF("AL");
-        return &M.x86.R_AL;
+       DECODE_PRINTF("AL");
+       return &M.x86.R_AL;
       case 1:
-        DECODE_PRINTF("CL");
-        return &M.x86.R_CL;
+       DECODE_PRINTF("CL");
+       return &M.x86.R_CL;
       case 2:
-        DECODE_PRINTF("DL");
-        return &M.x86.R_DL;
+       DECODE_PRINTF("DL");
+       return &M.x86.R_DL;
       case 3:
-        DECODE_PRINTF("BL");
-        return &M.x86.R_BL;
+       DECODE_PRINTF("BL");
+       return &M.x86.R_BL;
       case 4:
-        DECODE_PRINTF("AH");
-        return &M.x86.R_AH;
+       DECODE_PRINTF("AH");
+       return &M.x86.R_AH;
       case 5:
-        DECODE_PRINTF("CH");
-        return &M.x86.R_CH;
+       DECODE_PRINTF("CH");
+       return &M.x86.R_CH;
       case 6:
-        DECODE_PRINTF("DH");
-        return &M.x86.R_DH;
+       DECODE_PRINTF("DH");
+       return &M.x86.R_DH;
       case 7:
-        DECODE_PRINTF("BH");
-        return &M.x86.R_BH;
+       DECODE_PRINTF("BH");
+       return &M.x86.R_BH;
     }
     HALT_SYS();
-    return NULL;                /* NOT REACHED OR REACHED ON ERROR */
+    return NULL;               /* NOT REACHED OR REACHED ON ERROR */
 }
 
 /****************************************************************************
@@ -599,39 +599,39 @@ Pointer to the appropriate register
 
 REMARKS:
 Return a pointer to the register given by the R/RM field of the
-modrm byte, for word operands.  Also enables the decoding of instructions.
+modrm byte, for word operands. Also enables the decoding of instructions.
 ****************************************************************************/
 u16* decode_rm_word_register(
     int reg)
 {
     switch (reg) {
       case 0:
-        DECODE_PRINTF("AX");
-        return &M.x86.R_AX;
+       DECODE_PRINTF("AX");
+       return &M.x86.R_AX;
       case 1:
-        DECODE_PRINTF("CX");
-        return &M.x86.R_CX;
+       DECODE_PRINTF("CX");
+       return &M.x86.R_CX;
       case 2:
-        DECODE_PRINTF("DX");
-        return &M.x86.R_DX;
+       DECODE_PRINTF("DX");
+       return &M.x86.R_DX;
       case 3:
-        DECODE_PRINTF("BX");
-        return &M.x86.R_BX;
+       DECODE_PRINTF("BX");
+       return &M.x86.R_BX;
       case 4:
-        DECODE_PRINTF("SP");
-        return &M.x86.R_SP;
+       DECODE_PRINTF("SP");
+       return &M.x86.R_SP;
       case 5:
-        DECODE_PRINTF("BP");
-        return &M.x86.R_BP;
+       DECODE_PRINTF("BP");
+       return &M.x86.R_BP;
       case 6:
-        DECODE_PRINTF("SI");
-        return &M.x86.R_SI;
+       DECODE_PRINTF("SI");
+       return &M.x86.R_SI;
       case 7:
-        DECODE_PRINTF("DI");
-        return &M.x86.R_DI;
+       DECODE_PRINTF("DI");
+       return &M.x86.R_DI;
     }
     HALT_SYS();
-    return NULL;                /* NOTREACHED OR REACHED ON ERROR */
+    return NULL;               /* NOTREACHED OR REACHED ON ERROR */
 }
 
 /****************************************************************************
@@ -643,39 +643,39 @@ Pointer to the appropriate register
 
 REMARKS:
 Return a pointer to the register given by the R/RM field of the
-modrm byte, for dword operands.  Also enables the decoding of instructions.
+modrm byte, for dword operands.         Also enables the decoding of instructions.
 ****************************************************************************/
 u32* decode_rm_long_register(
     int reg)
 {
     switch (reg) {
       case 0:
-        DECODE_PRINTF("EAX");
-        return &M.x86.R_EAX;
+       DECODE_PRINTF("EAX");
+       return &M.x86.R_EAX;
       case 1:
-        DECODE_PRINTF("ECX");
-        return &M.x86.R_ECX;
+       DECODE_PRINTF("ECX");
+       return &M.x86.R_ECX;
       case 2:
-        DECODE_PRINTF("EDX");
-        return &M.x86.R_EDX;
+       DECODE_PRINTF("EDX");
+       return &M.x86.R_EDX;
       case 3:
-        DECODE_PRINTF("EBX");
-        return &M.x86.R_EBX;
+       DECODE_PRINTF("EBX");
+       return &M.x86.R_EBX;
       case 4:
-        DECODE_PRINTF("ESP");
-        return &M.x86.R_ESP;
+       DECODE_PRINTF("ESP");
+       return &M.x86.R_ESP;
       case 5:
-        DECODE_PRINTF("EBP");
-        return &M.x86.R_EBP;
+       DECODE_PRINTF("EBP");
+       return &M.x86.R_EBP;
       case 6:
-        DECODE_PRINTF("ESI");
-        return &M.x86.R_ESI;
+       DECODE_PRINTF("ESI");
+       return &M.x86.R_ESI;
       case 7:
-        DECODE_PRINTF("EDI");
-        return &M.x86.R_EDI;
+       DECODE_PRINTF("EDI");
+       return &M.x86.R_EDI;
     }
     HALT_SYS();
-    return NULL;                /* NOTREACHED OR REACHED ON ERROR */
+    return NULL;               /* NOTREACHED OR REACHED ON ERROR */
 }
 
 /****************************************************************************
@@ -695,30 +695,30 @@ u16* decode_rm_seg_register(
 {
     switch (reg) {
       case 0:
-        DECODE_PRINTF("ES");
-        return &M.x86.R_ES;
+       DECODE_PRINTF("ES");
+       return &M.x86.R_ES;
       case 1:
-        DECODE_PRINTF("CS");
-        return &M.x86.R_CS;
+       DECODE_PRINTF("CS");
+       return &M.x86.R_CS;
       case 2:
-        DECODE_PRINTF("SS");
-        return &M.x86.R_SS;
+       DECODE_PRINTF("SS");
+       return &M.x86.R_SS;
       case 3:
-        DECODE_PRINTF("DS");
-        return &M.x86.R_DS;
+       DECODE_PRINTF("DS");
+       return &M.x86.R_DS;
       case 4:
-        DECODE_PRINTF("FS");
-        return &M.x86.R_FS;
+       DECODE_PRINTF("FS");
+       return &M.x86.R_FS;
       case 5:
-        DECODE_PRINTF("GS");
-        return &M.x86.R_GS;
+       DECODE_PRINTF("GS");
+       return &M.x86.R_GS;
       case 6:
       case 7:
-        DECODE_PRINTF("ILLEGAL SEGREG");
-        break;
+       DECODE_PRINTF("ILLEGAL SEGREG");
+       break;
     }
     HALT_SYS();
-    return NULL;                /* NOT REACHED OR REACHED ON ERROR */
+    return NULL;               /* NOT REACHED OR REACHED ON ERROR */
 }
 
 /****************************************************************************
@@ -739,38 +739,38 @@ unsigned decode_sib_si(
 {
     scale = 1 << scale;
     if (scale > 1) {
-        DECODE_PRINTF2("[%d*", scale);
+       DECODE_PRINTF2("[%d*", scale);
     } else {
-        DECODE_PRINTF("[");
+       DECODE_PRINTF("[");
     }
     switch (index) {
       case 0:
-        DECODE_PRINTF("EAX]");
-        return M.x86.R_EAX * index;
+       DECODE_PRINTF("EAX]");
+       return M.x86.R_EAX * index;
       case 1:
-        DECODE_PRINTF("ECX]");
-        return M.x86.R_ECX * index;
+       DECODE_PRINTF("ECX]");
+       return M.x86.R_ECX * index;
       case 2:
-        DECODE_PRINTF("EDX]");
-        return M.x86.R_EDX * index;
+       DECODE_PRINTF("EDX]");
+       return M.x86.R_EDX * index;
       case 3:
-        DECODE_PRINTF("EBX]");
-        return M.x86.R_EBX * index;
+       DECODE_PRINTF("EBX]");
+       return M.x86.R_EBX * index;
       case 4:
-        DECODE_PRINTF("0]");
-        return 0;
+       DECODE_PRINTF("0]");
+       return 0;
       case 5:
-        DECODE_PRINTF("EBP]");
-        return M.x86.R_EBP * index;
+       DECODE_PRINTF("EBP]");
+       return M.x86.R_EBP * index;
       case 6:
-        DECODE_PRINTF("ESI]");
-        return M.x86.R_ESI * index;
+       DECODE_PRINTF("ESI]");
+       return M.x86.R_ESI * index;
       case 7:
-        DECODE_PRINTF("EDI]");
-        return M.x86.R_EDI * index;
+       DECODE_PRINTF("EDI]");
+       return M.x86.R_EDI * index;
     }
     HALT_SYS();
-    return 0;                   /* NOT REACHED OR REACHED ON ERROR */
+    return 0;                  /* NOT REACHED OR REACHED ON ERROR */
 }
 
 /****************************************************************************
@@ -795,58 +795,58 @@ unsigned decode_sib_address(
 
     switch (base) {
       case 0:
-        DECODE_PRINTF("[EAX]");
-        offset = M.x86.R_EAX;
-        break;
+       DECODE_PRINTF("[EAX]");
+       offset = M.x86.R_EAX;
+       break;
       case 1:
-        DECODE_PRINTF("[ECX]");
-        offset = M.x86.R_ECX;
-        break;
+       DECODE_PRINTF("[ECX]");
+       offset = M.x86.R_ECX;
+       break;
       case 2:
-        DECODE_PRINTF("[EDX]");
-        offset = M.x86.R_EDX;
-        break;
+       DECODE_PRINTF("[EDX]");
+       offset = M.x86.R_EDX;
+       break;
       case 3:
-        DECODE_PRINTF("[EBX]");
-        offset = M.x86.R_EBX;
-        break;
+       DECODE_PRINTF("[EBX]");
+       offset = M.x86.R_EBX;
+       break;
       case 4:
-        DECODE_PRINTF("[ESP]");
-        offset = M.x86.R_ESP;
-        break;
+       DECODE_PRINTF("[ESP]");
+       offset = M.x86.R_ESP;
+       break;
       case 5:
-        switch (mod) {
-          case 0:
-            displacement = (s32)fetch_long_imm();
-            DECODE_PRINTF2("[%d]", displacement);
-            offset = displacement;
-            break;
-          case 1:
-            displacement = (s8)fetch_byte_imm();
-            DECODE_PRINTF2("[%d][EBP]", displacement);
-            offset = M.x86.R_EBP + displacement;
-            break;
-          case 2:
-            displacement = (s32)fetch_long_imm();
-            DECODE_PRINTF2("[%d][EBP]", displacement);
-            offset = M.x86.R_EBP + displacement;
-            break;
-          default:
-            HALT_SYS();
-        }
-        DECODE_PRINTF("[EAX]");
-        offset = M.x86.R_EAX;
-        break;
+       switch (mod) {
+         case 0:
+           displacement = (s32)fetch_long_imm();
+           DECODE_PRINTF2("[%d]", displacement);
+           offset = displacement;
+           break;
+         case 1:
+           displacement = (s8)fetch_byte_imm();
+           DECODE_PRINTF2("[%d][EBP]", displacement);
+           offset = M.x86.R_EBP + displacement;
+           break;
+         case 2:
+           displacement = (s32)fetch_long_imm();
+           DECODE_PRINTF2("[%d][EBP]", displacement);
+           offset = M.x86.R_EBP + displacement;
+           break;
+         default:
+           HALT_SYS();
+       }
+       DECODE_PRINTF("[EAX]");
+       offset = M.x86.R_EAX;
+       break;
       case 6:
-        DECODE_PRINTF("[ESI]");
-        offset = M.x86.R_ESI;
-        break;
+       DECODE_PRINTF("[ESI]");
+       offset = M.x86.R_ESI;
+       break;
       case 7:
-        DECODE_PRINTF("[EDI]");
-        offset = M.x86.R_EDI;
-        break;
+       DECODE_PRINTF("[EDI]");
+       offset = M.x86.R_EDI;
+       break;
       default:
-        HALT_SYS();
+       HALT_SYS();
     }
     offset += decode_sib_si(ss, index);
     return offset;
@@ -864,14 +864,14 @@ REMARKS:
 Return the offset given by mod=00 addressing.  Also enables the
 decoding of instructions.
 
-NOTE:   The code which specifies the corresponding segment (ds vs ss)
-        below in the case of [BP+..].  The assumption here is that at the
-        point that this subroutine is called, the bit corresponding to
-        SYSMODE_SEG_DS_SS will be zero.  After every instruction
-        except the segment override instructions, this bit (as well
-        as any bits indicating segment overrides) will be clear.  So
-        if a SS access is needed, set this bit.  Otherwise, DS access
-        occurs (unless any of the segment override bits are set).
+NOTE:  The code which specifies the corresponding segment (ds vs ss)
+       below in the case of [BP+..].  The assumption here is that at the
+       point that this subroutine is called, the bit corresponding to
+       SYSMODE_SEG_DS_SS will be zero.  After every instruction
+       except the segment override instructions, this bit (as well
+       as any bits indicating segment overrides) will be clear.  So
+       if a SS access is needed, set this bit.  Otherwise, DS access
+       occurs (unless any of the segment override bits are set).
 ****************************************************************************/
 unsigned decode_rm00_address(
     int rm)
@@ -879,64 +879,64 @@ unsigned decode_rm00_address(
     unsigned offset;
 
     if (M.x86.mode & SYSMODE_PREFIX_ADDR) {
-        /* 32-bit addressing */
-        switch (rm) {
-          case 0:
-            DECODE_PRINTF("[EAX]");
-            return M.x86.R_EAX;
-          case 1:
-            DECODE_PRINTF("[ECX]");
-            return M.x86.R_ECX;
-          case 2:
-            DECODE_PRINTF("[EDX]");
-            return M.x86.R_EDX;
-          case 3:
-            DECODE_PRINTF("[EBX]");
-            return M.x86.R_EBX;
-          case 4:
-            return decode_sib_address(0);
-          case 5:
-            offset = fetch_long_imm();
-            DECODE_PRINTF2("[%08x]", offset);
-            return offset;
-          case 6:
-            DECODE_PRINTF("[ESI]");
-            return M.x86.R_ESI;
-          case 7:
-            DECODE_PRINTF("[EDI]");
-            return M.x86.R_EDI;
-        }
+       /* 32-bit addressing */
+       switch (rm) {
+         case 0:
+           DECODE_PRINTF("[EAX]");
+           return M.x86.R_EAX;
+         case 1:
+           DECODE_PRINTF("[ECX]");
+           return M.x86.R_ECX;
+         case 2:
+           DECODE_PRINTF("[EDX]");
+           return M.x86.R_EDX;
+         case 3:
+           DECODE_PRINTF("[EBX]");
+           return M.x86.R_EBX;
+         case 4:
+           return decode_sib_address(0);
+         case 5:
+           offset = fetch_long_imm();
+           DECODE_PRINTF2("[%08x]", offset);
+           return offset;
+         case 6:
+           DECODE_PRINTF("[ESI]");
+           return M.x86.R_ESI;
+         case 7:
+           DECODE_PRINTF("[EDI]");
+           return M.x86.R_EDI;
+       }
     } else {
-        /* 16-bit addressing */
-        switch (rm) {
-          case 0:
-            DECODE_PRINTF("[BX+SI]");
-            return (M.x86.R_BX + M.x86.R_SI) & 0xffff;
-          case 1:
-            DECODE_PRINTF("[BX+DI]");
-            return (M.x86.R_BX + M.x86.R_DI) & 0xffff;
-          case 2:
-            DECODE_PRINTF("[BP+SI]");
-            M.x86.mode |= SYSMODE_SEG_DS_SS;
-            return (M.x86.R_BP + M.x86.R_SI) & 0xffff;
-          case 3:
-            DECODE_PRINTF("[BP+DI]");
-            M.x86.mode |= SYSMODE_SEG_DS_SS;
-            return (M.x86.R_BP + M.x86.R_DI) & 0xffff;
-          case 4:
-            DECODE_PRINTF("[SI]");
-            return M.x86.R_SI;
-          case 5:
-            DECODE_PRINTF("[DI]");
-            return M.x86.R_DI;
-          case 6:
-            offset = fetch_word_imm();
-            DECODE_PRINTF2("[%04x]", offset);
-            return offset;
-          case 7:
-            DECODE_PRINTF("[BX]");
-            return M.x86.R_BX;
-        }
+       /* 16-bit addressing */
+       switch (rm) {
+         case 0:
+           DECODE_PRINTF("[BX+SI]");
+           return (M.x86.R_BX + M.x86.R_SI) & 0xffff;
+         case 1:
+           DECODE_PRINTF("[BX+DI]");
+           return (M.x86.R_BX + M.x86.R_DI) & 0xffff;
+         case 2:
+           DECODE_PRINTF("[BP+SI]");
+           M.x86.mode |= SYSMODE_SEG_DS_SS;
+           return (M.x86.R_BP + M.x86.R_SI) & 0xffff;
+         case 3:
+           DECODE_PRINTF("[BP+DI]");
+           M.x86.mode |= SYSMODE_SEG_DS_SS;
+           return (M.x86.R_BP + M.x86.R_DI) & 0xffff;
+         case 4:
+           DECODE_PRINTF("[SI]");
+           return M.x86.R_SI;
+         case 5:
+           DECODE_PRINTF("[DI]");
+           return M.x86.R_DI;
+         case 6:
+           offset = fetch_word_imm();
+           DECODE_PRINTF2("[%04x]", offset);
+           return offset;
+         case 7:
+           DECODE_PRINTF("[BX]");
+           return M.x86.R_BX;
+       }
     }
     HALT_SYS();
     return 0;
@@ -959,76 +959,76 @@ unsigned decode_rm01_address(
     int displacement;
 
     if (M.x86.mode & SYSMODE_PREFIX_ADDR) {
-        /* 32-bit addressing */
-        if (rm != 4)
-            displacement = (s8)fetch_byte_imm();
-        else
-            displacement = 0;
-
-        switch (rm) {
-          case 0:
-            DECODE_PRINTF2("%d[EAX]", displacement);
-            return M.x86.R_EAX + displacement;
-          case 1:
-            DECODE_PRINTF2("%d[ECX]", displacement);
-            return M.x86.R_ECX + displacement;
-          case 2:
-            DECODE_PRINTF2("%d[EDX]", displacement);
-            return M.x86.R_EDX + displacement;
-          case 3:
-            DECODE_PRINTF2("%d[EBX]", displacement);
-            return M.x86.R_EBX + displacement;
-          case 4: {
-            int offset = decode_sib_address(1);
-            displacement = (s8)fetch_byte_imm();
-            DECODE_PRINTF2("[%d]", displacement);
-            return offset + displacement;
-          }
-          case 5:
-            DECODE_PRINTF2("%d[EBP]", displacement);
-            return M.x86.R_EBP + displacement;
-          case 6:
-            DECODE_PRINTF2("%d[ESI]", displacement);
-            return M.x86.R_ESI + displacement;
-          case 7:
-            DECODE_PRINTF2("%d[EDI]", displacement);
-            return M.x86.R_EDI + displacement;
-        }
+       /* 32-bit addressing */
+       if (rm != 4)
+           displacement = (s8)fetch_byte_imm();
+       else
+           displacement = 0;
+
+       switch (rm) {
+         case 0:
+           DECODE_PRINTF2("%d[EAX]", displacement);
+           return M.x86.R_EAX + displacement;
+         case 1:
+           DECODE_PRINTF2("%d[ECX]", displacement);
+           return M.x86.R_ECX + displacement;
+         case 2:
+           DECODE_PRINTF2("%d[EDX]", displacement);
+           return M.x86.R_EDX + displacement;
+         case 3:
+           DECODE_PRINTF2("%d[EBX]", displacement);
+           return M.x86.R_EBX + displacement;
+         case 4: {
+           int offset = decode_sib_address(1);
+           displacement = (s8)fetch_byte_imm();
+           DECODE_PRINTF2("[%d]", displacement);
+           return offset + displacement;
+         }
+         case 5:
+           DECODE_PRINTF2("%d[EBP]", displacement);
+           return M.x86.R_EBP + displacement;
+         case 6:
+           DECODE_PRINTF2("%d[ESI]", displacement);
+           return M.x86.R_ESI + displacement;
+         case 7:
+           DECODE_PRINTF2("%d[EDI]", displacement);
+           return M.x86.R_EDI + displacement;
+       }
     } else {
-        /* 16-bit addressing */
-        displacement = (s8)fetch_byte_imm();
-        switch (rm) {
-          case 0:
-            DECODE_PRINTF2("%d[BX+SI]", displacement);
-            return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff;
-          case 1:
-            DECODE_PRINTF2("%d[BX+DI]", displacement);
-            return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff;
-          case 2:
-            DECODE_PRINTF2("%d[BP+SI]", displacement);
-            M.x86.mode |= SYSMODE_SEG_DS_SS;
-            return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff;
-          case 3:
-            DECODE_PRINTF2("%d[BP+DI]", displacement);
-            M.x86.mode |= SYSMODE_SEG_DS_SS;
-            return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff;
-          case 4:
-            DECODE_PRINTF2("%d[SI]", displacement);
-            return (M.x86.R_SI + displacement) & 0xffff;
-          case 5:
-            DECODE_PRINTF2("%d[DI]", displacement);
-            return (M.x86.R_DI + displacement) & 0xffff;
-          case 6:
-            DECODE_PRINTF2("%d[BP]", displacement);
-            M.x86.mode |= SYSMODE_SEG_DS_SS;
-            return (M.x86.R_BP + displacement) & 0xffff;
-          case 7:
-            DECODE_PRINTF2("%d[BX]", displacement);
-            return (M.x86.R_BX + displacement) & 0xffff;
-        }
+       /* 16-bit addressing */
+       displacement = (s8)fetch_byte_imm();
+       switch (rm) {
+         case 0:
+           DECODE_PRINTF2("%d[BX+SI]", displacement);
+           return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff;
+         case 1:
+           DECODE_PRINTF2("%d[BX+DI]", displacement);
+           return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff;
+         case 2:
+           DECODE_PRINTF2("%d[BP+SI]", displacement);
+           M.x86.mode |= SYSMODE_SEG_DS_SS;
+           return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff;
+         case 3:
+           DECODE_PRINTF2("%d[BP+DI]", displacement);
+           M.x86.mode |= SYSMODE_SEG_DS_SS;
+           return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff;
+         case 4:
+           DECODE_PRINTF2("%d[SI]", displacement);
+           return (M.x86.R_SI + displacement) & 0xffff;
+         case 5:
+           DECODE_PRINTF2("%d[DI]", displacement);
+           return (M.x86.R_DI + displacement) & 0xffff;
+         case 6:
+           DECODE_PRINTF2("%d[BP]", displacement);
+           M.x86.mode |= SYSMODE_SEG_DS_SS;
+           return (M.x86.R_BP + displacement) & 0xffff;
+         case 7:
+           DECODE_PRINTF2("%d[BX]", displacement);
+           return (M.x86.R_BX + displacement) & 0xffff;
+       }
     }
     HALT_SYS();
-    return 0;                   /* SHOULD NOT HAPPEN */
+    return 0;                  /* SHOULD NOT HAPPEN */
 }
 
 /****************************************************************************
@@ -1046,82 +1046,81 @@ unsigned decode_rm10_address(
     int rm)
 {
     if (M.x86.mode & SYSMODE_PREFIX_ADDR) {
-        int displacement;
-
-        /* 32-bit addressing */
-        if (rm != 4)
-            displacement = (s32)fetch_long_imm();
-        else
-            displacement = 0;
-
-        switch (rm) {
-          case 0:
-            DECODE_PRINTF2("%d[EAX]", displacement);
-            return M.x86.R_EAX + displacement;
-          case 1:
-            DECODE_PRINTF2("%d[ECX]", displacement);
-            return M.x86.R_ECX + displacement;
-          case 2:
-            DECODE_PRINTF2("%d[EDX]", displacement);
-            return M.x86.R_EDX + displacement;
-          case 3:
-            DECODE_PRINTF2("%d[EBX]", displacement);
-            return M.x86.R_EBX + displacement;
-          case 4: {
-            int offset = decode_sib_address(2);
-            displacement = (s32)fetch_long_imm();
-            DECODE_PRINTF2("[%d]", displacement);
-            return offset + displacement;
-          }
-          case 5:
-            DECODE_PRINTF2("%d[EBP]", displacement);
-            return M.x86.R_EBP + displacement;
-          case 6:
-            DECODE_PRINTF2("%d[ESI]", displacement);
-            return M.x86.R_ESI + displacement;
-          case 7:
-            DECODE_PRINTF2("%d[EDI]", displacement);
-            return M.x86.R_EDI + displacement;
-        }
+       int displacement;
+
+       /* 32-bit addressing */
+       if (rm != 4)
+           displacement = (s32)fetch_long_imm();
+       else
+           displacement = 0;
+
+       switch (rm) {
+         case 0:
+           DECODE_PRINTF2("%d[EAX]", displacement);
+           return M.x86.R_EAX + displacement;
+         case 1:
+           DECODE_PRINTF2("%d[ECX]", displacement);
+           return M.x86.R_ECX + displacement;
+         case 2:
+           DECODE_PRINTF2("%d[EDX]", displacement);
+           return M.x86.R_EDX + displacement;
+         case 3:
+           DECODE_PRINTF2("%d[EBX]", displacement);
+           return M.x86.R_EBX + displacement;
+         case 4: {
+           int offset = decode_sib_address(2);
+           displacement = (s32)fetch_long_imm();
+           DECODE_PRINTF2("[%d]", displacement);
+           return offset + displacement;
+         }
+         case 5:
+           DECODE_PRINTF2("%d[EBP]", displacement);
+           return M.x86.R_EBP + displacement;
+         case 6:
+           DECODE_PRINTF2("%d[ESI]", displacement);
+           return M.x86.R_ESI + displacement;
+         case 7:
+           DECODE_PRINTF2("%d[EDI]", displacement);
+           return M.x86.R_EDI + displacement;
+       }
     } else {
-        int displacement = (s16)fetch_word_imm();
-
-        /* 16-bit addressing */
-        switch (rm) {
-          case 0:
-            DECODE_PRINTF2("%d[BX+SI]", displacement);
-            return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff;
-          case 1:
-            DECODE_PRINTF2("%d[BX+DI]", displacement);
-            return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff;
-          case 2:
-            DECODE_PRINTF2("%d[BP+SI]", displacement);
-            M.x86.mode |= SYSMODE_SEG_DS_SS;
-            return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff;
-          case 3:
-            DECODE_PRINTF2("%d[BP+DI]", displacement);
-            M.x86.mode |= SYSMODE_SEG_DS_SS;
-            return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff;
-          case 4:
-            DECODE_PRINTF2("%d[SI]", displacement);
-            return (M.x86.R_SI + displacement) & 0xffff;
-          case 5:
-            DECODE_PRINTF2("%d[DI]", displacement);
-            return (M.x86.R_DI + displacement) & 0xffff;
-          case 6:
-            DECODE_PRINTF2("%d[BP]", displacement);
-            M.x86.mode |= SYSMODE_SEG_DS_SS;
-            return (M.x86.R_BP + displacement) & 0xffff;
-          case 7:
-            DECODE_PRINTF2("%d[BX]", displacement);
-            return (M.x86.R_BX + displacement) & 0xffff;
-        }
+       int displacement = (s16)fetch_word_imm();
+
+       /* 16-bit addressing */
+       switch (rm) {
+         case 0:
+           DECODE_PRINTF2("%d[BX+SI]", displacement);
+           return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff;
+         case 1:
+           DECODE_PRINTF2("%d[BX+DI]", displacement);
+           return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff;
+         case 2:
+           DECODE_PRINTF2("%d[BP+SI]", displacement);
+           M.x86.mode |= SYSMODE_SEG_DS_SS;
+           return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff;
+         case 3:
+           DECODE_PRINTF2("%d[BP+DI]", displacement);
+           M.x86.mode |= SYSMODE_SEG_DS_SS;
+           return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff;
+         case 4:
+           DECODE_PRINTF2("%d[SI]", displacement);
+           return (M.x86.R_SI + displacement) & 0xffff;
+         case 5:
+           DECODE_PRINTF2("%d[DI]", displacement);
+           return (M.x86.R_DI + displacement) & 0xffff;
+         case 6:
+           DECODE_PRINTF2("%d[BP]", displacement);
+           M.x86.mode |= SYSMODE_SEG_DS_SS;
+           return (M.x86.R_BP + displacement) & 0xffff;
+         case 7:
+           DECODE_PRINTF2("%d[BX]", displacement);
+           return (M.x86.R_BX + displacement) & 0xffff;
+       }
     }
     HALT_SYS();
-    return 0;                   /* SHOULD NOT HAPPEN */
+    return 0;                  /* SHOULD NOT HAPPEN */
 }
 
-
 /****************************************************************************
 PARAMETERS:
 mod - modifier
@@ -1143,6 +1142,3 @@ unsigned decode_rmXX_address(int mod, int rm)
     return decode_rm01_address(rm);
   return decode_rm10_address(rm);
 }
-
-
-
index 632979dd574967e137f1e7031404551a0c290f78..d1380ceec0099526d1552a5bc8a968a17f1ae79a 100644 (file)
@@ -4,9 +4,9 @@
 *  Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
 *  Jason Jin <Jason.jin@freescale.com>
 *
-*              Copyright (C) 1991-2004 SciTech Software, Inc.
-*                                   Copyright (C) David Mosberger-Tang
-*                                         Copyright (C) 1999 Egbert Eich
+*              Copyright (C) 1991-2004 SciTech Software, Inc.
+*                                   Copyright (C) David Mosberger-Tang
+*                                         Copyright (C) 1999 Egbert Eich
 *
 *  ========================================================================
 *
@@ -16,7 +16,7 @@
 *  both that copyright notice and this permission notice appear in
 *  supporting documentation, and that the name of the authors not be used
 *  in advertising or publicity pertaining to distribution of the software
-*  without specific, written prior permission.  The authors makes no
+*  without specific, written prior permission. The authors makes no
 *  representations about the suitability of this software for any purpose.
 *  It is provided "as is" without express or implied warranty.
 *
 *
 * Language:            ANSI C
 * Environment: Any
-* Developer:    Kendall Bennett
+* Developer:   Kendall Bennett
 *
-* Description:  This file includes subroutines to implement the decoding
-*               and emulation of all the x86 processor instructions.
+* Description: This file includes subroutines to implement the decoding
+*              and emulation of all the x86 processor instructions.
 *
 * There are approximately 250 subroutines in here, which correspond
-* to the 256 byte-"opcodes" found on the 8086.  The table which
+* to the 256 byte-"opcodes" found on the 8086. The table which
 * dispatches this is found in the files optab.[ch].
 *
 * Each opcode proc has a comment preceeding it which gives it's table
 * DECODE_PRINTF2), debugging (TRACE_REGS, SINGLE_STEP), and misc
 * functions (START_OF_INSTR, END_OF_INSTR).
 *
-* Many of the procedures are *VERY* similar in coding.  This has
+* Many of the procedures are *VERY* similar in coding. This has
 * allowed for a very large amount of code to be generated in a fairly
 * short amount of time (i.e. cut, paste, and modify).  The result is
 * that much of the code below could have been folded into subroutines
 * for a large reduction in size of this file.  The downside would be
 * that there would be a penalty in execution speed.  The file could
 * also have been *MUCH* larger by inlining certain functions which
-* were called.  This could have resulted even faster execution.  The
+* were called. This could have resulted even faster execution.  The
 * prime directive I used to decide whether to inline the code or to
 * modularize it, was basically: 1) no unnecessary subroutine calls,
 * 2) no routines more than about 200 lines in size, and 3) modularize
@@ -88,38 +88,38 @@ static char *x86emu_GenOpName[8] = {
 /* used by several opcodes  */
 static u8 (*genop_byte_operation[])(u8 d, u8 s) __attribute__ ((section(".got2"))) =
 {
-    add_byte,           /* 00 */
-    or_byte,            /* 01 */
-    adc_byte,           /* 02 */
-    sbb_byte,           /* 03 */
-    and_byte,           /* 04 */
-    sub_byte,           /* 05 */
-    xor_byte,           /* 06 */
-    cmp_byte,           /* 07 */
+    add_byte,          /* 00 */
+    or_byte,           /* 01 */
+    adc_byte,          /* 02 */
+    sbb_byte,          /* 03 */
+    and_byte,          /* 04 */
+    sub_byte,          /* 05 */
+    xor_byte,          /* 06 */
+    cmp_byte,          /* 07 */
 };
 
 static u16 (*genop_word_operation[])(u16 d, u16 s) __attribute__ ((section(".got2"))) =
 {
-    add_word,           /*00 */
-    or_word,            /*01 */
-    adc_word,           /*02 */
-    sbb_word,           /*03 */
-    and_word,           /*04 */
-    sub_word,           /*05 */
-    xor_word,           /*06 */
-    cmp_word,           /*07 */
+    add_word,          /*00 */
+    or_word,           /*01 */
+    adc_word,          /*02 */
+    sbb_word,          /*03 */
+    and_word,          /*04 */
+    sub_word,          /*05 */
+    xor_word,          /*06 */
+    cmp_word,          /*07 */
 };
 
 static u32 (*genop_long_operation[])(u32 d, u32 s) __attribute__ ((section(".got2"))) =
 {
-    add_long,           /*00 */
-    or_long,            /*01 */
-    adc_long,           /*02 */
-    sbb_long,           /*03 */
-    and_long,           /*04 */
-    sub_long,           /*05 */
-    xor_long,           /*06 */
-    cmp_long,           /*07 */
+    add_long,          /*00 */
+    or_long,           /*01 */
+    adc_long,          /*02 */
+    sbb_long,          /*03 */
+    and_long,          /*04 */
+    sub_long,          /*05 */
+    xor_long,          /*06 */
+    cmp_long,          /*07 */
 };
 
 /* used by opcodes 80, c0, d0, and d2. */
@@ -131,7 +131,7 @@ static u8(*opcD0_byte_operation[])(u8 d, u8 s) __attribute__ ((section(".got2"))
     rcr_byte,
     shl_byte,
     shr_byte,
-    shl_byte,           /* sal_byte === shl_byte  by definition */
+    shl_byte,          /* sal_byte === shl_byte  by definition */
     sar_byte,
 };
 
@@ -144,7 +144,7 @@ static u16(*opcD1_word_operation[])(u16 s, u8 d) __attribute__ ((section(".got2"
     rcr_word,
     shl_word,
     shr_word,
-    shl_word,           /* sal_byte === shl_byte  by definition */
+    shl_word,          /* sal_byte === shl_byte  by definition */
     sar_word,
 };
 
@@ -157,7 +157,7 @@ static u32 (*opcD1_long_operation[])(u32 s, u8 d) __attribute__ ((section(".got2
     rcr_long,
     shl_long,
     shr_long,
-    shl_long,           /* sal_byte === shl_byte  by definition */
+    shl_long,          /* sal_byte === shl_byte  by definition */
     sar_long,
 };
 
@@ -180,21 +180,21 @@ void x86emuOp_illegal_op(
 {
     START_OF_INSTR();
     if (M.x86.R_SP != 0) {
-        DECODE_PRINTF("ILLEGAL X86 OPCODE\n");
-        TRACE_REGS();
-        DB( printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n",
-            M.x86.R_CS, M.x86.R_IP-1,op1));
-        HALT_SYS();
-        }
+       DECODE_PRINTF("ILLEGAL X86 OPCODE\n");
+       TRACE_REGS();
+       DB( printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n",
+           M.x86.R_CS, M.x86.R_IP-1,op1));
+       HALT_SYS();
+       }
     else {
-        /* If we get here, it means the stack pointer is back to zero
-         * so we are just returning from an emulator service call
-         * so therte is no need to display an error message. We trap
-         * the emulator with an 0xF1 opcode to finish the service
-         * call.
-         */
-        X86EMU_halt_sys();
-        }
+       /* If we get here, it means the stack pointer is back to zero
+        * so we are just returning from an emulator service call
+        * so therte is no need to display an error message. We trap
+        * the emulator with an 0xF1 opcode to finish the service
+        * call.
+        */
+       X86EMU_halt_sys();
+       }
     END_OF_INSTR();
 }
 
@@ -216,24 +216,24 @@ void x86emuOp_genop_byte_RM_R(u8 op1)
     DECODE_PRINTF("\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if(mod<3)
-        { destoffset = decode_rmXX_address(mod,rl);
-        DECODE_PRINTF(",");
-        destval = fetch_data_byte(destoffset);
-        srcreg = DECODE_RM_BYTE_REGISTER(rh);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        destval = genop_byte_operation[op1](destval, *srcreg);
-        store_data_byte(destoffset, destval);
-        }
+       { destoffset = decode_rmXX_address(mod,rl);
+       DECODE_PRINTF(",");
+       destval = fetch_data_byte(destoffset);
+       srcreg = DECODE_RM_BYTE_REGISTER(rh);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       destval = genop_byte_operation[op1](destval, *srcreg);
+       store_data_byte(destoffset, destval);
+       }
     else
-        {                       /* register to register */
-        destreg = DECODE_RM_BYTE_REGISTER(rl);
-        DECODE_PRINTF(",");
-        srcreg = DECODE_RM_BYTE_REGISTER(rh);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *destreg = genop_byte_operation[op1](*destreg, *srcreg);
-        }
+       {                       /* register to register */
+       destreg = DECODE_RM_BYTE_REGISTER(rl);
+       DECODE_PRINTF(",");
+       srcreg = DECODE_RM_BYTE_REGISTER(rh);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *destreg = genop_byte_operation[op1](*destreg, *srcreg);
+       }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
 }
@@ -255,50 +255,50 @@ void x86emuOp_genop_word_RM_R(u8 op1)
     FETCH_DECODE_MODRM(mod, rh, rl);
 
     if(mod<3) {
-        destoffset = decode_rmXX_address(mod,rl);
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 destval;
-            u32 *srcreg;
-
-            DECODE_PRINTF(",");
-            destval = fetch_data_long(destoffset);
-            srcreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            destval = genop_long_operation[op1](destval, *srcreg);
-            store_data_long(destoffset, destval);
-        } else {
-            u16 destval;
-            u16 *srcreg;
-
-            DECODE_PRINTF(",");
-            destval = fetch_data_word(destoffset);
-            srcreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            destval = genop_word_operation[op1](destval, *srcreg);
-            store_data_word(destoffset, destval);
-        }
-    } else {                    /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg,*srcreg;
-
-            destreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = genop_long_operation[op1](*destreg, *srcreg);
-        } else {
-            u16 *destreg,*srcreg;
-
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = genop_word_operation[op1](*destreg, *srcreg);
-        }
+       destoffset = decode_rmXX_address(mod,rl);
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 destval;
+           u32 *srcreg;
+
+           DECODE_PRINTF(",");
+           destval = fetch_data_long(destoffset);
+           srcreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           destval = genop_long_operation[op1](destval, *srcreg);
+           store_data_long(destoffset, destval);
+       } else {
+           u16 destval;
+           u16 *srcreg;
+
+           DECODE_PRINTF(",");
+           destval = fetch_data_word(destoffset);
+           srcreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           destval = genop_word_operation[op1](destval, *srcreg);
+           store_data_word(destoffset, destval);
+       }
+    } else {                   /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg,*srcreg;
+
+           destreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = genop_long_operation[op1](*destreg, *srcreg);
+       } else {
+           u16 *destreg,*srcreg;
+
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = genop_word_operation[op1](*destreg, *srcreg);
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -322,15 +322,15 @@ void x86emuOp_genop_byte_R_RM(u8 op1)
     DECODE_PRINTF("\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        destreg = DECODE_RM_BYTE_REGISTER(rh);
-        DECODE_PRINTF(",");
-        srcoffset = decode_rmXX_address(mod,rl);
-        srcval = fetch_data_byte(srcoffset);
-    } else {     /* register to register */
-        destreg = DECODE_RM_BYTE_REGISTER(rh);
-        DECODE_PRINTF(",");
-        srcreg = DECODE_RM_BYTE_REGISTER(rl);
-        srcval = *srcreg;
+       destreg = DECODE_RM_BYTE_REGISTER(rh);
+       DECODE_PRINTF(",");
+       srcoffset = decode_rmXX_address(mod,rl);
+       srcval = fetch_data_byte(srcoffset);
+    } else {    /* register to register */
+       destreg = DECODE_RM_BYTE_REGISTER(rh);
+       DECODE_PRINTF(",");
+       srcreg = DECODE_RM_BYTE_REGISTER(rl);
+       srcval = *srcreg;
     }
     DECODE_PRINTF("\n");
     TRACE_AND_STEP();
@@ -358,40 +358,40 @@ void x86emuOp_genop_word_R_RM(u8 op1)
     DECODE_PRINTF("\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        srcoffset = decode_rmXX_address(mod,rl);
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            destreg32 = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcval = fetch_data_long(srcoffset);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg32 = genop_long_operation[op1](*destreg32, srcval);
-        } else {
-            destreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcval = fetch_data_word(srcoffset);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = genop_word_operation[op1](*destreg, srcval);
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *srcreg;
-            destreg32 = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg32 = genop_long_operation[op1](*destreg32, *srcreg);
-        } else {
-            u16 *srcreg;
-            destreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = genop_word_operation[op1](*destreg, *srcreg);
-        }
+       srcoffset = decode_rmXX_address(mod,rl);
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           destreg32 = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcval = fetch_data_long(srcoffset);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg32 = genop_long_operation[op1](*destreg32, srcval);
+       } else {
+           destreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcval = fetch_data_word(srcoffset);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = genop_word_operation[op1](*destreg, srcval);
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *srcreg;
+           destreg32 = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg32 = genop_long_operation[op1](*destreg32, *srcreg);
+       } else {
+           u16 *srcreg;
+           destreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = genop_word_operation[op1](*destreg, *srcreg);
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -430,20 +430,20 @@ void x86emuOp_genop_word_AX_IMM(u8 op1)
 
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF(x86emu_GenOpName[op1]);
-        DECODE_PRINTF("\tEAX,");
-        srcval = fetch_long_imm();
+       DECODE_PRINTF(x86emu_GenOpName[op1]);
+       DECODE_PRINTF("\tEAX,");
+       srcval = fetch_long_imm();
     } else {
-        DECODE_PRINTF(x86emu_GenOpName[op1]);
-        DECODE_PRINTF("\tAX,");
-        srcval = fetch_word_imm();
+       DECODE_PRINTF(x86emu_GenOpName[op1]);
+       DECODE_PRINTF("\tAX,");
+       srcval = fetch_word_imm();
     }
     DECODE_PRINTF2("%x\n", srcval);
     TRACE_AND_STEP();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        M.x86.R_EAX = genop_long_operation[op1](M.x86.R_EAX, srcval);
+       M.x86.R_EAX = genop_long_operation[op1](M.x86.R_EAX, srcval);
     } else {
-        M.x86.R_AX = genop_word_operation[op1](M.x86.R_AX, (u16)srcval);
+       M.x86.R_AX = genop_word_operation[op1](M.x86.R_AX, (u16)srcval);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -683,17 +683,17 @@ void x86emuOp_inc_register(u8 op1)
     op1 &= 0x7;
     DECODE_PRINTF("INC\t");
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        u32 *reg;
-        reg = DECODE_RM_LONG_REGISTER(op1);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *reg = inc_long(*reg);
+       u32 *reg;
+       reg = DECODE_RM_LONG_REGISTER(op1);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *reg = inc_long(*reg);
     } else {
-        u16 *reg;
-        reg = DECODE_RM_WORD_REGISTER(op1);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *reg = inc_word(*reg);
+       u16 *reg;
+       reg = DECODE_RM_WORD_REGISTER(op1);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *reg = inc_word(*reg);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -709,17 +709,17 @@ void x86emuOp_dec_register(u8 op1)
     op1 &= 0x7;
     DECODE_PRINTF("DEC\t");
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        u32 *reg;
-        reg = DECODE_RM_LONG_REGISTER(op1);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *reg = dec_long(*reg);
+       u32 *reg;
+       reg = DECODE_RM_LONG_REGISTER(op1);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *reg = dec_long(*reg);
     } else {
-        u16 *reg;
-        reg = DECODE_RM_WORD_REGISTER(op1);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *reg = dec_word(*reg);
+       u16 *reg;
+       reg = DECODE_RM_WORD_REGISTER(op1);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *reg = dec_word(*reg);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -735,17 +735,17 @@ void x86emuOp_push_register(u8 op1)
     op1 &= 0x7;
     DECODE_PRINTF("PUSH\t");
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        u32 *reg;
-        reg = DECODE_RM_LONG_REGISTER(op1);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        push_long(*reg);
+       u32 *reg;
+       reg = DECODE_RM_LONG_REGISTER(op1);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       push_long(*reg);
     } else {
-        u16 *reg;
-        reg = DECODE_RM_WORD_REGISTER(op1);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        push_word(*reg);
+       u16 *reg;
+       reg = DECODE_RM_WORD_REGISTER(op1);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       push_word(*reg);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -761,17 +761,17 @@ void x86emuOp_pop_register(u8 op1)
     op1 &= 0x7;
     DECODE_PRINTF("POP\t");
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        u32 *reg;
-        reg = DECODE_RM_LONG_REGISTER(op1);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *reg = pop_long();
+       u32 *reg;
+       reg = DECODE_RM_LONG_REGISTER(op1);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *reg = pop_long();
     } else {
-        u16 *reg;
-        reg = DECODE_RM_WORD_REGISTER(op1);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *reg = pop_word();
+       u16 *reg;
+       reg = DECODE_RM_WORD_REGISTER(op1);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *reg = pop_word();
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -785,33 +785,33 @@ void x86emuOp_push_all(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF("PUSHAD\n");
+       DECODE_PRINTF("PUSHAD\n");
     } else {
-        DECODE_PRINTF("PUSHA\n");
+       DECODE_PRINTF("PUSHA\n");
     }
     TRACE_AND_STEP();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        u32 old_sp = M.x86.R_ESP;
-
-        push_long(M.x86.R_EAX);
-        push_long(M.x86.R_ECX);
-        push_long(M.x86.R_EDX);
-        push_long(M.x86.R_EBX);
-        push_long(old_sp);
-        push_long(M.x86.R_EBP);
-        push_long(M.x86.R_ESI);
-        push_long(M.x86.R_EDI);
+       u32 old_sp = M.x86.R_ESP;
+
+       push_long(M.x86.R_EAX);
+       push_long(M.x86.R_ECX);
+       push_long(M.x86.R_EDX);
+       push_long(M.x86.R_EBX);
+       push_long(old_sp);
+       push_long(M.x86.R_EBP);
+       push_long(M.x86.R_ESI);
+       push_long(M.x86.R_EDI);
     } else {
-        u16 old_sp = M.x86.R_SP;
-
-        push_word(M.x86.R_AX);
-        push_word(M.x86.R_CX);
-        push_word(M.x86.R_DX);
-        push_word(M.x86.R_BX);
-        push_word(old_sp);
-        push_word(M.x86.R_BP);
-        push_word(M.x86.R_SI);
-        push_word(M.x86.R_DI);
+       u16 old_sp = M.x86.R_SP;
+
+       push_word(M.x86.R_AX);
+       push_word(M.x86.R_CX);
+       push_word(M.x86.R_DX);
+       push_word(M.x86.R_BX);
+       push_word(old_sp);
+       push_word(M.x86.R_BP);
+       push_word(M.x86.R_SI);
+       push_word(M.x86.R_DI);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -825,36 +825,36 @@ void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF("POPAD\n");
+       DECODE_PRINTF("POPAD\n");
     } else {
-        DECODE_PRINTF("POPA\n");
+       DECODE_PRINTF("POPA\n");
     }
     TRACE_AND_STEP();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        M.x86.R_EDI = pop_long();
-        M.x86.R_ESI = pop_long();
-        M.x86.R_EBP = pop_long();
-        M.x86.R_ESP += 4;              /* skip ESP */
-        M.x86.R_EBX = pop_long();
-        M.x86.R_EDX = pop_long();
-        M.x86.R_ECX = pop_long();
-        M.x86.R_EAX = pop_long();
+       M.x86.R_EDI = pop_long();
+       M.x86.R_ESI = pop_long();
+       M.x86.R_EBP = pop_long();
+       M.x86.R_ESP += 4;              /* skip ESP */
+       M.x86.R_EBX = pop_long();
+       M.x86.R_EDX = pop_long();
+       M.x86.R_ECX = pop_long();
+       M.x86.R_EAX = pop_long();
     } else {
-        M.x86.R_DI = pop_word();
-        M.x86.R_SI = pop_word();
-        M.x86.R_BP = pop_word();
-        M.x86.R_SP += 2;               /* skip SP */
-        M.x86.R_BX = pop_word();
-        M.x86.R_DX = pop_word();
-        M.x86.R_CX = pop_word();
-        M.x86.R_AX = pop_word();
+       M.x86.R_DI = pop_word();
+       M.x86.R_SI = pop_word();
+       M.x86.R_BP = pop_word();
+       M.x86.R_SP += 2;               /* skip SP */
+       M.x86.R_BX = pop_word();
+       M.x86.R_DX = pop_word();
+       M.x86.R_CX = pop_word();
+       M.x86.R_AX = pop_word();
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
 }
 
-/*opcode 0x62   ILLEGAL OP, calls x86emuOp_illegal_op() */
-/*opcode 0x63   ILLEGAL OP, calls x86emuOp_illegal_op() */
+/*opcode 0x62  ILLEGAL OP, calls x86emuOp_illegal_op() */
+/*opcode 0x63  ILLEGAL OP, calls x86emuOp_illegal_op() */
 
 /****************************************************************************
 REMARKS:
@@ -928,16 +928,16 @@ void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1))
 
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        imm = fetch_long_imm();
+       imm = fetch_long_imm();
     } else {
-        imm = fetch_word_imm();
+       imm = fetch_word_imm();
     }
     DECODE_PRINTF2("PUSH\t%x\n", imm);
     TRACE_AND_STEP();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        push_long(imm);
+       push_long(imm);
     } else {
-        push_word((u16)imm);
+       push_word((u16)imm);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -956,95 +956,95 @@ void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("IMUL\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        srcoffset = decode_rmXX_address(mod, rl);
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg;
-            u32 srcval;
-            u32 res_lo,res_hi;
-            s32 imm;
-
-            destreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcval = fetch_data_long(srcoffset);
-            imm = fetch_long_imm();
-            DECODE_PRINTF2(",%d\n", (s32)imm);
-            TRACE_AND_STEP();
-            imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm);
-            if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) ||
-                (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) {
-                CLEAR_FLAG(F_CF);
-                CLEAR_FLAG(F_OF);
-            } else {
-                SET_FLAG(F_CF);
-                SET_FLAG(F_OF);
-            }
-            *destreg = (u32)res_lo;
-        } else {
-            u16 *destreg;
-            u16 srcval;
-            u32 res;
-            s16 imm;
-
-            destreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcval = fetch_data_word(srcoffset);
-            imm = fetch_word_imm();
-            DECODE_PRINTF2(",%d\n", (s32)imm);
-            TRACE_AND_STEP();
-            res = (s16)srcval * (s16)imm;
-            if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) ||
-                (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) {
-                CLEAR_FLAG(F_CF);
-                CLEAR_FLAG(F_OF);
-            } else {
-                SET_FLAG(F_CF);
-                SET_FLAG(F_OF);
-            }
-            *destreg = (u16)res;
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg,*srcreg;
-            u32 res_lo,res_hi;
-            s32 imm;
-
-            destreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_LONG_REGISTER(rl);
-            imm = fetch_long_imm();
-            DECODE_PRINTF2(",%d\n", (s32)imm);
-            TRACE_AND_STEP();
-            imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm);
-            if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) ||
-                (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) {
-                CLEAR_FLAG(F_CF);
-                CLEAR_FLAG(F_OF);
-            } else {
-                SET_FLAG(F_CF);
-                SET_FLAG(F_OF);
-            }
-            *destreg = (u32)res_lo;
-        } else {
-            u16 *destreg,*srcreg;
-            u32 res;
-            s16 imm;
-
-            destreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_WORD_REGISTER(rl);
-            imm = fetch_word_imm();
-            DECODE_PRINTF2(",%d\n", (s32)imm);
-            res = (s16)*srcreg * (s16)imm;
-            if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) ||
-                (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) {
-                CLEAR_FLAG(F_CF);
-                CLEAR_FLAG(F_OF);
-            } else {
-                SET_FLAG(F_CF);
-                SET_FLAG(F_OF);
-            }
-            *destreg = (u16)res;
-        }
+       srcoffset = decode_rmXX_address(mod, rl);
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg;
+           u32 srcval;
+           u32 res_lo,res_hi;
+           s32 imm;
+
+           destreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcval = fetch_data_long(srcoffset);
+           imm = fetch_long_imm();
+           DECODE_PRINTF2(",%d\n", (s32)imm);
+           TRACE_AND_STEP();
+           imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm);
+           if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) ||
+               (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) {
+               CLEAR_FLAG(F_CF);
+               CLEAR_FLAG(F_OF);
+           } else {
+               SET_FLAG(F_CF);
+               SET_FLAG(F_OF);
+           }
+           *destreg = (u32)res_lo;
+       } else {
+           u16 *destreg;
+           u16 srcval;
+           u32 res;
+           s16 imm;
+
+           destreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcval = fetch_data_word(srcoffset);
+           imm = fetch_word_imm();
+           DECODE_PRINTF2(",%d\n", (s32)imm);
+           TRACE_AND_STEP();
+           res = (s16)srcval * (s16)imm;
+           if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) ||
+               (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) {
+               CLEAR_FLAG(F_CF);
+               CLEAR_FLAG(F_OF);
+           } else {
+               SET_FLAG(F_CF);
+               SET_FLAG(F_OF);
+           }
+           *destreg = (u16)res;
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg,*srcreg;
+           u32 res_lo,res_hi;
+           s32 imm;
+
+           destreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_LONG_REGISTER(rl);
+           imm = fetch_long_imm();
+           DECODE_PRINTF2(",%d\n", (s32)imm);
+           TRACE_AND_STEP();
+           imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm);
+           if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) ||
+               (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) {
+               CLEAR_FLAG(F_CF);
+               CLEAR_FLAG(F_OF);
+           } else {
+               SET_FLAG(F_CF);
+               SET_FLAG(F_OF);
+           }
+           *destreg = (u32)res_lo;
+       } else {
+           u16 *destreg,*srcreg;
+           u32 res;
+           s16 imm;
+
+           destreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_WORD_REGISTER(rl);
+           imm = fetch_word_imm();
+           DECODE_PRINTF2(",%d\n", (s32)imm);
+           res = (s16)*srcreg * (s16)imm;
+           if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) ||
+               (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) {
+               CLEAR_FLAG(F_CF);
+               CLEAR_FLAG(F_OF);
+           } else {
+               SET_FLAG(F_CF);
+               SET_FLAG(F_OF);
+           }
+           *destreg = (u16)res;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1075,98 +1075,98 @@ void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
     uint srcoffset;
-    s8  imm;
+    s8 imm;
 
     START_OF_INSTR();
     DECODE_PRINTF("IMUL\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        srcoffset = decode_rmXX_address(mod, rl);
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg;
-            u32 srcval;
-            u32 res_lo,res_hi;
-
-            destreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcval = fetch_data_long(srcoffset);
-            imm = fetch_byte_imm();
-            DECODE_PRINTF2(",%d\n", (s32)imm);
-            TRACE_AND_STEP();
-            imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm);
-            if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) ||
-                (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) {
-                CLEAR_FLAG(F_CF);
-                CLEAR_FLAG(F_OF);
-            } else {
-                SET_FLAG(F_CF);
-                SET_FLAG(F_OF);
-            }
-            *destreg = (u32)res_lo;
-        } else {
-            u16 *destreg;
-            u16 srcval;
-            u32 res;
-
-            destreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcval = fetch_data_word(srcoffset);
-            imm = fetch_byte_imm();
-            DECODE_PRINTF2(",%d\n", (s32)imm);
-            TRACE_AND_STEP();
-            res = (s16)srcval * (s16)imm;
-            if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) ||
-                (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) {
-                CLEAR_FLAG(F_CF);
-                CLEAR_FLAG(F_OF);
-            } else {
-                SET_FLAG(F_CF);
-                SET_FLAG(F_OF);
-            }
-            *destreg = (u16)res;
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg,*srcreg;
-            u32 res_lo,res_hi;
-
-            destreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_LONG_REGISTER(rl);
-            imm = fetch_byte_imm();
-            DECODE_PRINTF2(",%d\n", (s32)imm);
-            TRACE_AND_STEP();
-            imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm);
-            if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) ||
-                (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) {
-                CLEAR_FLAG(F_CF);
-                CLEAR_FLAG(F_OF);
-            } else {
-                SET_FLAG(F_CF);
-                SET_FLAG(F_OF);
-            }
-            *destreg = (u32)res_lo;
-        } else {
-            u16 *destreg,*srcreg;
-            u32 res;
-
-            destreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_WORD_REGISTER(rl);
-            imm = fetch_byte_imm();
-            DECODE_PRINTF2(",%d\n", (s32)imm);
-            TRACE_AND_STEP();
-            res = (s16)*srcreg * (s16)imm;
-            if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) ||
-                (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) {
-                CLEAR_FLAG(F_CF);
-                CLEAR_FLAG(F_OF);
-            } else {
-                SET_FLAG(F_CF);
-                SET_FLAG(F_OF);
-            }
-            *destreg = (u16)res;
-        }
+       srcoffset = decode_rmXX_address(mod, rl);
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg;
+           u32 srcval;
+           u32 res_lo,res_hi;
+
+           destreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcval = fetch_data_long(srcoffset);
+           imm = fetch_byte_imm();
+           DECODE_PRINTF2(",%d\n", (s32)imm);
+           TRACE_AND_STEP();
+           imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm);
+           if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) ||
+               (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) {
+               CLEAR_FLAG(F_CF);
+               CLEAR_FLAG(F_OF);
+           } else {
+               SET_FLAG(F_CF);
+               SET_FLAG(F_OF);
+           }
+           *destreg = (u32)res_lo;
+       } else {
+           u16 *destreg;
+           u16 srcval;
+           u32 res;
+
+           destreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcval = fetch_data_word(srcoffset);
+           imm = fetch_byte_imm();
+           DECODE_PRINTF2(",%d\n", (s32)imm);
+           TRACE_AND_STEP();
+           res = (s16)srcval * (s16)imm;
+           if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) ||
+               (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) {
+               CLEAR_FLAG(F_CF);
+               CLEAR_FLAG(F_OF);
+           } else {
+               SET_FLAG(F_CF);
+               SET_FLAG(F_OF);
+           }
+           *destreg = (u16)res;
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg,*srcreg;
+           u32 res_lo,res_hi;
+
+           destreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_LONG_REGISTER(rl);
+           imm = fetch_byte_imm();
+           DECODE_PRINTF2(",%d\n", (s32)imm);
+           TRACE_AND_STEP();
+           imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm);
+           if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) ||
+               (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) {
+               CLEAR_FLAG(F_CF);
+               CLEAR_FLAG(F_OF);
+           } else {
+               SET_FLAG(F_CF);
+               SET_FLAG(F_OF);
+           }
+           *destreg = (u32)res_lo;
+       } else {
+           u16 *destreg,*srcreg;
+           u32 res;
+
+           destreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_WORD_REGISTER(rl);
+           imm = fetch_byte_imm();
+           DECODE_PRINTF2(",%d\n", (s32)imm);
+           TRACE_AND_STEP();
+           res = (s16)*srcreg * (s16)imm;
+           if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) ||
+               (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) {
+               CLEAR_FLAG(F_CF);
+               CLEAR_FLAG(F_OF);
+           } else {
+               SET_FLAG(F_CF);
+               SET_FLAG(F_OF);
+           }
+           *destreg = (u16)res;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1194,11 +1194,11 @@ void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF("INSD\n");
-        ins(4);
+       DECODE_PRINTF("INSD\n");
+       ins(4);
     } else {
-        DECODE_PRINTF("INSW\n");
-        ins(2);
+       DECODE_PRINTF("INSW\n");
+       ins(2);
     }
     TRACE_AND_STEP();
     DECODE_CLEAR_SEGOVR();
@@ -1227,11 +1227,11 @@ void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF("OUTSD\n");
-        outs(4);
+       DECODE_PRINTF("OUTSD\n");
+       outs(4);
     } else {
-        DECODE_PRINTF("OUTSW\n");
-        outs(2);
+       DECODE_PRINTF("OUTSW\n");
+       outs(2);
     }
     TRACE_AND_STEP();
     DECODE_CLEAR_SEGOVR();
@@ -1258,7 +1258,7 @@ void x86emuOp_jump_near_cond(u8 op1)
     DECODE_PRINTF2("%x\n", target);
     TRACE_AND_STEP();
     if (cond)
-        M.x86.R_IP = target;
+       M.x86.R_IP = target;
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
 }
@@ -1276,7 +1276,7 @@ void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
     u8 destval;
 
     /*
-     * Weirdo special case instruction format.  Part of the opcode
+     * Weirdo special case instruction format. Part of the opcode
      * held below in "RH".  Doubly nested case would result, except
      * that the decoded instruction
      */
@@ -1284,61 +1284,61 @@ void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
     FETCH_DECODE_MODRM(mod, rh, rl);
 #ifdef DEBUG
     if (DEBUG_DECODE()) {
-        /* XXX DECODE_PRINTF may be changed to something more
-           general, so that it is important to leave the strings
-           in the same format, even though the result is that the
-           above test is done twice. */
-
-        switch (rh) {
-        case 0:
-            DECODE_PRINTF("ADD\t");
-            break;
-        case 1:
-            DECODE_PRINTF("OR\t");
-            break;
-        case 2:
-            DECODE_PRINTF("ADC\t");
-            break;
-        case 3:
-            DECODE_PRINTF("SBB\t");
-            break;
-        case 4:
-            DECODE_PRINTF("AND\t");
-            break;
-        case 5:
-            DECODE_PRINTF("SUB\t");
-            break;
-        case 6:
-            DECODE_PRINTF("XOR\t");
-            break;
-        case 7:
-            DECODE_PRINTF("CMP\t");
-            break;
-        }
+       /* XXX DECODE_PRINTF may be changed to something more
+          general, so that it is important to leave the strings
+          in the same format, even though the result is that the
+          above test is done twice. */
+
+       switch (rh) {
+       case 0:
+           DECODE_PRINTF("ADD\t");
+           break;
+       case 1:
+           DECODE_PRINTF("OR\t");
+           break;
+       case 2:
+           DECODE_PRINTF("ADC\t");
+           break;
+       case 3:
+           DECODE_PRINTF("SBB\t");
+           break;
+       case 4:
+           DECODE_PRINTF("AND\t");
+           break;
+       case 5:
+           DECODE_PRINTF("SUB\t");
+           break;
+       case 6:
+           DECODE_PRINTF("XOR\t");
+           break;
+       case 7:
+           DECODE_PRINTF("CMP\t");
+           break;
+       }
     }
 #endif
     /* know operation, decode the mod byte to find the addressing
        mode. */
     if (mod < 3) {
-        DECODE_PRINTF("BYTE PTR ");
-        destoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF(",");
-        destval = fetch_data_byte(destoffset);
-        imm = fetch_byte_imm();
-        DECODE_PRINTF2("%x\n", imm);
-        TRACE_AND_STEP();
-        destval = (*genop_byte_operation[rh]) (destval, imm);
-        if (rh != 7)
-            store_data_byte(destoffset, destval);
-    } else {                     /* register to register */
-        destreg = DECODE_RM_BYTE_REGISTER(rl);
-        DECODE_PRINTF(",");
-        imm = fetch_byte_imm();
-        DECODE_PRINTF2("%x\n", imm);
-        TRACE_AND_STEP();
-        destval = (*genop_byte_operation[rh]) (*destreg, imm);
-        if (rh != 7)
-            *destreg = destval;
+       DECODE_PRINTF("BYTE PTR ");
+       destoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF(",");
+       destval = fetch_data_byte(destoffset);
+       imm = fetch_byte_imm();
+       DECODE_PRINTF2("%x\n", imm);
+       TRACE_AND_STEP();
+       destval = (*genop_byte_operation[rh]) (destval, imm);
+       if (rh != 7)
+           store_data_byte(destoffset, destval);
+    } else {                    /* register to register */
+       destreg = DECODE_RM_BYTE_REGISTER(rl);
+       DECODE_PRINTF(",");
+       imm = fetch_byte_imm();
+       DECODE_PRINTF2("%x\n", imm);
+       TRACE_AND_STEP();
+       destval = (*genop_byte_operation[rh]) (*destreg, imm);
+       if (rh != 7)
+           *destreg = destval;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1354,7 +1354,7 @@ void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1))
     uint destoffset;
 
     /*
-     * Weirdo special case instruction format.  Part of the opcode
+     * Weirdo special case instruction format. Part of the opcode
      * held below in "RH".  Doubly nested case would result, except
      * that the decoded instruction
      */
@@ -1362,37 +1362,37 @@ void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1))
     FETCH_DECODE_MODRM(mod, rh, rl);
 #ifdef DEBUG
     if (DEBUG_DECODE()) {
-        /* XXX DECODE_PRINTF may be changed to something more
-           general, so that it is important to leave the strings
-           in the same format, even though the result is that the
-           above test is done twice. */
-
-        switch (rh) {
-        case 0:
-            DECODE_PRINTF("ADD\t");
-            break;
-        case 1:
-            DECODE_PRINTF("OR\t");
-            break;
-        case 2:
-            DECODE_PRINTF("ADC\t");
-            break;
-        case 3:
-            DECODE_PRINTF("SBB\t");
-            break;
-        case 4:
-            DECODE_PRINTF("AND\t");
-            break;
-        case 5:
-            DECODE_PRINTF("SUB\t");
-            break;
-        case 6:
-            DECODE_PRINTF("XOR\t");
-            break;
-        case 7:
-            DECODE_PRINTF("CMP\t");
-            break;
-        }
+       /* XXX DECODE_PRINTF may be changed to something more
+          general, so that it is important to leave the strings
+          in the same format, even though the result is that the
+          above test is done twice. */
+
+       switch (rh) {
+       case 0:
+           DECODE_PRINTF("ADD\t");
+           break;
+       case 1:
+           DECODE_PRINTF("OR\t");
+           break;
+       case 2:
+           DECODE_PRINTF("ADC\t");
+           break;
+       case 3:
+           DECODE_PRINTF("SBB\t");
+           break;
+       case 4:
+           DECODE_PRINTF("AND\t");
+           break;
+       case 5:
+           DECODE_PRINTF("SUB\t");
+           break;
+       case 6:
+           DECODE_PRINTF("XOR\t");
+           break;
+       case 7:
+           DECODE_PRINTF("CMP\t");
+           break;
+       }
     }
 #endif
     /*
@@ -1400,57 +1400,57 @@ void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1))
      * mode.
      */
     if (mod < 3) {
-        DECODE_PRINTF("DWORD PTR ");
-        destoffset = decode_rmXX_address(mod, rl);
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 destval,imm;
-
-            DECODE_PRINTF(",");
-            destval = fetch_data_long(destoffset);
-            imm = fetch_long_imm();
-            DECODE_PRINTF2("%x\n", imm);
-            TRACE_AND_STEP();
-            destval = (*genop_long_operation[rh]) (destval, imm);
-            if (rh != 7)
-                store_data_long(destoffset, destval);
-        } else {
-            u16 destval,imm;
-
-            DECODE_PRINTF(",");
-            destval = fetch_data_word(destoffset);
-            imm = fetch_word_imm();
-            DECODE_PRINTF2("%x\n", imm);
-            TRACE_AND_STEP();
-            destval = (*genop_word_operation[rh]) (destval, imm);
-            if (rh != 7)
-                store_data_word(destoffset, destval);
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg;
-            u32 destval,imm;
-
-            destreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF(",");
-            imm = fetch_long_imm();
-            DECODE_PRINTF2("%x\n", imm);
-            TRACE_AND_STEP();
-            destval = (*genop_long_operation[rh]) (*destreg, imm);
-            if (rh != 7)
-                *destreg = destval;
-        } else {
-            u16 *destreg;
-            u16 destval,imm;
-
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF(",");
-            imm = fetch_word_imm();
-            DECODE_PRINTF2("%x\n", imm);
-            TRACE_AND_STEP();
-            destval = (*genop_word_operation[rh]) (*destreg, imm);
-            if (rh != 7)
-                *destreg = destval;
-        }
+       DECODE_PRINTF("DWORD PTR ");
+       destoffset = decode_rmXX_address(mod, rl);
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 destval,imm;
+
+           DECODE_PRINTF(",");
+           destval = fetch_data_long(destoffset);
+           imm = fetch_long_imm();
+           DECODE_PRINTF2("%x\n", imm);
+           TRACE_AND_STEP();
+           destval = (*genop_long_operation[rh]) (destval, imm);
+           if (rh != 7)
+               store_data_long(destoffset, destval);
+       } else {
+           u16 destval,imm;
+
+           DECODE_PRINTF(",");
+           destval = fetch_data_word(destoffset);
+           imm = fetch_word_imm();
+           DECODE_PRINTF2("%x\n", imm);
+           TRACE_AND_STEP();
+           destval = (*genop_word_operation[rh]) (destval, imm);
+           if (rh != 7)
+               store_data_word(destoffset, destval);
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg;
+           u32 destval,imm;
+
+           destreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF(",");
+           imm = fetch_long_imm();
+           DECODE_PRINTF2("%x\n", imm);
+           TRACE_AND_STEP();
+           destval = (*genop_long_operation[rh]) (*destreg, imm);
+           if (rh != 7)
+               *destreg = destval;
+       } else {
+           u16 *destreg;
+           u16 destval,imm;
+
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF(",");
+           imm = fetch_word_imm();
+           DECODE_PRINTF2("%x\n", imm);
+           TRACE_AND_STEP();
+           destval = (*genop_word_operation[rh]) (*destreg, imm);
+           if (rh != 7)
+               *destreg = destval;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1469,7 +1469,7 @@ void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
     u8 destval;
 
     /*
-     * Weirdo special case instruction format.  Part of the opcode
+     * Weirdo special case instruction format. Part of the opcode
      * held below in "RH".  Doubly nested case would result, except
      * that the decoded instruction Similar to opcode 81, except that
      * the immediate byte is sign extended to a word length.
@@ -1478,58 +1478,58 @@ void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
     FETCH_DECODE_MODRM(mod, rh, rl);
 #ifdef DEBUG
     if (DEBUG_DECODE()) {
-        /* XXX DECODE_PRINTF may be changed to something more
-           general, so that it is important to leave the strings
-           in the same format, even though the result is that the
-           above test is done twice. */
-        switch (rh) {
-        case 0:
-            DECODE_PRINTF("ADD\t");
-            break;
-        case 1:
-            DECODE_PRINTF("OR\t");
-            break;
-        case 2:
-            DECODE_PRINTF("ADC\t");
-            break;
-        case 3:
-            DECODE_PRINTF("SBB\t");
-            break;
-        case 4:
-            DECODE_PRINTF("AND\t");
-            break;
-        case 5:
-            DECODE_PRINTF("SUB\t");
-            break;
-        case 6:
-            DECODE_PRINTF("XOR\t");
-            break;
-        case 7:
-            DECODE_PRINTF("CMP\t");
-            break;
-        }
+       /* XXX DECODE_PRINTF may be changed to something more
+          general, so that it is important to leave the strings
+          in the same format, even though the result is that the
+          above test is done twice. */
+       switch (rh) {
+       case 0:
+           DECODE_PRINTF("ADD\t");
+           break;
+       case 1:
+           DECODE_PRINTF("OR\t");
+           break;
+       case 2:
+           DECODE_PRINTF("ADC\t");
+           break;
+       case 3:
+           DECODE_PRINTF("SBB\t");
+           break;
+       case 4:
+           DECODE_PRINTF("AND\t");
+           break;
+       case 5:
+           DECODE_PRINTF("SUB\t");
+           break;
+       case 6:
+           DECODE_PRINTF("XOR\t");
+           break;
+       case 7:
+           DECODE_PRINTF("CMP\t");
+           break;
+       }
     }
 #endif
     /* know operation, decode the mod byte to find the addressing
        mode. */
     if (mod < 3) {
-        DECODE_PRINTF("BYTE PTR ");
-        destoffset = decode_rmXX_address(mod, rl);
-        destval = fetch_data_byte(destoffset);
-        imm = fetch_byte_imm();
-        DECODE_PRINTF2(",%x\n", imm);
-        TRACE_AND_STEP();
-        destval = (*genop_byte_operation[rh]) (destval, imm);
-        if (rh != 7)
-            store_data_byte(destoffset, destval);
-    } else {                     /* register to register */
-        destreg = DECODE_RM_BYTE_REGISTER(rl);
-        imm = fetch_byte_imm();
-        DECODE_PRINTF2(",%x\n", imm);
-        TRACE_AND_STEP();
-        destval = (*genop_byte_operation[rh]) (*destreg, imm);
-        if (rh != 7)
-            *destreg = destval;
+       DECODE_PRINTF("BYTE PTR ");
+       destoffset = decode_rmXX_address(mod, rl);
+       destval = fetch_data_byte(destoffset);
+       imm = fetch_byte_imm();
+       DECODE_PRINTF2(",%x\n", imm);
+       TRACE_AND_STEP();
+       destval = (*genop_byte_operation[rh]) (destval, imm);
+       if (rh != 7)
+           store_data_byte(destoffset, destval);
+    } else {                    /* register to register */
+       destreg = DECODE_RM_BYTE_REGISTER(rl);
+       imm = fetch_byte_imm();
+       DECODE_PRINTF2(",%x\n", imm);
+       TRACE_AND_STEP();
+       destval = (*genop_byte_operation[rh]) (*destreg, imm);
+       if (rh != 7)
+           *destreg = destval;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1545,7 +1545,7 @@ void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1))
     uint destoffset;
 
     /*
-     * Weirdo special case instruction format.  Part of the opcode
+     * Weirdo special case instruction format. Part of the opcode
      * held below in "RH".  Doubly nested case would result, except
      * that the decoded instruction Similar to opcode 81, except that
      * the immediate byte is sign extended to a word length.
@@ -1554,89 +1554,89 @@ void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1))
     FETCH_DECODE_MODRM(mod, rh, rl);
 #ifdef DEBUG
     if (DEBUG_DECODE()) {
-        /* XXX DECODE_PRINTF may be changed to something more
-           general, so that it is important to leave the strings
-           in the same format, even though the result is that the
-           above test is done twice. */
+       /* XXX DECODE_PRINTF may be changed to something more
+          general, so that it is important to leave the strings
+          in the same format, even though the result is that the
+          above test is done twice. */
        switch (rh) {
-        case 0:
-            DECODE_PRINTF("ADD\t");
-            break;
-        case 1:
-            DECODE_PRINTF("OR\t");
-            break;
-        case 2:
-            DECODE_PRINTF("ADC\t");
-            break;
-        case 3:
-            DECODE_PRINTF("SBB\t");
-            break;
-        case 4:
-            DECODE_PRINTF("AND\t");
-            break;
-        case 5:
-            DECODE_PRINTF("SUB\t");
-            break;
-        case 6:
-            DECODE_PRINTF("XOR\t");
-            break;
-        case 7:
-            DECODE_PRINTF("CMP\t");
-            break;
-        }
+       case 0:
+           DECODE_PRINTF("ADD\t");
+           break;
+       case 1:
+           DECODE_PRINTF("OR\t");
+           break;
+       case 2:
+           DECODE_PRINTF("ADC\t");
+           break;
+       case 3:
+           DECODE_PRINTF("SBB\t");
+           break;
+       case 4:
+           DECODE_PRINTF("AND\t");
+           break;
+       case 5:
+           DECODE_PRINTF("SUB\t");
+           break;
+       case 6:
+           DECODE_PRINTF("XOR\t");
+           break;
+       case 7:
+           DECODE_PRINTF("CMP\t");
+           break;
+       }
     }
 #endif
     /* know operation, decode the mod byte to find the addressing
        mode. */
     if (mod < 3) {
-        DECODE_PRINTF("DWORD PTR ");
-        destoffset = decode_rmXX_address(mod,rl);
-
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 destval,imm;
-
-            destval = fetch_data_long(destoffset);
-            imm = (s8) fetch_byte_imm();
-            DECODE_PRINTF2(",%x\n", imm);
-            TRACE_AND_STEP();
-            destval = (*genop_long_operation[rh]) (destval, imm);
-            if (rh != 7)
-                store_data_long(destoffset, destval);
-        } else {
-            u16 destval,imm;
-
-            destval = fetch_data_word(destoffset);
-            imm = (s8) fetch_byte_imm();
-            DECODE_PRINTF2(",%x\n", imm);
-            TRACE_AND_STEP();
-            destval = (*genop_word_operation[rh]) (destval, imm);
-            if (rh != 7)
-                store_data_word(destoffset, destval);
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg;
-            u32 destval,imm;
-
-            destreg = DECODE_RM_LONG_REGISTER(rl);
-            imm = (s8) fetch_byte_imm();
-            DECODE_PRINTF2(",%x\n", imm);
-            TRACE_AND_STEP();
-            destval = (*genop_long_operation[rh]) (*destreg, imm);
-            if (rh != 7)
-                *destreg = destval;
-        } else {
-            u16 *destreg;
-            u16 destval,imm;
-
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-            imm = (s8) fetch_byte_imm();
-            DECODE_PRINTF2(",%x\n", imm);
-            TRACE_AND_STEP();
-            destval = (*genop_word_operation[rh]) (*destreg, imm);
-            if (rh != 7)
-                *destreg = destval;
-        }
+       DECODE_PRINTF("DWORD PTR ");
+       destoffset = decode_rmXX_address(mod,rl);
+
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 destval,imm;
+
+           destval = fetch_data_long(destoffset);
+           imm = (s8) fetch_byte_imm();
+           DECODE_PRINTF2(",%x\n", imm);
+           TRACE_AND_STEP();
+           destval = (*genop_long_operation[rh]) (destval, imm);
+           if (rh != 7)
+               store_data_long(destoffset, destval);
+       } else {
+           u16 destval,imm;
+
+           destval = fetch_data_word(destoffset);
+           imm = (s8) fetch_byte_imm();
+           DECODE_PRINTF2(",%x\n", imm);
+           TRACE_AND_STEP();
+           destval = (*genop_word_operation[rh]) (destval, imm);
+           if (rh != 7)
+               store_data_word(destoffset, destval);
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg;
+           u32 destval,imm;
+
+           destreg = DECODE_RM_LONG_REGISTER(rl);
+           imm = (s8) fetch_byte_imm();
+           DECODE_PRINTF2(",%x\n", imm);
+           TRACE_AND_STEP();
+           destval = (*genop_long_operation[rh]) (*destreg, imm);
+           if (rh != 7)
+               *destreg = destval;
+       } else {
+           u16 *destreg;
+           u16 destval,imm;
+
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+           imm = (s8) fetch_byte_imm();
+           DECODE_PRINTF2(",%x\n", imm);
+           TRACE_AND_STEP();
+           destval = (*genop_word_operation[rh]) (*destreg, imm);
+           if (rh != 7)
+               *destreg = destval;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1657,20 +1657,20 @@ void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("TEST\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        destoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF(",");
-        destval = fetch_data_byte(destoffset);
-        srcreg = DECODE_RM_BYTE_REGISTER(rh);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        test_byte(destval, *srcreg);
-    } else {                     /* register to register */
-        destreg = DECODE_RM_BYTE_REGISTER(rl);
-        DECODE_PRINTF(",");
-        srcreg = DECODE_RM_BYTE_REGISTER(rh);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        test_byte(*destreg, *srcreg);
+       destoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF(",");
+       destval = fetch_data_byte(destoffset);
+       srcreg = DECODE_RM_BYTE_REGISTER(rh);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       test_byte(destval, *srcreg);
+    } else {                    /* register to register */
+       destreg = DECODE_RM_BYTE_REGISTER(rl);
+       DECODE_PRINTF(",");
+       srcreg = DECODE_RM_BYTE_REGISTER(rh);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       test_byte(*destreg, *srcreg);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1689,48 +1689,48 @@ void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("TEST\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        destoffset = decode_rmXX_address(mod, rl);
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 destval;
-            u32 *srcreg;
-
-            DECODE_PRINTF(",");
-            destval = fetch_data_long(destoffset);
-            srcreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            test_long(destval, *srcreg);
-        } else {
-            u16 destval;
-            u16 *srcreg;
-
-            DECODE_PRINTF(",");
-            destval = fetch_data_word(destoffset);
-            srcreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            test_word(destval, *srcreg);
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg,*srcreg;
-
-            destreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            test_long(*destreg, *srcreg);
-        } else {
-            u16 *destreg,*srcreg;
-
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            test_word(*destreg, *srcreg);
-        }
+       destoffset = decode_rmXX_address(mod, rl);
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 destval;
+           u32 *srcreg;
+
+           DECODE_PRINTF(",");
+           destval = fetch_data_long(destoffset);
+           srcreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           test_long(destval, *srcreg);
+       } else {
+           u16 destval;
+           u16 *srcreg;
+
+           DECODE_PRINTF(",");
+           destval = fetch_data_word(destoffset);
+           srcreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           test_word(destval, *srcreg);
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg,*srcreg;
+
+           destreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           test_long(*destreg, *srcreg);
+       } else {
+           u16 *destreg,*srcreg;
+
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           test_word(*destreg, *srcreg);
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1752,25 +1752,25 @@ void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("XCHG\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        destoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF(",");
-        destval = fetch_data_byte(destoffset);
-        srcreg = DECODE_RM_BYTE_REGISTER(rh);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        tmp = *srcreg;
-        *srcreg = destval;
-        destval = tmp;
-        store_data_byte(destoffset, destval);
-    } else {                     /* register to register */
-        destreg = DECODE_RM_BYTE_REGISTER(rl);
-        DECODE_PRINTF(",");
-        srcreg = DECODE_RM_BYTE_REGISTER(rh);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        tmp = *srcreg;
-        *srcreg = *destreg;
-        *destreg = tmp;
+       destoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF(",");
+       destval = fetch_data_byte(destoffset);
+       srcreg = DECODE_RM_BYTE_REGISTER(rh);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       tmp = *srcreg;
+       *srcreg = destval;
+       destval = tmp;
+       store_data_byte(destoffset, destval);
+    } else {                    /* register to register */
+       destreg = DECODE_RM_BYTE_REGISTER(rl);
+       DECODE_PRINTF(",");
+       srcreg = DECODE_RM_BYTE_REGISTER(rh);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       tmp = *srcreg;
+       *srcreg = *destreg;
+       *destreg = tmp;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1789,59 +1789,59 @@ void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("XCHG\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        destoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF(",");
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *srcreg;
-            u32 destval,tmp;
-
-            destval = fetch_data_long(destoffset);
-            srcreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            tmp = *srcreg;
-            *srcreg = destval;
-            destval = tmp;
-            store_data_long(destoffset, destval);
-        } else {
-            u16 *srcreg;
-            u16 destval,tmp;
-
-            destval = fetch_data_word(destoffset);
-            srcreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            tmp = *srcreg;
-            *srcreg = destval;
-            destval = tmp;
-            store_data_word(destoffset, destval);
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg,*srcreg;
-            u32 tmp;
-
-            destreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            tmp = *srcreg;
-            *srcreg = *destreg;
-            *destreg = tmp;
-        } else {
-            u16 *destreg,*srcreg;
-            u16 tmp;
-
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            tmp = *srcreg;
-            *srcreg = *destreg;
-            *destreg = tmp;
-        }
+       destoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF(",");
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *srcreg;
+           u32 destval,tmp;
+
+           destval = fetch_data_long(destoffset);
+           srcreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           tmp = *srcreg;
+           *srcreg = destval;
+           destval = tmp;
+           store_data_long(destoffset, destval);
+       } else {
+           u16 *srcreg;
+           u16 destval,tmp;
+
+           destval = fetch_data_word(destoffset);
+           srcreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           tmp = *srcreg;
+           *srcreg = destval;
+           destval = tmp;
+           store_data_word(destoffset, destval);
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg,*srcreg;
+           u32 tmp;
+
+           destreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           tmp = *srcreg;
+           *srcreg = *destreg;
+           *destreg = tmp;
+       } else {
+           u16 *destreg,*srcreg;
+           u16 tmp;
+
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           tmp = *srcreg;
+           *srcreg = *destreg;
+           *destreg = tmp;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1861,19 +1861,19 @@ void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("MOV\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        destoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF(",");
-        srcreg = DECODE_RM_BYTE_REGISTER(rh);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        store_data_byte(destoffset, *srcreg);
-    } else {                     /* register to register */
-        destreg = DECODE_RM_BYTE_REGISTER(rl);
-        DECODE_PRINTF(",");
-        srcreg = DECODE_RM_BYTE_REGISTER(rh);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *destreg = *srcreg;
+       destoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF(",");
+       srcreg = DECODE_RM_BYTE_REGISTER(rh);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       store_data_byte(destoffset, *srcreg);
+    } else {                    /* register to register */
+       destreg = DECODE_RM_BYTE_REGISTER(rl);
+       DECODE_PRINTF(",");
+       srcreg = DECODE_RM_BYTE_REGISTER(rh);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *destreg = *srcreg;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1892,44 +1892,44 @@ void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("MOV\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        destoffset = decode_rmXX_address(mod, rl);
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *srcreg;
-
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            store_data_long(destoffset, *srcreg);
-        } else {
-            u16 *srcreg;
-
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            store_data_word(destoffset, *srcreg);
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg,*srcreg;
-
-            destreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = *srcreg;
-        } else {
-            u16 *destreg,*srcreg;
-
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = *srcreg;
-        }
+       destoffset = decode_rmXX_address(mod, rl);
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *srcreg;
+
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           store_data_long(destoffset, *srcreg);
+       } else {
+           u16 *srcreg;
+
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           store_data_word(destoffset, *srcreg);
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg,*srcreg;
+
+           destreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = *srcreg;
+       } else {
+           u16 *destreg,*srcreg;
+
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = *srcreg;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1950,20 +1950,20 @@ void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("MOV\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        destreg = DECODE_RM_BYTE_REGISTER(rh);
-        DECODE_PRINTF(",");
-        srcoffset = decode_rmXX_address(mod, rl);
-        srcval = fetch_data_byte(srcoffset);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *destreg = srcval;
-    } else {                     /* register to register */
-        destreg = DECODE_RM_BYTE_REGISTER(rh);
-        DECODE_PRINTF(",");
-        srcreg = DECODE_RM_BYTE_REGISTER(rl);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *destreg = *srcreg;
+       destreg = DECODE_RM_BYTE_REGISTER(rh);
+       DECODE_PRINTF(",");
+       srcoffset = decode_rmXX_address(mod, rl);
+       srcval = fetch_data_byte(srcoffset);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *destreg = srcval;
+    } else {                    /* register to register */
+       destreg = DECODE_RM_BYTE_REGISTER(rh);
+       DECODE_PRINTF(",");
+       srcreg = DECODE_RM_BYTE_REGISTER(rl);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *destreg = *srcreg;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1982,49 +1982,49 @@ void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("MOV\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg;
-            u32 srcval;
-
-            destreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcoffset = decode_rmXX_address(mod, rl);
-            srcval = fetch_data_long(srcoffset);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = srcval;
-        } else {
-            u16 *destreg;
-            u16 srcval;
-
-            destreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcoffset = decode_rmXX_address(mod, rl);
-            srcval = fetch_data_word(srcoffset);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = srcval;
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg, *srcreg;
-
-            destreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = *srcreg;
-        } else {
-            u16 *destreg, *srcreg;
-
-            destreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = *srcreg;
-        }
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg;
+           u32 srcval;
+
+           destreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcoffset = decode_rmXX_address(mod, rl);
+           srcval = fetch_data_long(srcoffset);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = srcval;
+       } else {
+           u16 *destreg;
+           u16 srcval;
+
+           destreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcoffset = decode_rmXX_address(mod, rl);
+           srcval = fetch_data_word(srcoffset);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = srcval;
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg, *srcreg;
+
+           destreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = *srcreg;
+       } else {
+           u16 *destreg, *srcreg;
+
+           destreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = *srcreg;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2045,20 +2045,20 @@ void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("MOV\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        destoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF(",");
-        srcreg = decode_rm_seg_register(rh);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        destval = *srcreg;
-        store_data_word(destoffset, destval);
-    } else {                     /* register to register */
-        destreg = DECODE_RM_WORD_REGISTER(rl);
-        DECODE_PRINTF(",");
-        srcreg = decode_rm_seg_register(rh);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *destreg = *srcreg;
+       destoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF(",");
+       srcreg = decode_rm_seg_register(rh);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       destval = *srcreg;
+       store_data_word(destoffset, destval);
+    } else {                    /* register to register */
+       destreg = DECODE_RM_WORD_REGISTER(rl);
+       DECODE_PRINTF(",");
+       srcreg = decode_rm_seg_register(rh);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *destreg = *srcreg;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2077,20 +2077,20 @@ void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1))
 /*
  * TODO: Need to handle address size prefix!
  *
- * lea  eax,[eax+ebx*2] ??
+ * lea eax,[eax+ebx*2] ??
  */
 
     START_OF_INSTR();
     DECODE_PRINTF("LEA\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        srcreg = DECODE_RM_WORD_REGISTER(rh);
-        DECODE_PRINTF(",");
-        destoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *srcreg = (u16)destoffset;
-        }
+       srcreg = DECODE_RM_WORD_REGISTER(rh);
+       DECODE_PRINTF(",");
+       destoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *srcreg = (u16)destoffset;
+       }
     /* } else { undefined.  Do nothing. } */
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2111,20 +2111,20 @@ void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("MOV\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        destreg = decode_rm_seg_register(rh);
-        DECODE_PRINTF(",");
-        srcoffset = decode_rmXX_address(mod, rl);
-        srcval = fetch_data_word(srcoffset);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *destreg = srcval;
-    } else {                     /* register to register */
-        destreg = decode_rm_seg_register(rh);
-        DECODE_PRINTF(",");
-        srcreg = DECODE_RM_WORD_REGISTER(rl);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *destreg = *srcreg;
+       destreg = decode_rm_seg_register(rh);
+       DECODE_PRINTF(",");
+       srcoffset = decode_rmXX_address(mod, rl);
+       srcval = fetch_data_word(srcoffset);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *destreg = srcval;
+    } else {                    /* register to register */
+       destreg = decode_rm_seg_register(rh);
+       DECODE_PRINTF(",");
+       srcreg = DECODE_RM_WORD_REGISTER(rl);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *destreg = *srcreg;
     }
     /*
      * Clean up, and reset all the R_xSP pointers to the correct
@@ -2149,42 +2149,42 @@ void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("POP\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (rh != 0) {
-        DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
-        HALT_SYS();
+       DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
+       HALT_SYS();
     }
     if (mod < 3) {
-        destoffset = decode_rmXX_address(mod, rl);
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 destval;
-
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            destval = pop_long();
-            store_data_long(destoffset, destval);
-        } else {
-            u16 destval;
-
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            destval = pop_word();
-            store_data_word(destoffset, destval);
-        }
-    } else {                    /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg;
-
-            destreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = pop_long();
-        } else {
-            u16 *destreg;
-
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = pop_word();
-        }
+       destoffset = decode_rmXX_address(mod, rl);
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 destval;
+
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           destval = pop_long();
+           store_data_long(destoffset, destval);
+       } else {
+           u16 destval;
+
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           destval = pop_word();
+           store_data_word(destoffset, destval);
+       }
+    } else {                   /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg;
+
+           destreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = pop_long();
+       } else {
+           u16 *destreg;
+
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = pop_word();
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2216,23 +2216,23 @@ void x86emuOp_xchg_word_AX_register(u8 X86EMU_UNUSED(op1))
     START_OF_INSTR();
 
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        u32 *reg32;
-        DECODE_PRINTF("XCHG\tEAX,");
-        reg32 = DECODE_RM_LONG_REGISTER(op1);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        tmp = M.x86.R_EAX;
-        M.x86.R_EAX = *reg32;
-        *reg32 = tmp;
+       u32 *reg32;
+       DECODE_PRINTF("XCHG\tEAX,");
+       reg32 = DECODE_RM_LONG_REGISTER(op1);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       tmp = M.x86.R_EAX;
+       M.x86.R_EAX = *reg32;
+       *reg32 = tmp;
     } else {
-        u16 *reg16;
-        DECODE_PRINTF("XCHG\tAX,");
-        reg16 = DECODE_RM_WORD_REGISTER(op1);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        tmp = M.x86.R_AX;
-        M.x86.R_EAX = *reg16;
-        *reg16 = (u16)tmp;
+       u16 *reg16;
+       DECODE_PRINTF("XCHG\tAX,");
+       reg16 = DECODE_RM_WORD_REGISTER(op1);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       tmp = M.x86.R_AX;
+       M.x86.R_EAX = *reg16;
+       *reg16 = (u16)tmp;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2246,23 +2246,23 @@ void x86emuOp_cbw(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF("CWDE\n");
+       DECODE_PRINTF("CWDE\n");
     } else {
-        DECODE_PRINTF("CBW\n");
+       DECODE_PRINTF("CBW\n");
     }
     TRACE_AND_STEP();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        if (M.x86.R_AX & 0x8000) {
-            M.x86.R_EAX |= 0xffff0000;
-        } else {
-            M.x86.R_EAX &= 0x0000ffff;
-        }
+       if (M.x86.R_AX & 0x8000) {
+           M.x86.R_EAX |= 0xffff0000;
+       } else {
+           M.x86.R_EAX &= 0x0000ffff;
+       }
     } else {
-        if (M.x86.R_AL & 0x80) {
-            M.x86.R_AH = 0xff;
-        } else {
-            M.x86.R_AH = 0x0;
-        }
+       if (M.x86.R_AL & 0x80) {
+           M.x86.R_AH = 0xff;
+       } else {
+           M.x86.R_AH = 0x0;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2276,24 +2276,24 @@ void x86emuOp_cwd(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF("CDQ\n");
+       DECODE_PRINTF("CDQ\n");
     } else {
-        DECODE_PRINTF("CWD\n");
+       DECODE_PRINTF("CWD\n");
     }
     DECODE_PRINTF("CWD\n");
     TRACE_AND_STEP();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        if (M.x86.R_EAX & 0x80000000) {
-            M.x86.R_EDX = 0xffffffff;
-        } else {
-            M.x86.R_EDX = 0x0;
-        }
+       if (M.x86.R_EAX & 0x80000000) {
+           M.x86.R_EDX = 0xffffffff;
+       } else {
+           M.x86.R_EDX = 0x0;
+       }
     } else {
-        if (M.x86.R_AX & 0x8000) {
-            M.x86.R_DX = 0xffff;
-        } else {
-            M.x86.R_DX = 0x0;
-        }
+       if (M.x86.R_AX & 0x8000) {
+           M.x86.R_DX = 0xffff;
+       } else {
+           M.x86.R_DX = 0x0;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2319,7 +2319,7 @@ void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1))
      *
      * Hooked interrupt vectors calling into our "BIOS" will cause
      * problems unless all intersegment stuff is checked for BIOS
-     * access.  Check needed here.  For moment, let it alone.
+     * access. Check needed here.  For moment, let it alone.
      */
     TRACE_AND_STEP();
     push_word(M.x86.R_CS);
@@ -2354,18 +2354,18 @@ void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1))
 
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF("PUSHFD\n");
+       DECODE_PRINTF("PUSHFD\n");
     } else {
-        DECODE_PRINTF("PUSHF\n");
+       DECODE_PRINTF("PUSHF\n");
     }
     TRACE_AND_STEP();
 
     /* clear out *all* bits not representing flags, and turn on real bits */
     flags = (M.x86.R_EFLG & F_MSK) | F_ALWAYS_ON;
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        push_long(flags);
+       push_long(flags);
     } else {
-        push_word((u16)flags);
+       push_word((u16)flags);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2379,15 +2379,15 @@ void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF("POPFD\n");
+       DECODE_PRINTF("POPFD\n");
     } else {
-        DECODE_PRINTF("POPF\n");
+       DECODE_PRINTF("POPF\n");
     }
     TRACE_AND_STEP();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        M.x86.R_EFLG = pop_long();
+       M.x86.R_EFLG = pop_long();
     } else {
-        M.x86.R_FLG = pop_word();
+       M.x86.R_FLG = pop_word();
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2456,15 +2456,15 @@ void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1))
     START_OF_INSTR();
     offset = fetch_word_imm();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset);
+       DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset);
     } else {
-        DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset);
+       DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset);
     }
     TRACE_AND_STEP();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        M.x86.R_EAX = fetch_data_long(offset);
+       M.x86.R_EAX = fetch_data_long(offset);
     } else {
-        M.x86.R_AX = fetch_data_word(offset);
+       M.x86.R_AX = fetch_data_word(offset);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2499,15 +2499,15 @@ void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1))
     START_OF_INSTR();
     offset = fetch_word_imm();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset);
+       DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset);
     } else {
-        DECODE_PRINTF2("MOV\t[%04x],AX\n", offset);
+       DECODE_PRINTF2("MOV\t[%04x],AX\n", offset);
     }
     TRACE_AND_STEP();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        store_data_long(offset, M.x86.R_EAX);
+       store_data_long(offset, M.x86.R_EAX);
     } else {
-        store_data_word(offset, M.x86.R_AX);
+       store_data_word(offset, M.x86.R_AX);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2519,30 +2519,30 @@ Handles opcode 0xa4
 ****************************************************************************/
 void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1))
 {
-    u8  val;
+    u8 val;
     u32 count;
     int inc;
 
     START_OF_INSTR();
     DECODE_PRINTF("MOVS\tBYTE\n");
     if (ACCESS_FLAG(F_DF))   /* down */
-        inc = -1;
+       inc = -1;
     else
-        inc = 1;
+       inc = 1;
     TRACE_AND_STEP();
     count = 1;
     if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
-        /* dont care whether REPE or REPNE */
-        /* move them until CX is ZERO. */
-        count = M.x86.R_CX;
-        M.x86.R_CX = 0;
-        M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+       /* dont care whether REPE or REPNE */
+       /* move them until CX is ZERO. */
+       count = M.x86.R_CX;
+       M.x86.R_CX = 0;
+       M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
     }
     while (count--) {
-        val = fetch_data_byte(M.x86.R_SI);
-        store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val);
-        M.x86.R_SI += inc;
-        M.x86.R_DI += inc;
+       val = fetch_data_byte(M.x86.R_SI);
+       store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val);
+       M.x86.R_SI += inc;
+       M.x86.R_DI += inc;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2560,37 +2560,37 @@ void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1))
 
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF("MOVS\tDWORD\n");
-        if (ACCESS_FLAG(F_DF))      /* down */
-            inc = -4;
-        else
-            inc = 4;
+       DECODE_PRINTF("MOVS\tDWORD\n");
+       if (ACCESS_FLAG(F_DF))      /* down */
+           inc = -4;
+       else
+           inc = 4;
     } else {
-        DECODE_PRINTF("MOVS\tWORD\n");
-        if (ACCESS_FLAG(F_DF))      /* down */
-            inc = -2;
-        else
-            inc = 2;
+       DECODE_PRINTF("MOVS\tWORD\n");
+       if (ACCESS_FLAG(F_DF))      /* down */
+           inc = -2;
+       else
+           inc = 2;
     }
     TRACE_AND_STEP();
     count = 1;
     if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
-        /* dont care whether REPE or REPNE */
-        /* move them until CX is ZERO. */
-        count = M.x86.R_CX;
-        M.x86.R_CX = 0;
-        M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+       /* dont care whether REPE or REPNE */
+       /* move them until CX is ZERO. */
+       count = M.x86.R_CX;
+       M.x86.R_CX = 0;
+       M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
     }
     while (count--) {
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            val = fetch_data_long(M.x86.R_SI);
-            store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val);
-        } else {
-            val = fetch_data_word(M.x86.R_SI);
-            store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val);
-        }
-        M.x86.R_SI += inc;
-        M.x86.R_DI += inc;
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           val = fetch_data_long(M.x86.R_SI);
+           store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val);
+       } else {
+           val = fetch_data_word(M.x86.R_SI);
+           store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val);
+       }
+       M.x86.R_SI += inc;
+       M.x86.R_DI += inc;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2609,30 +2609,30 @@ void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("CMPS\tBYTE\n");
     TRACE_AND_STEP();
     if (ACCESS_FLAG(F_DF))   /* down */
-        inc = -1;
+       inc = -1;
     else
-        inc = 1;
+       inc = 1;
 
     if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
-        /* REPE  */
-        /* move them until CX is ZERO. */
-        while (M.x86.R_CX != 0) {
-            val1 = fetch_data_byte(M.x86.R_SI);
-            val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
-                     cmp_byte(val1, val2);
-            M.x86.R_CX -= 1;
-            M.x86.R_SI += inc;
-            M.x86.R_DI += inc;
-            if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && (ACCESS_FLAG(F_ZF) == 0) ) break;
-            if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break;
-        }
-        M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+       /* REPE  */
+       /* move them until CX is ZERO. */
+       while (M.x86.R_CX != 0) {
+           val1 = fetch_data_byte(M.x86.R_SI);
+           val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
+                    cmp_byte(val1, val2);
+           M.x86.R_CX -= 1;
+           M.x86.R_SI += inc;
+           M.x86.R_DI += inc;
+           if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && (ACCESS_FLAG(F_ZF) == 0) ) break;
+           if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break;
+       }
+       M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
     } else {
-        val1 = fetch_data_byte(M.x86.R_SI);
-        val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
-        cmp_byte(val1, val2);
-        M.x86.R_SI += inc;
-        M.x86.R_DI += inc;
+       val1 = fetch_data_byte(M.x86.R_SI);
+       val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
+       cmp_byte(val1, val2);
+       M.x86.R_SI += inc;
+       M.x86.R_DI += inc;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2649,48 +2649,48 @@ void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1))
 
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF("CMPS\tDWORD\n");
-        inc = 4;
+       DECODE_PRINTF("CMPS\tDWORD\n");
+       inc = 4;
     } else {
-        DECODE_PRINTF("CMPS\tWORD\n");
-        inc = 2;
+       DECODE_PRINTF("CMPS\tWORD\n");
+       inc = 2;
     }
     if (ACCESS_FLAG(F_DF))   /* down */
-        inc = -inc;
+       inc = -inc;
 
     TRACE_AND_STEP();
     if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
-        /* REPE  */
-        /* move them until CX is ZERO. */
-        while (M.x86.R_CX != 0) {
-            if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-                val1 = fetch_data_long(M.x86.R_SI);
-                val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
-                cmp_long(val1, val2);
-            } else {
-                val1 = fetch_data_word(M.x86.R_SI);
-                val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
-                cmp_word((u16)val1, (u16)val2);
-            }
-            M.x86.R_CX -= 1;
-            M.x86.R_SI += inc;
-            M.x86.R_DI += inc;
-            if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && ACCESS_FLAG(F_ZF) == 0 ) break;
-            if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break;
-        }
-        M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+       /* REPE  */
+       /* move them until CX is ZERO. */
+       while (M.x86.R_CX != 0) {
+           if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+               val1 = fetch_data_long(M.x86.R_SI);
+               val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
+               cmp_long(val1, val2);
+           } else {
+               val1 = fetch_data_word(M.x86.R_SI);
+               val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
+               cmp_word((u16)val1, (u16)val2);
+           }
+           M.x86.R_CX -= 1;
+           M.x86.R_SI += inc;
+           M.x86.R_DI += inc;
+           if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && ACCESS_FLAG(F_ZF) == 0 ) break;
+           if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break;
+       }
+       M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
     } else {
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            val1 = fetch_data_long(M.x86.R_SI);
-            val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
-            cmp_long(val1, val2);
-        } else {
-            val1 = fetch_data_word(M.x86.R_SI);
-            val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
-            cmp_word((u16)val1, (u16)val2);
-        }
-        M.x86.R_SI += inc;
-        M.x86.R_DI += inc;
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           val1 = fetch_data_long(M.x86.R_SI);
+           val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
+           cmp_long(val1, val2);
+       } else {
+           val1 = fetch_data_word(M.x86.R_SI);
+           val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
+           cmp_word((u16)val1, (u16)val2);
+       }
+       M.x86.R_SI += inc;
+       M.x86.R_DI += inc;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2724,18 +2724,18 @@ void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1))
 
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF("TEST\tEAX,");
-        srcval = fetch_long_imm();
+       DECODE_PRINTF("TEST\tEAX,");
+       srcval = fetch_long_imm();
     } else {
-        DECODE_PRINTF("TEST\tAX,");
-        srcval = fetch_word_imm();
+       DECODE_PRINTF("TEST\tAX,");
+       srcval = fetch_word_imm();
     }
     DECODE_PRINTF2("%x\n", srcval);
     TRACE_AND_STEP();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        test_long(M.x86.R_EAX, srcval);
+       test_long(M.x86.R_EAX, srcval);
     } else {
-        test_word(M.x86.R_AX, (u16)srcval);
+       test_word(M.x86.R_AX, (u16)srcval);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2752,22 +2752,22 @@ void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1))
     START_OF_INSTR();
     DECODE_PRINTF("STOS\tBYTE\n");
     if (ACCESS_FLAG(F_DF))   /* down */
-        inc = -1;
+       inc = -1;
     else
-        inc = 1;
+       inc = 1;
     TRACE_AND_STEP();
     if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
-        /* dont care whether REPE or REPNE */
-        /* move them until CX is ZERO. */
-        while (M.x86.R_CX != 0) {
-            store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL);
-            M.x86.R_CX -= 1;
-            M.x86.R_DI += inc;
-        }
-        M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+       /* dont care whether REPE or REPNE */
+       /* move them until CX is ZERO. */
+       while (M.x86.R_CX != 0) {
+           store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL);
+           M.x86.R_CX -= 1;
+           M.x86.R_DI += inc;
+       }
+       M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
     } else {
-        store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL);
-        M.x86.R_DI += inc;
+       store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL);
+       M.x86.R_DI += inc;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2784,34 +2784,34 @@ void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1))
 
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF("STOS\tDWORD\n");
-        if (ACCESS_FLAG(F_DF))   /* down */
-            inc = -4;
-        else
-            inc = 4;
+       DECODE_PRINTF("STOS\tDWORD\n");
+       if (ACCESS_FLAG(F_DF))   /* down */
+           inc = -4;
+       else
+           inc = 4;
     } else {
-        DECODE_PRINTF("STOS\tWORD\n");
-        if (ACCESS_FLAG(F_DF))   /* down */
-            inc = -2;
-        else
-            inc = 2;
+       DECODE_PRINTF("STOS\tWORD\n");
+       if (ACCESS_FLAG(F_DF))   /* down */
+           inc = -2;
+       else
+           inc = 2;
     }
     TRACE_AND_STEP();
     count = 1;
     if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
-        /* dont care whether REPE or REPNE */
-        /* move them until CX is ZERO. */
-        count = M.x86.R_CX;
-        M.x86.R_CX = 0;
-        M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+       /* dont care whether REPE or REPNE */
+       /* move them until CX is ZERO. */
+       count = M.x86.R_CX;
+       M.x86.R_CX = 0;
+       M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
     }
     while (count--) {
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX);
-        } else {
-            store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX);
-        }
-        M.x86.R_DI += inc;
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX);
+       } else {
+           store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX);
+       }
+       M.x86.R_DI += inc;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2829,21 +2829,21 @@ void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("LODS\tBYTE\n");
     TRACE_AND_STEP();
     if (ACCESS_FLAG(F_DF))   /* down */
-        inc = -1;
+       inc = -1;
     else
-        inc = 1;
+       inc = 1;
     if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
-        /* dont care whether REPE or REPNE */
-        /* move them until CX is ZERO. */
-        while (M.x86.R_CX != 0) {
-            M.x86.R_AL = fetch_data_byte(M.x86.R_SI);
-            M.x86.R_CX -= 1;
-            M.x86.R_SI += inc;
-        }
-        M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+       /* dont care whether REPE or REPNE */
+       /* move them until CX is ZERO. */
+       while (M.x86.R_CX != 0) {
+           M.x86.R_AL = fetch_data_byte(M.x86.R_SI);
+           M.x86.R_CX -= 1;
+           M.x86.R_SI += inc;
+       }
+       M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
     } else {
-        M.x86.R_AL = fetch_data_byte(M.x86.R_SI);
-        M.x86.R_SI += inc;
+       M.x86.R_AL = fetch_data_byte(M.x86.R_SI);
+       M.x86.R_SI += inc;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2860,34 +2860,34 @@ void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1))
 
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF("LODS\tDWORD\n");
-        if (ACCESS_FLAG(F_DF))   /* down */
-            inc = -4;
-        else
-            inc = 4;
+       DECODE_PRINTF("LODS\tDWORD\n");
+       if (ACCESS_FLAG(F_DF))   /* down */
+           inc = -4;
+       else
+           inc = 4;
     } else {
-        DECODE_PRINTF("LODS\tWORD\n");
-        if (ACCESS_FLAG(F_DF))   /* down */
-            inc = -2;
-        else
-            inc = 2;
+       DECODE_PRINTF("LODS\tWORD\n");
+       if (ACCESS_FLAG(F_DF))   /* down */
+           inc = -2;
+       else
+           inc = 2;
     }
     TRACE_AND_STEP();
     count = 1;
     if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
-        /* dont care whether REPE or REPNE */
-        /* move them until CX is ZERO. */
-        count = M.x86.R_CX;
-        M.x86.R_CX = 0;
-        M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+       /* dont care whether REPE or REPNE */
+       /* move them until CX is ZERO. */
+       count = M.x86.R_CX;
+       M.x86.R_CX = 0;
+       M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
     }
     while (count--) {
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            M.x86.R_EAX = fetch_data_long(M.x86.R_SI);
-        } else {
-            M.x86.R_AX = fetch_data_word(M.x86.R_SI);
-        }
-        M.x86.R_SI += inc;
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           M.x86.R_EAX = fetch_data_long(M.x86.R_SI);
+       } else {
+           M.x86.R_AX = fetch_data_word(M.x86.R_SI);
+       }
+       M.x86.R_SI += inc;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2906,37 +2906,37 @@ void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("SCAS\tBYTE\n");
     TRACE_AND_STEP();
     if (ACCESS_FLAG(F_DF))   /* down */
-        inc = -1;
+       inc = -1;
     else
-        inc = 1;
+       inc = 1;
     if (M.x86.mode & SYSMODE_PREFIX_REPE) {
-        /* REPE  */
-        /* move them until CX is ZERO. */
-        while (M.x86.R_CX != 0) {
-            val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
-            cmp_byte(M.x86.R_AL, val2);
-            M.x86.R_CX -= 1;
-            M.x86.R_DI += inc;
-            if (ACCESS_FLAG(F_ZF) == 0)
-                break;
-        }
-        M.x86.mode &= ~SYSMODE_PREFIX_REPE;
+       /* REPE  */
+       /* move them until CX is ZERO. */
+       while (M.x86.R_CX != 0) {
+           val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
+           cmp_byte(M.x86.R_AL, val2);
+           M.x86.R_CX -= 1;
+           M.x86.R_DI += inc;
+           if (ACCESS_FLAG(F_ZF) == 0)
+               break;
+       }
+       M.x86.mode &= ~SYSMODE_PREFIX_REPE;
     } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) {
-        /* REPNE  */
-        /* move them until CX is ZERO. */
-        while (M.x86.R_CX != 0) {
-            val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
-            cmp_byte(M.x86.R_AL, val2);
-            M.x86.R_CX -= 1;
-            M.x86.R_DI += inc;
-            if (ACCESS_FLAG(F_ZF))
-                break;          /* zero flag set means equal */
-        }
-        M.x86.mode &= ~SYSMODE_PREFIX_REPNE;
+       /* REPNE  */
+       /* move them until CX is ZERO. */
+       while (M.x86.R_CX != 0) {
+           val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
+           cmp_byte(M.x86.R_AL, val2);
+           M.x86.R_CX -= 1;
+           M.x86.R_DI += inc;
+           if (ACCESS_FLAG(F_ZF))
+               break;          /* zero flag set means equal */
+       }
+       M.x86.mode &= ~SYSMODE_PREFIX_REPNE;
     } else {
-        val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
-        cmp_byte(M.x86.R_AL, val2);
-        M.x86.R_DI += inc;
+       val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
+       cmp_byte(M.x86.R_AL, val2);
+       M.x86.R_DI += inc;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -2953,62 +2953,62 @@ void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1))
 
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF("SCAS\tDWORD\n");
-        if (ACCESS_FLAG(F_DF))   /* down */
-            inc = -4;
-        else
-            inc = 4;
+       DECODE_PRINTF("SCAS\tDWORD\n");
+       if (ACCESS_FLAG(F_DF))   /* down */
+           inc = -4;
+       else
+           inc = 4;
     } else {
-        DECODE_PRINTF("SCAS\tWORD\n");
-        if (ACCESS_FLAG(F_DF))   /* down */
-            inc = -2;
-        else
-            inc = 2;
+       DECODE_PRINTF("SCAS\tWORD\n");
+       if (ACCESS_FLAG(F_DF))   /* down */
+           inc = -2;
+       else
+           inc = 2;
     }
     TRACE_AND_STEP();
     if (M.x86.mode & SYSMODE_PREFIX_REPE) {
-        /* REPE  */
-        /* move them until CX is ZERO. */
-        while (M.x86.R_CX != 0) {
-            if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-                val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
-                cmp_long(M.x86.R_EAX, val);
-            } else {
-                val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
-                cmp_word(M.x86.R_AX, (u16)val);
-            }
-            M.x86.R_CX -= 1;
-            M.x86.R_DI += inc;
-            if (ACCESS_FLAG(F_ZF) == 0)
-                break;
-        }
-        M.x86.mode &= ~SYSMODE_PREFIX_REPE;
+       /* REPE  */
+       /* move them until CX is ZERO. */
+       while (M.x86.R_CX != 0) {
+           if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+               val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
+               cmp_long(M.x86.R_EAX, val);
+           } else {
+               val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
+               cmp_word(M.x86.R_AX, (u16)val);
+           }
+           M.x86.R_CX -= 1;
+           M.x86.R_DI += inc;
+           if (ACCESS_FLAG(F_ZF) == 0)
+               break;
+       }
+       M.x86.mode &= ~SYSMODE_PREFIX_REPE;
     } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) {
-        /* REPNE  */
-        /* move them until CX is ZERO. */
-        while (M.x86.R_CX != 0) {
-            if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-                val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
-                cmp_long(M.x86.R_EAX, val);
-            } else {
-                val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
-                cmp_word(M.x86.R_AX, (u16)val);
-            }
-            M.x86.R_CX -= 1;
-            M.x86.R_DI += inc;
-            if (ACCESS_FLAG(F_ZF))
-                break;          /* zero flag set means equal */
-        }
-        M.x86.mode &= ~SYSMODE_PREFIX_REPNE;
+       /* REPNE  */
+       /* move them until CX is ZERO. */
+       while (M.x86.R_CX != 0) {
+           if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+               val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
+               cmp_long(M.x86.R_EAX, val);
+           } else {
+               val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
+               cmp_word(M.x86.R_AX, (u16)val);
+           }
+           M.x86.R_CX -= 1;
+           M.x86.R_DI += inc;
+           if (ACCESS_FLAG(F_ZF))
+               break;          /* zero flag set means equal */
+       }
+       M.x86.mode &= ~SYSMODE_PREFIX_REPNE;
     } else {
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
-            cmp_long(M.x86.R_EAX, val);
-        } else {
-            val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
-            cmp_word(M.x86.R_AX, (u16)val);
-        }
-        M.x86.R_DI += inc;
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
+           cmp_long(M.x86.R_EAX, val);
+       } else {
+           val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
+           cmp_word(M.x86.R_AX, (u16)val);
+       }
+       M.x86.R_DI += inc;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -3047,19 +3047,19 @@ void x86emuOp_mov_word_register_IMM(u8 X86EMU_UNUSED(op1))
     START_OF_INSTR();
     DECODE_PRINTF("MOV\t");
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        u32 *reg32;
-        reg32 = DECODE_RM_LONG_REGISTER(op1);
-        srcval = fetch_long_imm();
-        DECODE_PRINTF2(",%x\n", srcval);
-        TRACE_AND_STEP();
-        *reg32 = srcval;
+       u32 *reg32;
+       reg32 = DECODE_RM_LONG_REGISTER(op1);
+       srcval = fetch_long_imm();
+       DECODE_PRINTF2(",%x\n", srcval);
+       TRACE_AND_STEP();
+       *reg32 = srcval;
     } else {
-        u16 *reg16;
-        reg16 = DECODE_RM_WORD_REGISTER(op1);
-        srcval = fetch_word_imm();
-        DECODE_PRINTF2(",%x\n", srcval);
-        TRACE_AND_STEP();
-        *reg16 = (u16)srcval;
+       u16 *reg16;
+       reg16 = DECODE_RM_WORD_REGISTER(op1);
+       srcval = fetch_word_imm();
+       DECODE_PRINTF2(",%x\n", srcval);
+       TRACE_AND_STEP();
+       *reg16 = (u16)srcval;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -3086,57 +3086,57 @@ void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1))
     FETCH_DECODE_MODRM(mod, rh, rl);
 #ifdef DEBUG
     if (DEBUG_DECODE()) {
-        /* XXX DECODE_PRINTF may be changed to something more
-           general, so that it is important to leave the strings
-           in the same format, even though the result is that the
-           above test is done twice. */
-
-        switch (rh) {
-        case 0:
-            DECODE_PRINTF("ROL\t");
-            break;
-        case 1:
-            DECODE_PRINTF("ROR\t");
-            break;
-        case 2:
-            DECODE_PRINTF("RCL\t");
-            break;
-        case 3:
-            DECODE_PRINTF("RCR\t");
-            break;
-        case 4:
-            DECODE_PRINTF("SHL\t");
-            break;
-        case 5:
-            DECODE_PRINTF("SHR\t");
-            break;
-        case 6:
-            DECODE_PRINTF("SAL\t");
-            break;
-        case 7:
-            DECODE_PRINTF("SAR\t");
-            break;
-        }
+       /* XXX DECODE_PRINTF may be changed to something more
+          general, so that it is important to leave the strings
+          in the same format, even though the result is that the
+          above test is done twice. */
+
+       switch (rh) {
+       case 0:
+           DECODE_PRINTF("ROL\t");
+           break;
+       case 1:
+           DECODE_PRINTF("ROR\t");
+           break;
+       case 2:
+           DECODE_PRINTF("RCL\t");
+           break;
+       case 3:
+           DECODE_PRINTF("RCR\t");
+           break;
+       case 4:
+           DECODE_PRINTF("SHL\t");
+           break;
+       case 5:
+           DECODE_PRINTF("SHR\t");
+           break;
+       case 6:
+           DECODE_PRINTF("SAL\t");
+           break;
+       case 7:
+           DECODE_PRINTF("SAR\t");
+           break;
+       }
     }
 #endif
     /* know operation, decode the mod byte to find the addressing
        mode. */
     if (mod < 3) {
-        DECODE_PRINTF("BYTE PTR ");
-        destoffset = decode_rmXX_address(mod, rl);
-        amt = fetch_byte_imm();
-        DECODE_PRINTF2(",%x\n", amt);
-        destval = fetch_data_byte(destoffset);
-        TRACE_AND_STEP();
-        destval = (*opcD0_byte_operation[rh]) (destval, amt);
-        store_data_byte(destoffset, destval);
-    } else {                     /* register to register */
-        destreg = DECODE_RM_BYTE_REGISTER(rl);
-        amt = fetch_byte_imm();
-        DECODE_PRINTF2(",%x\n", amt);
-        TRACE_AND_STEP();
-        destval = (*opcD0_byte_operation[rh]) (*destreg, amt);
-        *destreg = destval;
+       DECODE_PRINTF("BYTE PTR ");
+       destoffset = decode_rmXX_address(mod, rl);
+       amt = fetch_byte_imm();
+       DECODE_PRINTF2(",%x\n", amt);
+       destval = fetch_data_byte(destoffset);
+       TRACE_AND_STEP();
+       destval = (*opcD0_byte_operation[rh]) (destval, amt);
+       store_data_byte(destoffset, destval);
+    } else {                    /* register to register */
+       destreg = DECODE_RM_BYTE_REGISTER(rl);
+       amt = fetch_byte_imm();
+       DECODE_PRINTF2(",%x\n", amt);
+       TRACE_AND_STEP();
+       destval = (*opcD0_byte_operation[rh]) (*destreg, amt);
+       *destreg = destval;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -3161,83 +3161,83 @@ void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1))
     FETCH_DECODE_MODRM(mod, rh, rl);
 #ifdef DEBUG
     if (DEBUG_DECODE()) {
-        /* XXX DECODE_PRINTF may be changed to something more
-           general, so that it is important to leave the strings
-           in the same format, even though the result is that the
-           above test is done twice. */
-
-        switch (rh) {
-        case 0:
-            DECODE_PRINTF("ROL\t");
-            break;
-        case 1:
-            DECODE_PRINTF("ROR\t");
-            break;
-        case 2:
-            DECODE_PRINTF("RCL\t");
-            break;
-        case 3:
-            DECODE_PRINTF("RCR\t");
-            break;
-        case 4:
-            DECODE_PRINTF("SHL\t");
-            break;
-        case 5:
-            DECODE_PRINTF("SHR\t");
-            break;
-        case 6:
-            DECODE_PRINTF("SAL\t");
-            break;
-        case 7:
-            DECODE_PRINTF("SAR\t");
-            break;
-        }
+       /* XXX DECODE_PRINTF may be changed to something more
+          general, so that it is important to leave the strings
+          in the same format, even though the result is that the
+          above test is done twice. */
+
+       switch (rh) {
+       case 0:
+           DECODE_PRINTF("ROL\t");
+           break;
+       case 1:
+           DECODE_PRINTF("ROR\t");
+           break;
+       case 2:
+           DECODE_PRINTF("RCL\t");
+           break;
+       case 3:
+           DECODE_PRINTF("RCR\t");
+           break;
+       case 4:
+           DECODE_PRINTF("SHL\t");
+           break;
+       case 5:
+           DECODE_PRINTF("SHR\t");
+           break;
+       case 6:
+           DECODE_PRINTF("SAL\t");
+           break;
+       case 7:
+           DECODE_PRINTF("SAR\t");
+           break;
+       }
     }
 #endif
     /* know operation, decode the mod byte to find the addressing
        mode. */
     if (mod < 3) {
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 destval;
-
-            DECODE_PRINTF("DWORD PTR ");
-            destoffset = decode_rmXX_address(mod, rl);
-            amt = fetch_byte_imm();
-            DECODE_PRINTF2(",%x\n", amt);
-            destval = fetch_data_long(destoffset);
-            TRACE_AND_STEP();
-            destval = (*opcD1_long_operation[rh]) (destval, amt);
-            store_data_long(destoffset, destval);
-        } else {
-            u16 destval;
-
-            DECODE_PRINTF("WORD PTR ");
-            destoffset = decode_rmXX_address(mod, rl);
-            amt = fetch_byte_imm();
-            DECODE_PRINTF2(",%x\n", amt);
-            destval = fetch_data_word(destoffset);
-            TRACE_AND_STEP();
-            destval = (*opcD1_word_operation[rh]) (destval, amt);
-            store_data_word(destoffset, destval);
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg;
-
-            destreg = DECODE_RM_LONG_REGISTER(rl);
-            amt = fetch_byte_imm();
-            DECODE_PRINTF2(",%x\n", amt);
-            TRACE_AND_STEP();
-            *destreg = (*opcD1_long_operation[rh]) (*destreg, amt);
-        } else {
-            u16 *destreg;
-
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-            amt = fetch_byte_imm();
-            DECODE_PRINTF2(",%x\n", amt);
-            TRACE_AND_STEP();
-            *destreg = (*opcD1_word_operation[rh]) (*destreg, amt);
-        }
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 destval;
+
+           DECODE_PRINTF("DWORD PTR ");
+           destoffset = decode_rmXX_address(mod, rl);
+           amt = fetch_byte_imm();
+           DECODE_PRINTF2(",%x\n", amt);
+           destval = fetch_data_long(destoffset);
+           TRACE_AND_STEP();
+           destval = (*opcD1_long_operation[rh]) (destval, amt);
+           store_data_long(destoffset, destval);
+       } else {
+           u16 destval;
+
+           DECODE_PRINTF("WORD PTR ");
+           destoffset = decode_rmXX_address(mod, rl);
+           amt = fetch_byte_imm();
+           DECODE_PRINTF2(",%x\n", amt);
+           destval = fetch_data_word(destoffset);
+           TRACE_AND_STEP();
+           destval = (*opcD1_word_operation[rh]) (destval, amt);
+           store_data_word(destoffset, destval);
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg;
+
+           destreg = DECODE_RM_LONG_REGISTER(rl);
+           amt = fetch_byte_imm();
+           DECODE_PRINTF2(",%x\n", amt);
+           TRACE_AND_STEP();
+           *destreg = (*opcD1_long_operation[rh]) (*destreg, amt);
+       } else {
+           u16 *destreg;
+
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+           amt = fetch_byte_imm();
+           DECODE_PRINTF2(",%x\n", amt);
+           TRACE_AND_STEP();
+           *destreg = (*opcD1_word_operation[rh]) (*destreg, amt);
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -3292,15 +3292,15 @@ void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("LES\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        dstreg = DECODE_RM_WORD_REGISTER(rh);
-        DECODE_PRINTF(",");
-        srcoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *dstreg = fetch_data_word(srcoffset);
-        M.x86.R_ES = fetch_data_word(srcoffset + 2);
+       dstreg = DECODE_RM_WORD_REGISTER(rh);
+       DECODE_PRINTF(",");
+       srcoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *dstreg = fetch_data_word(srcoffset);
+       M.x86.R_ES = fetch_data_word(srcoffset + 2);
     }
-    /* else UNDEFINED!                   register to register */
+    /* else UNDEFINED!                  register to register */
 
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -3320,13 +3320,13 @@ void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("LDS\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        dstreg = DECODE_RM_WORD_REGISTER(rh);
-        DECODE_PRINTF(",");
-        srcoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *dstreg = fetch_data_word(srcoffset);
-        M.x86.R_DS = fetch_data_word(srcoffset + 2);
+       dstreg = DECODE_RM_WORD_REGISTER(rh);
+       DECODE_PRINTF(",");
+       srcoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *dstreg = fetch_data_word(srcoffset);
+       M.x86.R_DS = fetch_data_word(srcoffset + 2);
     }
     /* else UNDEFINED! */
     DECODE_CLEAR_SEGOVR();
@@ -3348,22 +3348,22 @@ void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("MOV\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (rh != 0) {
-        DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n");
-        HALT_SYS();
+       DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n");
+       HALT_SYS();
     }
     if (mod < 3) {
-        DECODE_PRINTF("BYTE PTR ");
-        destoffset = decode_rmXX_address(mod, rl);
-        imm = fetch_byte_imm();
-        DECODE_PRINTF2(",%2x\n", imm);
-        TRACE_AND_STEP();
-        store_data_byte(destoffset, imm);
-    } else {                     /* register to register */
-        destreg = DECODE_RM_BYTE_REGISTER(rl);
-        imm = fetch_byte_imm();
-        DECODE_PRINTF2(",%2x\n", imm);
-        TRACE_AND_STEP();
-        *destreg = imm;
+       DECODE_PRINTF("BYTE PTR ");
+       destoffset = decode_rmXX_address(mod, rl);
+       imm = fetch_byte_imm();
+       DECODE_PRINTF2(",%2x\n", imm);
+       TRACE_AND_STEP();
+       store_data_byte(destoffset, imm);
+    } else {                    /* register to register */
+       destreg = DECODE_RM_BYTE_REGISTER(rl);
+       imm = fetch_byte_imm();
+       DECODE_PRINTF2(",%2x\n", imm);
+       TRACE_AND_STEP();
+       *destreg = imm;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -3382,49 +3382,49 @@ void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("MOV\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (rh != 0) {
-        DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
-        HALT_SYS();
+       DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
+       HALT_SYS();
     }
     if (mod < 3) {
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 imm;
-
-            DECODE_PRINTF("DWORD PTR ");
-            destoffset = decode_rmXX_address(mod, rl);
-            imm = fetch_long_imm();
-            DECODE_PRINTF2(",%x\n", imm);
-            TRACE_AND_STEP();
-            store_data_long(destoffset, imm);
-        } else {
-            u16 imm;
-
-            DECODE_PRINTF("WORD PTR ");
-            destoffset = decode_rmXX_address(mod, rl);
-            imm = fetch_word_imm();
-            DECODE_PRINTF2(",%x\n", imm);
-            TRACE_AND_STEP();
-            store_data_word(destoffset, imm);
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 imm;
+
+           DECODE_PRINTF("DWORD PTR ");
+           destoffset = decode_rmXX_address(mod, rl);
+           imm = fetch_long_imm();
+           DECODE_PRINTF2(",%x\n", imm);
+           TRACE_AND_STEP();
+           store_data_long(destoffset, imm);
+       } else {
+           u16 imm;
+
+           DECODE_PRINTF("WORD PTR ");
+           destoffset = decode_rmXX_address(mod, rl);
+           imm = fetch_word_imm();
+           DECODE_PRINTF2(",%x\n", imm);
+           TRACE_AND_STEP();
+           store_data_word(destoffset, imm);
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
                        u32 *destreg;
                        u32 imm;
 
-            destreg = DECODE_RM_LONG_REGISTER(rl);
-            imm = fetch_long_imm();
-            DECODE_PRINTF2(",%x\n", imm);
-            TRACE_AND_STEP();
-            *destreg = imm;
-        } else {
+           destreg = DECODE_RM_LONG_REGISTER(rl);
+           imm = fetch_long_imm();
+           DECODE_PRINTF2(",%x\n", imm);
+           TRACE_AND_STEP();
+           *destreg = imm;
+       } else {
                        u16 *destreg;
                        u16 imm;
 
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-            imm = fetch_word_imm();
-            DECODE_PRINTF2(",%x\n", imm);
-            TRACE_AND_STEP();
-            *destreg = imm;
-        }
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+           imm = fetch_word_imm();
+           DECODE_PRINTF2(",%x\n", imm);
+           TRACE_AND_STEP();
+           *destreg = imm;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -3437,7 +3437,7 @@ Handles opcode 0xc8
 void x86emuOp_enter(u8 X86EMU_UNUSED(op1))
 {
     u16 local,frame_pointer;
-    u8  nesting;
+    u8 nesting;
     int i;
 
     START_OF_INSTR();
@@ -3449,12 +3449,12 @@ void x86emuOp_enter(u8 X86EMU_UNUSED(op1))
     push_word(M.x86.R_BP);
     frame_pointer = M.x86.R_SP;
     if (nesting > 0) {
-        for (i = 1; i < nesting; i++) {
-            M.x86.R_BP -= 2;
-            push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP));
-            }
-        push_word(frame_pointer);
-        }
+       for (i = 1; i < nesting; i++) {
+           M.x86.R_BP -= 2;
+           push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP));
+           }
+       push_word(frame_pointer);
+       }
     M.x86.R_BP = frame_pointer;
     M.x86.R_SP = (u16)(M.x86.R_SP - local);
     DECODE_CLEAR_SEGOVR();
@@ -3529,13 +3529,13 @@ void x86emuOp_int3(u8 X86EMU_UNUSED(op1))
        if (_X86EMU_intrTab[3]) {
                (*_X86EMU_intrTab[3])(3);
     } else {
-        push_word((u16)M.x86.R_FLG);
-        CLEAR_FLAG(F_IF);
-        CLEAR_FLAG(F_TF);
-        push_word(M.x86.R_CS);
-        M.x86.R_CS = mem_access_word(3 * 4 + 2);
-        push_word(M.x86.R_IP);
-        M.x86.R_IP = mem_access_word(3 * 4);
+       push_word((u16)M.x86.R_FLG);
+       CLEAR_FLAG(F_IF);
+       CLEAR_FLAG(F_TF);
+       push_word(M.x86.R_CS);
+       M.x86.R_CS = mem_access_word(3 * 4 + 2);
+       push_word(M.x86.R_IP);
+       M.x86.R_IP = mem_access_word(3 * 4);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -3559,13 +3559,13 @@ void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1))
        if (_X86EMU_intrTab[intnum]) {
                (*_X86EMU_intrTab[intnum])(intnum);
     } else {
-        push_word((u16)M.x86.R_FLG);
-        CLEAR_FLAG(F_IF);
-        CLEAR_FLAG(F_TF);
-        push_word(M.x86.R_CS);
-        M.x86.R_CS = mem_access_word(intnum * 4 + 2);
-        push_word(M.x86.R_IP);
-        M.x86.R_IP = mem_access_word(intnum * 4);
+       push_word((u16)M.x86.R_FLG);
+       CLEAR_FLAG(F_IF);
+       CLEAR_FLAG(F_TF);
+       push_word(M.x86.R_CS);
+       M.x86.R_CS = mem_access_word(intnum * 4 + 2);
+       push_word(M.x86.R_IP);
+       M.x86.R_IP = mem_access_word(intnum * 4);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -3583,18 +3583,18 @@ void x86emuOp_into(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("INTO\n");
     TRACE_AND_STEP();
     if (ACCESS_FLAG(F_OF)) {
-        tmp = mem_access_word(4 * 4 + 2);
+       tmp = mem_access_word(4 * 4 + 2);
                if (_X86EMU_intrTab[4]) {
                        (*_X86EMU_intrTab[4])(4);
-        } else {
-            push_word((u16)M.x86.R_FLG);
-            CLEAR_FLAG(F_IF);
-            CLEAR_FLAG(F_TF);
-            push_word(M.x86.R_CS);
-            M.x86.R_CS = mem_access_word(4 * 4 + 2);
-            push_word(M.x86.R_IP);
-            M.x86.R_IP = mem_access_word(4 * 4);
-        }
+       } else {
+           push_word((u16)M.x86.R_FLG);
+           CLEAR_FLAG(F_IF);
+           CLEAR_FLAG(F_TF);
+           push_word(M.x86.R_CS);
+           M.x86.R_CS = mem_access_word(4 * 4 + 2);
+           push_word(M.x86.R_IP);
+           M.x86.R_IP = mem_access_word(4 * 4);
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -3638,54 +3638,54 @@ void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1))
     FETCH_DECODE_MODRM(mod, rh, rl);
 #ifdef DEBUG
     if (DEBUG_DECODE()) {
-        /* XXX DECODE_PRINTF may be changed to something more
-           general, so that it is important to leave the strings
-           in the same format, even though the result is that the
-           above test is done twice. */
-        switch (rh) {
-        case 0:
-            DECODE_PRINTF("ROL\t");
-            break;
-        case 1:
-            DECODE_PRINTF("ROR\t");
-            break;
-        case 2:
-            DECODE_PRINTF("RCL\t");
-            break;
-        case 3:
-            DECODE_PRINTF("RCR\t");
-            break;
-        case 4:
-            DECODE_PRINTF("SHL\t");
-            break;
-        case 5:
-            DECODE_PRINTF("SHR\t");
-            break;
-        case 6:
-            DECODE_PRINTF("SAL\t");
-            break;
-        case 7:
-            DECODE_PRINTF("SAR\t");
-            break;
-        }
+       /* XXX DECODE_PRINTF may be changed to something more
+          general, so that it is important to leave the strings
+          in the same format, even though the result is that the
+          above test is done twice. */
+       switch (rh) {
+       case 0:
+           DECODE_PRINTF("ROL\t");
+           break;
+       case 1:
+           DECODE_PRINTF("ROR\t");
+           break;
+       case 2:
+           DECODE_PRINTF("RCL\t");
+           break;
+       case 3:
+           DECODE_PRINTF("RCR\t");
+           break;
+       case 4:
+           DECODE_PRINTF("SHL\t");
+           break;
+       case 5:
+           DECODE_PRINTF("SHR\t");
+           break;
+       case 6:
+           DECODE_PRINTF("SAL\t");
+           break;
+       case 7:
+           DECODE_PRINTF("SAR\t");
+           break;
+       }
     }
 #endif
     /* know operation, decode the mod byte to find the addressing
        mode. */
     if (mod < 3) {
-        DECODE_PRINTF("BYTE PTR ");
-        destoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF(",1\n");
-        destval = fetch_data_byte(destoffset);
-        TRACE_AND_STEP();
-        destval = (*opcD0_byte_operation[rh]) (destval, 1);
-        store_data_byte(destoffset, destval);
-    } else {                     /* register to register */
-        destreg = DECODE_RM_BYTE_REGISTER(rl);
-        DECODE_PRINTF(",1\n");
-        TRACE_AND_STEP();
-        destval = (*opcD0_byte_operation[rh]) (*destreg, 1);
-        *destreg = destval;
+       DECODE_PRINTF("BYTE PTR ");
+       destoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF(",1\n");
+       destval = fetch_data_byte(destoffset);
+       TRACE_AND_STEP();
+       destval = (*opcD0_byte_operation[rh]) (destval, 1);
+       store_data_byte(destoffset, destval);
+    } else {                    /* register to register */
+       destreg = DECODE_RM_BYTE_REGISTER(rl);
+       DECODE_PRINTF(",1\n");
+       TRACE_AND_STEP();
+       destval = (*opcD0_byte_operation[rh]) (*destreg, 1);
+       *destreg = destval;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -3709,82 +3709,82 @@ void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1))
     FETCH_DECODE_MODRM(mod, rh, rl);
 #ifdef DEBUG
     if (DEBUG_DECODE()) {
-        /* XXX DECODE_PRINTF may be changed to something more
-           general, so that it is important to leave the strings
-           in the same format, even though the result is that the
-           above test is done twice. */
-        switch (rh) {
-        case 0:
-            DECODE_PRINTF("ROL\t");
-            break;
-        case 1:
-            DECODE_PRINTF("ROR\t");
-            break;
-        case 2:
-            DECODE_PRINTF("RCL\t");
-            break;
-        case 3:
-            DECODE_PRINTF("RCR\t");
-            break;
-        case 4:
-            DECODE_PRINTF("SHL\t");
-            break;
-        case 5:
-            DECODE_PRINTF("SHR\t");
-            break;
-        case 6:
-            DECODE_PRINTF("SAL\t");
-            break;
-        case 7:
-            DECODE_PRINTF("SAR\t");
-            break;
-        }
+       /* XXX DECODE_PRINTF may be changed to something more
+          general, so that it is important to leave the strings
+          in the same format, even though the result is that the
+          above test is done twice. */
+       switch (rh) {
+       case 0:
+           DECODE_PRINTF("ROL\t");
+           break;
+       case 1:
+           DECODE_PRINTF("ROR\t");
+           break;
+       case 2:
+           DECODE_PRINTF("RCL\t");
+           break;
+       case 3:
+           DECODE_PRINTF("RCR\t");
+           break;
+       case 4:
+           DECODE_PRINTF("SHL\t");
+           break;
+       case 5:
+           DECODE_PRINTF("SHR\t");
+           break;
+       case 6:
+           DECODE_PRINTF("SAL\t");
+           break;
+       case 7:
+           DECODE_PRINTF("SAR\t");
+           break;
+       }
     }
 #endif
     /* know operation, decode the mod byte to find the addressing
        mode. */
     if (mod < 3) {
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 destval;
-
-            DECODE_PRINTF("DWORD PTR ");
-            destoffset = decode_rmXX_address(mod, rl);
-            DECODE_PRINTF(",1\n");
-            destval = fetch_data_long(destoffset);
-            TRACE_AND_STEP();
-            destval = (*opcD1_long_operation[rh]) (destval, 1);
-            store_data_long(destoffset, destval);
-        } else {
-            u16 destval;
-
-            DECODE_PRINTF("WORD PTR ");
-            destoffset = decode_rmXX_address(mod, rl);
-            DECODE_PRINTF(",1\n");
-            destval = fetch_data_word(destoffset);
-            TRACE_AND_STEP();
-            destval = (*opcD1_word_operation[rh]) (destval, 1);
-            store_data_word(destoffset, destval);
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 destval;
+
+           DECODE_PRINTF("DWORD PTR ");
+           destoffset = decode_rmXX_address(mod, rl);
+           DECODE_PRINTF(",1\n");
+           destval = fetch_data_long(destoffset);
+           TRACE_AND_STEP();
+           destval = (*opcD1_long_operation[rh]) (destval, 1);
+           store_data_long(destoffset, destval);
+       } else {
+           u16 destval;
+
+           DECODE_PRINTF("WORD PTR ");
+           destoffset = decode_rmXX_address(mod, rl);
+           DECODE_PRINTF(",1\n");
+           destval = fetch_data_word(destoffset);
+           TRACE_AND_STEP();
+           destval = (*opcD1_word_operation[rh]) (destval, 1);
+           store_data_word(destoffset, destval);
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
                        u32 destval;
                        u32 *destreg;
 
-            destreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF(",1\n");
-            TRACE_AND_STEP();
-            destval = (*opcD1_long_operation[rh]) (*destreg, 1);
-            *destreg = destval;
-        } else {
+           destreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF(",1\n");
+           TRACE_AND_STEP();
+           destval = (*opcD1_long_operation[rh]) (*destreg, 1);
+           *destreg = destval;
+       } else {
                        u16 destval;
                        u16 *destreg;
 
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF(",1\n");
-            TRACE_AND_STEP();
-            destval = (*opcD1_word_operation[rh]) (*destreg, 1);
-            *destreg = destval;
-        }
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF(",1\n");
+           TRACE_AND_STEP();
+           destval = (*opcD1_word_operation[rh]) (*destreg, 1);
+           *destreg = destval;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -3811,55 +3811,55 @@ void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1))
     FETCH_DECODE_MODRM(mod, rh, rl);
 #ifdef DEBUG
     if (DEBUG_DECODE()) {
-        /* XXX DECODE_PRINTF may be changed to something more
-           general, so that it is important to leave the strings
-           in the same format, even though the result is that the
-           above test is done twice. */
-        switch (rh) {
-        case 0:
-            DECODE_PRINTF("ROL\t");
-            break;
-        case 1:
-            DECODE_PRINTF("ROR\t");
-            break;
-        case 2:
-            DECODE_PRINTF("RCL\t");
-            break;
-        case 3:
-            DECODE_PRINTF("RCR\t");
-            break;
-        case 4:
-            DECODE_PRINTF("SHL\t");
-            break;
-        case 5:
-            DECODE_PRINTF("SHR\t");
-            break;
-        case 6:
-            DECODE_PRINTF("SAL\t");
-            break;
-        case 7:
-            DECODE_PRINTF("SAR\t");
-            break;
-        }
+       /* XXX DECODE_PRINTF may be changed to something more
+          general, so that it is important to leave the strings
+          in the same format, even though the result is that the
+          above test is done twice. */
+       switch (rh) {
+       case 0:
+           DECODE_PRINTF("ROL\t");
+           break;
+       case 1:
+           DECODE_PRINTF("ROR\t");
+           break;
+       case 2:
+           DECODE_PRINTF("RCL\t");
+           break;
+       case 3:
+           DECODE_PRINTF("RCR\t");
+           break;
+       case 4:
+           DECODE_PRINTF("SHL\t");
+           break;
+       case 5:
+           DECODE_PRINTF("SHR\t");
+           break;
+       case 6:
+           DECODE_PRINTF("SAL\t");
+           break;
+       case 7:
+           DECODE_PRINTF("SAR\t");
+           break;
+       }
     }
 #endif
     /* know operation, decode the mod byte to find the addressing
        mode. */
     amt = M.x86.R_CL;
     if (mod < 3) {
-        DECODE_PRINTF("BYTE PTR ");
-        destoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF(",CL\n");
-        destval = fetch_data_byte(destoffset);
-        TRACE_AND_STEP();
-        destval = (*opcD0_byte_operation[rh]) (destval, amt);
-        store_data_byte(destoffset, destval);
-    } else {                     /* register to register */
-        destreg = DECODE_RM_BYTE_REGISTER(rl);
-        DECODE_PRINTF(",CL\n");
-        TRACE_AND_STEP();
-        destval = (*opcD0_byte_operation[rh]) (*destreg, amt);
-        *destreg = destval;
+       DECODE_PRINTF("BYTE PTR ");
+       destoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF(",CL\n");
+       destval = fetch_data_byte(destoffset);
+       TRACE_AND_STEP();
+       destval = (*opcD0_byte_operation[rh]) (destval, amt);
+       store_data_byte(destoffset, destval);
+    } else {                    /* register to register */
+       destreg = DECODE_RM_BYTE_REGISTER(rl);
+       DECODE_PRINTF(",CL\n");
+       TRACE_AND_STEP();
+       destval = (*opcD0_byte_operation[rh]) (*destreg, amt);
+       *destreg = destval;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -3884,79 +3884,79 @@ void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1))
     FETCH_DECODE_MODRM(mod, rh, rl);
 #ifdef DEBUG
     if (DEBUG_DECODE()) {
-        /* XXX DECODE_PRINTF may be changed to something more
-           general, so that it is important to leave the strings
-           in the same format, even though the result is that the
-           above test is done twice. */
-        switch (rh) {
-        case 0:
-            DECODE_PRINTF("ROL\t");
-            break;
-        case 1:
-            DECODE_PRINTF("ROR\t");
-            break;
-        case 2:
-            DECODE_PRINTF("RCL\t");
-            break;
-        case 3:
-            DECODE_PRINTF("RCR\t");
-            break;
-        case 4:
-            DECODE_PRINTF("SHL\t");
-            break;
-        case 5:
-            DECODE_PRINTF("SHR\t");
-            break;
-        case 6:
-            DECODE_PRINTF("SAL\t");
-            break;
-        case 7:
-            DECODE_PRINTF("SAR\t");
-            break;
-        }
+       /* XXX DECODE_PRINTF may be changed to something more
+          general, so that it is important to leave the strings
+          in the same format, even though the result is that the
+          above test is done twice. */
+       switch (rh) {
+       case 0:
+           DECODE_PRINTF("ROL\t");
+           break;
+       case 1:
+           DECODE_PRINTF("ROR\t");
+           break;
+       case 2:
+           DECODE_PRINTF("RCL\t");
+           break;
+       case 3:
+           DECODE_PRINTF("RCR\t");
+           break;
+       case 4:
+           DECODE_PRINTF("SHL\t");
+           break;
+       case 5:
+           DECODE_PRINTF("SHR\t");
+           break;
+       case 6:
+           DECODE_PRINTF("SAL\t");
+           break;
+       case 7:
+           DECODE_PRINTF("SAR\t");
+           break;
+       }
     }
 #endif
     /* know operation, decode the mod byte to find the addressing
        mode. */
     amt = M.x86.R_CL;
     if (mod < 3) {
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 destval;
-
-            DECODE_PRINTF("DWORD PTR ");
-            destoffset = decode_rmXX_address(mod, rl);
-            DECODE_PRINTF(",CL\n");
-            destval = fetch_data_long(destoffset);
-            TRACE_AND_STEP();
-            destval = (*opcD1_long_operation[rh]) (destval, amt);
-            store_data_long(destoffset, destval);
-        } else {
-            u16 destval;
-
-            DECODE_PRINTF("WORD PTR ");
-            destoffset = decode_rmXX_address(mod, rl);
-            DECODE_PRINTF(",CL\n");
-            destval = fetch_data_word(destoffset);
-            TRACE_AND_STEP();
-            destval = (*opcD1_word_operation[rh]) (destval, amt);
-            store_data_word(destoffset, destval);
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg;
-
-            destreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF(",CL\n");
-            TRACE_AND_STEP();
-            *destreg = (*opcD1_long_operation[rh]) (*destreg, amt);
-        } else {
-            u16 *destreg;
-
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF(",CL\n");
-            TRACE_AND_STEP();
-            *destreg = (*opcD1_word_operation[rh]) (*destreg, amt);
-        }
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 destval;
+
+           DECODE_PRINTF("DWORD PTR ");
+           destoffset = decode_rmXX_address(mod, rl);
+           DECODE_PRINTF(",CL\n");
+           destval = fetch_data_long(destoffset);
+           TRACE_AND_STEP();
+           destval = (*opcD1_long_operation[rh]) (destval, amt);
+           store_data_long(destoffset, destval);
+       } else {
+           u16 destval;
+
+           DECODE_PRINTF("WORD PTR ");
+           destoffset = decode_rmXX_address(mod, rl);
+           DECODE_PRINTF(",CL\n");
+           destval = fetch_data_word(destoffset);
+           TRACE_AND_STEP();
+           destval = (*opcD1_word_operation[rh]) (destval, amt);
+           store_data_word(destoffset, destval);
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg;
+
+           destreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF(",CL\n");
+           TRACE_AND_STEP();
+           *destreg = (*opcD1_long_operation[rh]) (*destreg, amt);
+       } else {
+           u16 *destreg;
+
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF(",CL\n");
+           TRACE_AND_STEP();
+           *destreg = (*opcD1_word_operation[rh]) (*destreg, amt);
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -3974,9 +3974,9 @@ void x86emuOp_aam(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("AAM\n");
     a = fetch_byte_imm();      /* this is a stupid encoding. */
     if (a != 10) {
-        DECODE_PRINTF("ERROR DECODING AAM\n");
-        TRACE_REGS();
-        HALT_SYS();
+       DECODE_PRINTF("ERROR DECODING AAM\n");
+       TRACE_REGS();
+       HALT_SYS();
     }
     TRACE_AND_STEP();
     /* note the type change here --- returning AL and AH in AX. */
@@ -4021,7 +4021,7 @@ void x86emuOp_xlat(u8 X86EMU_UNUSED(op1))
     END_OF_INSTR();
 }
 
-/* instuctions  D8 .. DF are in i87_ops.c */
+/* instuctions D8 .. DF are in i87_ops.c */
 
 /****************************************************************************
 REMARKS:
@@ -4038,8 +4038,8 @@ void x86emuOp_loopne(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF2("%04x\n", ip);
     TRACE_AND_STEP();
     M.x86.R_CX -= 1;
-    if (M.x86.R_CX != 0 && !ACCESS_FLAG(F_ZF))      /* CX != 0 and !ZF */
-        M.x86.R_IP = ip;
+    if (M.x86.R_CX != 0 && !ACCESS_FLAG(F_ZF))     /* CX != 0 and !ZF */
+       M.x86.R_IP = ip;
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
 }
@@ -4059,8 +4059,8 @@ void x86emuOp_loope(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF2("%04x\n", ip);
     TRACE_AND_STEP();
     M.x86.R_CX -= 1;
-    if (M.x86.R_CX != 0 && ACCESS_FLAG(F_ZF))       /* CX != 0 and ZF */
-        M.x86.R_IP = ip;
+    if (M.x86.R_CX != 0 && ACCESS_FLAG(F_ZF))      /* CX != 0 and ZF */
+       M.x86.R_IP = ip;
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
 }
@@ -4081,7 +4081,7 @@ void x86emuOp_loop(u8 X86EMU_UNUSED(op1))
     TRACE_AND_STEP();
     M.x86.R_CX -= 1;
     if (M.x86.R_CX != 0)
-        M.x86.R_IP = ip;
+       M.x86.R_IP = ip;
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
 }
@@ -4093,7 +4093,7 @@ Handles opcode 0xe3
 void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1))
 {
     u16 target;
-    s8  offset;
+    s8 offset;
 
     /* jump to byte offset if overflow flag is set */
     START_OF_INSTR();
@@ -4103,7 +4103,7 @@ void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF2("%x\n", target);
     TRACE_AND_STEP();
     if (M.x86.R_CX == 0)
-        M.x86.R_IP = target;
+       M.x86.R_IP = target;
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
 }
@@ -4138,15 +4138,15 @@ void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("IN\t");
        port = (u8) fetch_byte_imm();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF2("EAX,%x\n", port);
+       DECODE_PRINTF2("EAX,%x\n", port);
     } else {
-        DECODE_PRINTF2("AX,%x\n", port);
+       DECODE_PRINTF2("AX,%x\n", port);
     }
     TRACE_AND_STEP();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        M.x86.R_EAX = (*sys_inl)(port);
+       M.x86.R_EAX = (*sys_inl)(port);
     } else {
-        M.x86.R_AX = (*sys_inw)(port);
+       M.x86.R_AX = (*sys_inw)(port);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -4182,15 +4182,15 @@ void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF("OUT\t");
        port = (u8) fetch_byte_imm();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF2("%x,EAX\n", port);
+       DECODE_PRINTF2("%x,EAX\n", port);
     } else {
-        DECODE_PRINTF2("%x,AX\n", port);
+       DECODE_PRINTF2("%x,AX\n", port);
     }
     TRACE_AND_STEP();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        (*sys_outl)(port, M.x86.R_EAX);
+       (*sys_outl)(port, M.x86.R_EAX);
     } else {
-        (*sys_outw)(port, M.x86.R_AX);
+       (*sys_outw)(port, M.x86.R_AX);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -4207,7 +4207,7 @@ void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1))
     START_OF_INSTR();
        DECODE_PRINTF("CALL\t");
        ip = (s16) fetch_word_imm();
-       ip += (s16) M.x86.R_IP;    /* CHECK SIGN */
+       ip += (s16) M.x86.R_IP;    /* CHECK SIGN */
        DECODE_PRINTF2("%04x\n", ip);
        CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, "");
     TRACE_AND_STEP();
@@ -4299,15 +4299,15 @@ void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF("IN\tEAX,DX\n");
+       DECODE_PRINTF("IN\tEAX,DX\n");
     } else {
-        DECODE_PRINTF("IN\tAX,DX\n");
+       DECODE_PRINTF("IN\tAX,DX\n");
     }
     TRACE_AND_STEP();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        M.x86.R_EAX = (*sys_inl)(M.x86.R_DX);
+       M.x86.R_EAX = (*sys_inl)(M.x86.R_DX);
     } else {
-        M.x86.R_AX = (*sys_inw)(M.x86.R_DX);
+       M.x86.R_AX = (*sys_inw)(M.x86.R_DX);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -4335,15 +4335,15 @@ void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1))
 {
     START_OF_INSTR();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        DECODE_PRINTF("OUT\tDX,EAX\n");
+       DECODE_PRINTF("OUT\tDX,EAX\n");
     } else {
-        DECODE_PRINTF("OUT\tDX,AX\n");
+       DECODE_PRINTF("OUT\tDX,AX\n");
     }
     TRACE_AND_STEP();
     if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-        (*sys_outl)(M.x86.R_DX, M.x86.R_EAX);
+       (*sys_outl)(M.x86.R_DX, M.x86.R_EAX);
     } else {
-        (*sys_outw)(M.x86.R_DX, M.x86.R_AX);
+       (*sys_outw)(M.x86.R_DX, M.x86.R_AX);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -4438,100 +4438,100 @@ void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1))
     FETCH_DECODE_MODRM(mod, rh, rl);
     DECODE_PRINTF(opF6_names[rh]);
     if (mod < 3) {
-        DECODE_PRINTF("BYTE PTR ");
-        destoffset = decode_rmXX_address(mod, rl);
-        destval = fetch_data_byte(destoffset);
-
-        switch (rh) {
-        case 0:         /* test byte imm */
-            DECODE_PRINTF(",");
-            srcval = fetch_byte_imm();
-            DECODE_PRINTF2("%02x\n", srcval);
-            TRACE_AND_STEP();
-            test_byte(destval, srcval);
-            break;
-        case 1:
-            DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
-            HALT_SYS();
-            break;
-        case 2:
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            destval = not_byte(destval);
-            store_data_byte(destoffset, destval);
-            break;
-        case 3:
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            destval = neg_byte(destval);
-            store_data_byte(destoffset, destval);
-            break;
-        case 4:
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            mul_byte(destval);
-            break;
-        case 5:
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            imul_byte(destval);
-            break;
-        case 6:
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            div_byte(destval);
-            break;
-        default:
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            idiv_byte(destval);
-            break;
-        }
-    } else {                     /* mod=11 */
-        destreg = DECODE_RM_BYTE_REGISTER(rl);
-        switch (rh) {
-        case 0:         /* test byte imm */
-            DECODE_PRINTF(",");
-            srcval = fetch_byte_imm();
-            DECODE_PRINTF2("%02x\n", srcval);
-            TRACE_AND_STEP();
-            test_byte(*destreg, srcval);
-            break;
-        case 1:
-            DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
-            HALT_SYS();
-            break;
-        case 2:
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = not_byte(*destreg);
-            break;
-        case 3:
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = neg_byte(*destreg);
-            break;
-        case 4:
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            mul_byte(*destreg);      /*!!!  */
-            break;
-        case 5:
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            imul_byte(*destreg);
-            break;
-        case 6:
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            div_byte(*destreg);
-            break;
-        default:
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            idiv_byte(*destreg);
-            break;
-        }
+       DECODE_PRINTF("BYTE PTR ");
+       destoffset = decode_rmXX_address(mod, rl);
+       destval = fetch_data_byte(destoffset);
+
+       switch (rh) {
+       case 0:         /* test byte imm */
+           DECODE_PRINTF(",");
+           srcval = fetch_byte_imm();
+           DECODE_PRINTF2("%02x\n", srcval);
+           TRACE_AND_STEP();
+           test_byte(destval, srcval);
+           break;
+       case 1:
+           DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+           HALT_SYS();
+           break;
+       case 2:
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           destval = not_byte(destval);
+           store_data_byte(destoffset, destval);
+           break;
+       case 3:
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           destval = neg_byte(destval);
+           store_data_byte(destoffset, destval);
+           break;
+       case 4:
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           mul_byte(destval);
+           break;
+       case 5:
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           imul_byte(destval);
+           break;
+       case 6:
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           div_byte(destval);
+           break;
+       default:
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           idiv_byte(destval);
+           break;
+       }
+    } else {                    /* mod=11 */
+       destreg = DECODE_RM_BYTE_REGISTER(rl);
+       switch (rh) {
+       case 0:         /* test byte imm */
+           DECODE_PRINTF(",");
+           srcval = fetch_byte_imm();
+           DECODE_PRINTF2("%02x\n", srcval);
+           TRACE_AND_STEP();
+           test_byte(*destreg, srcval);
+           break;
+       case 1:
+           DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+           HALT_SYS();
+           break;
+       case 2:
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = not_byte(*destreg);
+           break;
+       case 3:
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = neg_byte(*destreg);
+           break;
+       case 4:
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           mul_byte(*destreg);      /*!!!  */
+           break;
+       case 5:
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           imul_byte(*destreg);
+           break;
+       case 6:
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           div_byte(*destreg);
+           break;
+       default:
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           idiv_byte(*destreg);
+           break;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -4551,213 +4551,213 @@ void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1))
     DECODE_PRINTF(opF6_names[rh]);
     if (mod < 3) {
 
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 destval, srcval;
-
-            DECODE_PRINTF("DWORD PTR ");
-            destoffset = decode_rmXX_address(mod, rl);
-            destval = fetch_data_long(destoffset);
-
-            switch (rh) {
-            case 0:
-                DECODE_PRINTF(",");
-                srcval = fetch_long_imm();
-                DECODE_PRINTF2("%x\n", srcval);
-                TRACE_AND_STEP();
-                test_long(destval, srcval);
-                break;
-            case 1:
-                DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
-                HALT_SYS();
-                break;
-            case 2:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                destval = not_long(destval);
-                store_data_long(destoffset, destval);
-                break;
-            case 3:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                destval = neg_long(destval);
-                store_data_long(destoffset, destval);
-                break;
-            case 4:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                mul_long(destval);
-                break;
-            case 5:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                imul_long(destval);
-                break;
-            case 6:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                div_long(destval);
-                break;
-            case 7:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                idiv_long(destval);
-                break;
-            }
-        } else {
-            u16 destval, srcval;
-
-            DECODE_PRINTF("WORD PTR ");
-            destoffset = decode_rmXX_address(mod, rl);
-            destval = fetch_data_word(destoffset);
-
-            switch (rh) {
-            case 0:         /* test word imm */
-                DECODE_PRINTF(",");
-                srcval = fetch_word_imm();
-                DECODE_PRINTF2("%x\n", srcval);
-                TRACE_AND_STEP();
-                test_word(destval, srcval);
-                break;
-            case 1:
-                DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
-                HALT_SYS();
-                break;
-            case 2:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                destval = not_word(destval);
-                store_data_word(destoffset, destval);
-                break;
-            case 3:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                destval = neg_word(destval);
-                store_data_word(destoffset, destval);
-                break;
-            case 4:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                mul_word(destval);
-                break;
-            case 5:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                imul_word(destval);
-                break;
-            case 6:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                div_word(destval);
-                break;
-            case 7:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                idiv_word(destval);
-                break;
-            }
-        }
-
-    } else {                     /* mod=11 */
-
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg;
-            u32 srcval;
-
-            destreg = DECODE_RM_LONG_REGISTER(rl);
-
-            switch (rh) {
-            case 0:         /* test word imm */
-                DECODE_PRINTF(",");
-                srcval = fetch_long_imm();
-                DECODE_PRINTF2("%x\n", srcval);
-                TRACE_AND_STEP();
-                test_long(*destreg, srcval);
-                break;
-            case 1:
-                DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
-                HALT_SYS();
-                break;
-            case 2:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                *destreg = not_long(*destreg);
-                break;
-            case 3:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                *destreg = neg_long(*destreg);
-                break;
-            case 4:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                mul_long(*destreg);      /*!!!  */
-                break;
-            case 5:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                imul_long(*destreg);
-                break;
-            case 6:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                div_long(*destreg);
-                break;
-            case 7:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                idiv_long(*destreg);
-                break;
-            }
-        } else {
-            u16 *destreg;
-            u16 srcval;
-
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-
-            switch (rh) {
-            case 0:         /* test word imm */
-                DECODE_PRINTF(",");
-                srcval = fetch_word_imm();
-                DECODE_PRINTF2("%x\n", srcval);
-                TRACE_AND_STEP();
-                test_word(*destreg, srcval);
-                break;
-            case 1:
-                DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
-                HALT_SYS();
-                break;
-            case 2:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                *destreg = not_word(*destreg);
-                break;
-            case 3:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                *destreg = neg_word(*destreg);
-                break;
-            case 4:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                mul_word(*destreg);      /*!!!  */
-                break;
-            case 5:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                imul_word(*destreg);
-                break;
-            case 6:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                div_word(*destreg);
-                break;
-            case 7:
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                idiv_word(*destreg);
-                break;
-            }
-        }
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 destval, srcval;
+
+           DECODE_PRINTF("DWORD PTR ");
+           destoffset = decode_rmXX_address(mod, rl);
+           destval = fetch_data_long(destoffset);
+
+           switch (rh) {
+           case 0:
+               DECODE_PRINTF(",");
+               srcval = fetch_long_imm();
+               DECODE_PRINTF2("%x\n", srcval);
+               TRACE_AND_STEP();
+               test_long(destval, srcval);
+               break;
+           case 1:
+               DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
+               HALT_SYS();
+               break;
+           case 2:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               destval = not_long(destval);
+               store_data_long(destoffset, destval);
+               break;
+           case 3:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               destval = neg_long(destval);
+               store_data_long(destoffset, destval);
+               break;
+           case 4:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               mul_long(destval);
+               break;
+           case 5:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               imul_long(destval);
+               break;
+           case 6:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               div_long(destval);
+               break;
+           case 7:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               idiv_long(destval);
+               break;
+           }
+       } else {
+           u16 destval, srcval;
+
+           DECODE_PRINTF("WORD PTR ");
+           destoffset = decode_rmXX_address(mod, rl);
+           destval = fetch_data_word(destoffset);
+
+           switch (rh) {
+           case 0:         /* test word imm */
+               DECODE_PRINTF(",");
+               srcval = fetch_word_imm();
+               DECODE_PRINTF2("%x\n", srcval);
+               TRACE_AND_STEP();
+               test_word(destval, srcval);
+               break;
+           case 1:
+               DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
+               HALT_SYS();
+               break;
+           case 2:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               destval = not_word(destval);
+               store_data_word(destoffset, destval);
+               break;
+           case 3:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               destval = neg_word(destval);
+               store_data_word(destoffset, destval);
+               break;
+           case 4:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               mul_word(destval);
+               break;
+           case 5:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               imul_word(destval);
+               break;
+           case 6:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               div_word(destval);
+               break;
+           case 7:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               idiv_word(destval);
+               break;
+           }
+       }
+
+    } else {                    /* mod=11 */
+
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg;
+           u32 srcval;
+
+           destreg = DECODE_RM_LONG_REGISTER(rl);
+
+           switch (rh) {
+           case 0:         /* test word imm */
+               DECODE_PRINTF(",");
+               srcval = fetch_long_imm();
+               DECODE_PRINTF2("%x\n", srcval);
+               TRACE_AND_STEP();
+               test_long(*destreg, srcval);
+               break;
+           case 1:
+               DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+               HALT_SYS();
+               break;
+           case 2:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               *destreg = not_long(*destreg);
+               break;
+           case 3:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               *destreg = neg_long(*destreg);
+               break;
+           case 4:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               mul_long(*destreg);      /*!!!  */
+               break;
+           case 5:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               imul_long(*destreg);
+               break;
+           case 6:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               div_long(*destreg);
+               break;
+           case 7:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               idiv_long(*destreg);
+               break;
+           }
+       } else {
+           u16 *destreg;
+           u16 srcval;
+
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+
+           switch (rh) {
+           case 0:         /* test word imm */
+               DECODE_PRINTF(",");
+               srcval = fetch_word_imm();
+               DECODE_PRINTF2("%x\n", srcval);
+               TRACE_AND_STEP();
+               test_word(*destreg, srcval);
+               break;
+           case 1:
+               DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+               HALT_SYS();
+               break;
+           case 2:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               *destreg = not_word(*destreg);
+               break;
+           case 3:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               *destreg = neg_word(*destreg);
+               break;
+           case 4:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               mul_word(*destreg);      /*!!!  */
+               break;
+           case 5:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               imul_word(*destreg);
+               break;
+           case 6:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               div_word(*destreg);
+               break;
+           case 7:
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               idiv_word(*destreg);
+               break;
+           }
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -4869,49 +4869,49 @@ void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1))
     FETCH_DECODE_MODRM(mod, rh, rl);
 #ifdef DEBUG
     if (DEBUG_DECODE()) {
-        /* XXX DECODE_PRINTF may be changed to something more
-           general, so that it is important to leave the strings
-           in the same format, even though the result is that the
-           above test is done twice. */
-
-        switch (rh) {
-        case 0:
-            DECODE_PRINTF("INC\t");
-            break;
-        case 1:
-            DECODE_PRINTF("DEC\t");
-            break;
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-        case 6:
-        case 7:
-            DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod);
-            HALT_SYS();
-            break;
-        }
+       /* XXX DECODE_PRINTF may be changed to something more
+          general, so that it is important to leave the strings
+          in the same format, even though the result is that the
+          above test is done twice. */
+
+       switch (rh) {
+       case 0:
+           DECODE_PRINTF("INC\t");
+           break;
+       case 1:
+           DECODE_PRINTF("DEC\t");
+           break;
+       case 2:
+       case 3:
+       case 4:
+       case 5:
+       case 6:
+       case 7:
+           DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod);
+           HALT_SYS();
+           break;
+       }
     }
 #endif
     if (mod < 3) {
-        DECODE_PRINTF("BYTE PTR ");
-        destoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF("\n");
-        destval = fetch_data_byte(destoffset);
-        TRACE_AND_STEP();
-        if (rh == 0)
-          destval = inc_byte(destval);
-        else
-          destval = dec_byte(destval);
-        store_data_byte(destoffset, destval);
+       DECODE_PRINTF("BYTE PTR ");
+       destoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF("\n");
+       destval = fetch_data_byte(destoffset);
+       TRACE_AND_STEP();
+       if (rh == 0)
+         destval = inc_byte(destval);
+       else
+         destval = dec_byte(destval);
+       store_data_byte(destoffset, destval);
     } else {
-        destreg = DECODE_RM_BYTE_REGISTER(rl);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        if (rh == 0)
-          *destreg = inc_byte(*destreg);
-        else
-          *destreg = dec_byte(*destreg);
+       destreg = DECODE_RM_BYTE_REGISTER(rl);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       if (rh == 0)
+         *destreg = inc_byte(*destreg);
+       else
+         *destreg = dec_byte(*destreg);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -4933,207 +4933,207 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1))
     FETCH_DECODE_MODRM(mod, rh, rl);
 #ifdef DEBUG
     if (DEBUG_DECODE()) {
-        /* XXX DECODE_PRINTF may be changed to something more
-           general, so that it is important to leave the strings
-           in the same format, even though the result is that the
-           above test is done twice. */
-
-        switch (rh) {
-        case 0:
-            if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-                DECODE_PRINTF("INC\tDWORD PTR ");
-            } else {
-                DECODE_PRINTF("INC\tWORD PTR ");
-            }
-            break;
-        case 1:
-            if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-                DECODE_PRINTF("DEC\tDWORD PTR ");
-            } else {
-                DECODE_PRINTF("DEC\tWORD PTR ");
-            }
-            break;
-        case 2:
-            DECODE_PRINTF("CALL\t ");
-            break;
-        case 3:
-            DECODE_PRINTF("CALL\tFAR ");
-            break;
-        case 4:
-            DECODE_PRINTF("JMP\t");
-            break;
-        case 5:
-            DECODE_PRINTF("JMP\tFAR ");
-            break;
-        case 6:
-            DECODE_PRINTF("PUSH\t");
-            break;
-        case 7:
-            DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t");
-            HALT_SYS();
-            break;
-        }
+       /* XXX DECODE_PRINTF may be changed to something more
+          general, so that it is important to leave the strings
+          in the same format, even though the result is that the
+          above test is done twice. */
+
+       switch (rh) {
+       case 0:
+           if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+               DECODE_PRINTF("INC\tDWORD PTR ");
+           } else {
+               DECODE_PRINTF("INC\tWORD PTR ");
+           }
+           break;
+       case 1:
+           if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+               DECODE_PRINTF("DEC\tDWORD PTR ");
+           } else {
+               DECODE_PRINTF("DEC\tWORD PTR ");
+           }
+           break;
+       case 2:
+           DECODE_PRINTF("CALL\t ");
+           break;
+       case 3:
+           DECODE_PRINTF("CALL\tFAR ");
+           break;
+       case 4:
+           DECODE_PRINTF("JMP\t");
+           break;
+       case 5:
+           DECODE_PRINTF("JMP\tFAR ");
+           break;
+       case 6:
+           DECODE_PRINTF("PUSH\t");
+           break;
+       case 7:
+           DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t");
+           HALT_SYS();
+           break;
+       }
     }
 #endif
     if (mod < 3) {
-        destoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF("\n");
-        switch (rh) {
-        case 0:         /* inc word ptr ... */
-            if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-                u32 destval;
-
-                destval = fetch_data_long(destoffset);
-                TRACE_AND_STEP();
-                destval = inc_long(destval);
-                store_data_long(destoffset, destval);
-            } else {
-                u16 destval;
-
-                destval = fetch_data_word(destoffset);
-                TRACE_AND_STEP();
-                destval = inc_word(destval);
-                store_data_word(destoffset, destval);
-            }
-            break;
-        case 1:         /* dec word ptr ... */
-            if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-                u32 destval;
-
-                destval = fetch_data_long(destoffset);
-                TRACE_AND_STEP();
-                destval = dec_long(destval);
-                store_data_long(destoffset, destval);
-            } else {
-                u16 destval;
-
-                destval = fetch_data_word(destoffset);
-                TRACE_AND_STEP();
-                destval = dec_word(destval);
-                store_data_word(destoffset, destval);
-            }
-            break;
-        case 2:         /* call word ptr ... */
-            destval = fetch_data_word(destoffset);
-            TRACE_AND_STEP();
-            push_word(M.x86.R_IP);
-            M.x86.R_IP = destval;
-            break;
-        case 3:         /* call far ptr ... */
-            destval = fetch_data_word(destoffset);
-            destval2 = fetch_data_word(destoffset + 2);
-            TRACE_AND_STEP();
-            push_word(M.x86.R_CS);
-            M.x86.R_CS = destval2;
-            push_word(M.x86.R_IP);
-            M.x86.R_IP = destval;
-            break;
-        case 4:         /* jmp word ptr ... */
-            destval = fetch_data_word(destoffset);
-            TRACE_AND_STEP();
-            M.x86.R_IP = destval;
-            break;
-        case 5:         /* jmp far ptr ... */
-            destval = fetch_data_word(destoffset);
-            destval2 = fetch_data_word(destoffset + 2);
-            TRACE_AND_STEP();
-            M.x86.R_IP = destval;
-            M.x86.R_CS = destval2;
-            break;
-        case 6:         /*  push word ptr ... */
-            if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-                u32 destval;
-
-                destval = fetch_data_long(destoffset);
-                TRACE_AND_STEP();
-                push_long(destval);
-            } else {
-                u16 destval;
-
-                destval = fetch_data_word(destoffset);
-                TRACE_AND_STEP();
-                push_word(destval);
-            }
-            break;
-        }
+       destoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF("\n");
+       switch (rh) {
+       case 0:         /* inc word ptr ... */
+           if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+               u32 destval;
+
+               destval = fetch_data_long(destoffset);
+               TRACE_AND_STEP();
+               destval = inc_long(destval);
+               store_data_long(destoffset, destval);
+           } else {
+               u16 destval;
+
+               destval = fetch_data_word(destoffset);
+               TRACE_AND_STEP();
+               destval = inc_word(destval);
+               store_data_word(destoffset, destval);
+           }
+           break;
+       case 1:         /* dec word ptr ... */
+           if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+               u32 destval;
+
+               destval = fetch_data_long(destoffset);
+               TRACE_AND_STEP();
+               destval = dec_long(destval);
+               store_data_long(destoffset, destval);
+           } else {
+               u16 destval;
+
+               destval = fetch_data_word(destoffset);
+               TRACE_AND_STEP();
+               destval = dec_word(destval);
+               store_data_word(destoffset, destval);
+           }
+           break;
+       case 2:         /* call word ptr ... */
+           destval = fetch_data_word(destoffset);
+           TRACE_AND_STEP();
+           push_word(M.x86.R_IP);
+           M.x86.R_IP = destval;
+           break;
+       case 3:         /* call far ptr ... */
+           destval = fetch_data_word(destoffset);
+           destval2 = fetch_data_word(destoffset + 2);
+           TRACE_AND_STEP();
+           push_word(M.x86.R_CS);
+           M.x86.R_CS = destval2;
+           push_word(M.x86.R_IP);
+           M.x86.R_IP = destval;
+           break;
+       case 4:         /* jmp word ptr ... */
+           destval = fetch_data_word(destoffset);
+           TRACE_AND_STEP();
+           M.x86.R_IP = destval;
+           break;
+       case 5:         /* jmp far ptr ... */
+           destval = fetch_data_word(destoffset);
+           destval2 = fetch_data_word(destoffset + 2);
+           TRACE_AND_STEP();
+           M.x86.R_IP = destval;
+           M.x86.R_CS = destval2;
+           break;
+       case 6:         /*  push word ptr ... */
+           if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+               u32 destval;
+
+               destval = fetch_data_long(destoffset);
+               TRACE_AND_STEP();
+               push_long(destval);
+           } else {
+               u16 destval;
+
+               destval = fetch_data_word(destoffset);
+               TRACE_AND_STEP();
+               push_word(destval);
+           }
+           break;
+       }
     } else {
-        switch (rh) {
-        case 0:
-            if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-                u32 *destreg;
-
-                destreg = DECODE_RM_LONG_REGISTER(rl);
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                *destreg = inc_long(*destreg);
-            } else {
-                u16 *destreg;
-
-                destreg = DECODE_RM_WORD_REGISTER(rl);
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                *destreg = inc_word(*destreg);
-            }
-            break;
-        case 1:
-            if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-                u32 *destreg;
-
-                destreg = DECODE_RM_LONG_REGISTER(rl);
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                *destreg = dec_long(*destreg);
-            } else {
-                u16 *destreg;
-
-                destreg = DECODE_RM_WORD_REGISTER(rl);
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                *destreg = dec_word(*destreg);
-            }
-            break;
-        case 2:         /* call word ptr ... */
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            push_word(M.x86.R_IP);
-            M.x86.R_IP = *destreg;
-            break;
-        case 3:         /* jmp far ptr ... */
-            DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n");
-            TRACE_AND_STEP();
-            HALT_SYS();
-            break;
-
-        case 4:         /* jmp  ... */
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            M.x86.R_IP = (u16) (*destreg);
-            break;
-        case 5:         /* jmp far ptr ... */
-            DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n");
-            TRACE_AND_STEP();
-            HALT_SYS();
-            break;
-        case 6:
-            if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-                u32 *destreg;
-
-                destreg = DECODE_RM_LONG_REGISTER(rl);
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                push_long(*destreg);
-            } else {
-                u16 *destreg;
-
-                destreg = DECODE_RM_WORD_REGISTER(rl);
-                DECODE_PRINTF("\n");
-                TRACE_AND_STEP();
-                push_word(*destreg);
-            }
-            break;
-        }
+       switch (rh) {
+       case 0:
+           if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+               u32 *destreg;
+
+               destreg = DECODE_RM_LONG_REGISTER(rl);
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               *destreg = inc_long(*destreg);
+           } else {
+               u16 *destreg;
+
+               destreg = DECODE_RM_WORD_REGISTER(rl);
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               *destreg = inc_word(*destreg);
+           }
+           break;
+       case 1:
+           if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+               u32 *destreg;
+
+               destreg = DECODE_RM_LONG_REGISTER(rl);
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               *destreg = dec_long(*destreg);
+           } else {
+               u16 *destreg;
+
+               destreg = DECODE_RM_WORD_REGISTER(rl);
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               *destreg = dec_word(*destreg);
+           }
+           break;
+       case 2:         /* call word ptr ... */
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           push_word(M.x86.R_IP);
+           M.x86.R_IP = *destreg;
+           break;
+       case 3:         /* jmp far ptr ... */
+           DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n");
+           TRACE_AND_STEP();
+           HALT_SYS();
+           break;
+
+       case 4:         /* jmp  ... */
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           M.x86.R_IP = (u16) (*destreg);
+           break;
+       case 5:         /* jmp far ptr ... */
+           DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n");
+           TRACE_AND_STEP();
+           HALT_SYS();
+           break;
+       case 6:
+           if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+               u32 *destreg;
+
+               destreg = DECODE_RM_LONG_REGISTER(rl);
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               push_long(*destreg);
+           } else {
+               u16 *destreg;
+
+               destreg = DECODE_RM_WORD_REGISTER(rl);
+               DECODE_PRINTF("\n");
+               TRACE_AND_STEP();
+               push_word(*destreg);
+           }
+           break;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
index 2412b24cd80db8bd735d5f6dfbc29f264f9396ee..631a340ed2bd38a094e675bf28801a7df0a4467b 100644 (file)
@@ -1,13 +1,13 @@
 /****************************************************************************
 *
-*                       Realmode X86 Emulator Library
+*                      Realmode X86 Emulator Library
 *
 *  Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
 *  Jason Jin <Jason.jin@freescale.com>
 *
-*               Copyright (C) 1991-2004 SciTech Software, Inc.
-*                    Copyright (C) David Mosberger-Tang
-*                      Copyright (C) 1999 Egbert Eich
+*              Copyright (C) 1991-2004 SciTech Software, Inc.
+*                   Copyright (C) David Mosberger-Tang
+*                     Copyright (C) 1999 Egbert Eich
 *
 *  ========================================================================
 *
@@ -17,7 +17,7 @@
 *  both that copyright notice and this permission notice appear in
 *  supporting documentation, and that the name of the authors not be used
 *  in advertising or publicity pertaining to distribution of the software
-*  without specific, written prior permission.  The authors makes no
+*  without specific, written prior permission. The authors makes no
 *  representations about the suitability of this software for any purpose.
 *  It is provided "as is" without express or implied warranty.
 *
 *
 *  ========================================================================
 *
-* Language:     ANSI C
-* Environment:  Any
-* Developer:    Kendall Bennett
+* Language:    ANSI C
+* Environment: Any
+* Developer:   Kendall Bennett
 *
-* Description:  This file includes subroutines to implement the decoding
-*               and emulation of all the x86 extended two-byte processor
-*               instructions.
+* Description: This file includes subroutines to implement the decoding
+*              and emulation of all the x86 extended two-byte processor
+*              instructions.
 *
-*               Jason port this file to u-boot. Put the function pointer into
-*               got2 sector.
+*              Jason port this file to u-boot. Put the function pointer into
+*              got2 sector.
 *
 ****************************************************************************/
 
@@ -62,7 +62,7 @@ void x86emuOp2_illegal_op(
     DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
     TRACE_REGS();
     printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n",
-        M.x86.R_CS, M.x86.R_IP-2,op2);
+       M.x86.R_CS, M.x86.R_IP-2,op2);
     HALT_SYS();
     END_OF_INSTR();
 }
@@ -77,69 +77,69 @@ int x86emu_check_jump_condition(u8 op)
 {
     switch (op) {
       case 0x0:
-        DECODE_PRINTF("JO\t");
-        return ACCESS_FLAG(F_OF);
+       DECODE_PRINTF("JO\t");
+       return ACCESS_FLAG(F_OF);
       case 0x1:
-        DECODE_PRINTF("JNO\t");
-        return !ACCESS_FLAG(F_OF);
-        break;
+       DECODE_PRINTF("JNO\t");
+       return !ACCESS_FLAG(F_OF);
+       break;
       case 0x2:
-        DECODE_PRINTF("JB\t");
-        return ACCESS_FLAG(F_CF);
-        break;
+       DECODE_PRINTF("JB\t");
+       return ACCESS_FLAG(F_CF);
+       break;
       case 0x3:
-        DECODE_PRINTF("JNB\t");
-        return !ACCESS_FLAG(F_CF);
-        break;
+       DECODE_PRINTF("JNB\t");
+       return !ACCESS_FLAG(F_CF);
+       break;
       case 0x4:
-        DECODE_PRINTF("JZ\t");
-        return ACCESS_FLAG(F_ZF);
-        break;
+       DECODE_PRINTF("JZ\t");
+       return ACCESS_FLAG(F_ZF);
+       break;
       case 0x5:
-        DECODE_PRINTF("JNZ\t");
-        return !ACCESS_FLAG(F_ZF);
-        break;
+       DECODE_PRINTF("JNZ\t");
+       return !ACCESS_FLAG(F_ZF);
+       break;
       case 0x6:
-        DECODE_PRINTF("JBE\t");
-        return ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF);
-        break;
+       DECODE_PRINTF("JBE\t");
+       return ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF);
+       break;
       case 0x7:
-        DECODE_PRINTF("JNBE\t");
-        return !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF));
-        break;
+       DECODE_PRINTF("JNBE\t");
+       return !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF));
+       break;
       case 0x8:
-        DECODE_PRINTF("JS\t");
-        return ACCESS_FLAG(F_SF);
-        break;
+       DECODE_PRINTF("JS\t");
+       return ACCESS_FLAG(F_SF);
+       break;
       case 0x9:
-        DECODE_PRINTF("JNS\t");
-        return !ACCESS_FLAG(F_SF);
-        break;
+       DECODE_PRINTF("JNS\t");
+       return !ACCESS_FLAG(F_SF);
+       break;
       case 0xa:
-        DECODE_PRINTF("JP\t");
-        return ACCESS_FLAG(F_PF);
-        break;
+       DECODE_PRINTF("JP\t");
+       return ACCESS_FLAG(F_PF);
+       break;
       case 0xb:
-        DECODE_PRINTF("JNP\t");
-        return !ACCESS_FLAG(F_PF);
-        break;
+       DECODE_PRINTF("JNP\t");
+       return !ACCESS_FLAG(F_PF);
+       break;
       case 0xc:
-        DECODE_PRINTF("JL\t");
-        return xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
-        break;
+       DECODE_PRINTF("JL\t");
+       return xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
+       break;
       case 0xd:
-        DECODE_PRINTF("JNL\t");
-        return !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
-        break;
+       DECODE_PRINTF("JNL\t");
+       return !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
+       break;
       case 0xe:
-        DECODE_PRINTF("JLE\t");
-        return (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
-                ACCESS_FLAG(F_ZF));
-        break;
+       DECODE_PRINTF("JLE\t");
+       return (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
+               ACCESS_FLAG(F_ZF));
+       break;
       default:
-        DECODE_PRINTF("JNLE\t");
-        return !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
-                 ACCESS_FLAG(F_ZF));
+       DECODE_PRINTF("JNLE\t");
+       return !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
+                ACCESS_FLAG(F_ZF));
     }
 }
 
@@ -156,7 +156,7 @@ void x86emuOp2_long_jump(u8 op2)
     DECODE_PRINTF2("%04x\n", target);
     TRACE_AND_STEP();
     if (cond)
-        M.x86.R_IP = (u16)target;
+       M.x86.R_IP = (u16)target;
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
 }
@@ -169,89 +169,89 @@ void x86emuOp2_set_byte(u8 op2)
 {
     int mod, rl, rh;
     uint destoffset;
-    u8  *destreg;
+    u8 *destreg;
     char *name = 0;
     int cond = 0;
 
     START_OF_INSTR();
     switch (op2) {
       case 0x90:
-        name = "SETO\t";
-        cond =  ACCESS_FLAG(F_OF);
-        break;
+       name = "SETO\t";
+       cond =  ACCESS_FLAG(F_OF);
+       break;
       case 0x91:
-        name = "SETNO\t";
-        cond = !ACCESS_FLAG(F_OF);
-        break;
+       name = "SETNO\t";
+       cond = !ACCESS_FLAG(F_OF);
+       break;
       case 0x92:
-        name = "SETB\t";
-        cond = ACCESS_FLAG(F_CF);
-        break;
+       name = "SETB\t";
+       cond = ACCESS_FLAG(F_CF);
+       break;
       case 0x93:
-        name = "SETNB\t";
-        cond = !ACCESS_FLAG(F_CF);
-        break;
+       name = "SETNB\t";
+       cond = !ACCESS_FLAG(F_CF);
+       break;
       case 0x94:
-        name = "SETZ\t";
-        cond = ACCESS_FLAG(F_ZF);
-        break;
+       name = "SETZ\t";
+       cond = ACCESS_FLAG(F_ZF);
+       break;
       case 0x95:
-        name = "SETNZ\t";
-        cond = !ACCESS_FLAG(F_ZF);
-        break;
+       name = "SETNZ\t";
+       cond = !ACCESS_FLAG(F_ZF);
+       break;
       case 0x96:
-        name = "SETBE\t";
-        cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF);
-        break;
+       name = "SETBE\t";
+       cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF);
+       break;
       case 0x97:
-        name = "SETNBE\t";
-        cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF));
-        break;
+       name = "SETNBE\t";
+       cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF));
+       break;
       case 0x98:
-        name = "SETS\t";
-        cond = ACCESS_FLAG(F_SF);
-        break;
+       name = "SETS\t";
+       cond = ACCESS_FLAG(F_SF);
+       break;
       case 0x99:
-        name = "SETNS\t";
-        cond = !ACCESS_FLAG(F_SF);
-        break;
+       name = "SETNS\t";
+       cond = !ACCESS_FLAG(F_SF);
+       break;
       case 0x9a:
-        name = "SETP\t";
-        cond = ACCESS_FLAG(F_PF);
-        break;
+       name = "SETP\t";
+       cond = ACCESS_FLAG(F_PF);
+       break;
       case 0x9b:
-        name = "SETNP\t";
-        cond = !ACCESS_FLAG(F_PF);
-        break;
+       name = "SETNP\t";
+       cond = !ACCESS_FLAG(F_PF);
+       break;
       case 0x9c:
-        name = "SETL\t";
-        cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
-        break;
+       name = "SETL\t";
+       cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
+       break;
       case 0x9d:
-        name = "SETNL\t";
-        cond = !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
-        break;
+       name = "SETNL\t";
+       cond = !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
+       break;
       case 0x9e:
-        name = "SETLE\t";
-        cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
-                ACCESS_FLAG(F_ZF));
-        break;
+       name = "SETLE\t";
+       cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
+               ACCESS_FLAG(F_ZF));
+       break;
       case 0x9f:
-        name = "SETNLE\t";
-        cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
-                 ACCESS_FLAG(F_ZF));
-        break;
+       name = "SETNLE\t";
+       cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
+                ACCESS_FLAG(F_ZF));
+       break;
     }
     DECODE_PRINTF(name);
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        destoffset = decode_rmXX_address(mod, rl);
-        TRACE_AND_STEP();
-        store_data_byte(destoffset, cond ? 0x01 : 0x00);
-    } else {                     /* register to register */
-        destreg = DECODE_RM_BYTE_REGISTER(rl);
-        TRACE_AND_STEP();
-        *destreg = cond ? 0x01 : 0x00;
+       destoffset = decode_rmXX_address(mod, rl);
+       TRACE_AND_STEP();
+       store_data_byte(destoffset, cond ? 0x01 : 0x00);
+    } else {                    /* register to register */
+       destreg = DECODE_RM_BYTE_REGISTER(rl);
+       TRACE_AND_STEP();
+       *destreg = cond ? 0x01 : 0x00;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -299,50 +299,50 @@ void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("BT\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        srcoffset = decode_rmXX_address(mod, rl);
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 srcval;
-            u32 *shiftreg;
-
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_LONG_REGISTER(rh);
-            TRACE_AND_STEP();
-            bit = *shiftreg & 0x1F;
-            disp = (s16)*shiftreg >> 5;
-            srcval = fetch_data_long(srcoffset+disp);
-            CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF);
-        } else {
-            u16 srcval;
-            u16 *shiftreg;
-
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_WORD_REGISTER(rh);
-            TRACE_AND_STEP();
-            bit = *shiftreg & 0xF;
-            disp = (s16)*shiftreg >> 4;
-            srcval = fetch_data_word(srcoffset+disp);
-            CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF);
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *srcreg,*shiftreg;
-
-            srcreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_LONG_REGISTER(rh);
-            TRACE_AND_STEP();
-            bit = *shiftreg & 0x1F;
-            CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF);
-        } else {
-            u16 *srcreg,*shiftreg;
-
-            srcreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_WORD_REGISTER(rh);
-            TRACE_AND_STEP();
-            bit = *shiftreg & 0xF;
-            CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF);
-        }
+       srcoffset = decode_rmXX_address(mod, rl);
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 srcval;
+           u32 *shiftreg;
+
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_LONG_REGISTER(rh);
+           TRACE_AND_STEP();
+           bit = *shiftreg & 0x1F;
+           disp = (s16)*shiftreg >> 5;
+           srcval = fetch_data_long(srcoffset+disp);
+           CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF);
+       } else {
+           u16 srcval;
+           u16 *shiftreg;
+
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_WORD_REGISTER(rh);
+           TRACE_AND_STEP();
+           bit = *shiftreg & 0xF;
+           disp = (s16)*shiftreg >> 4;
+           srcval = fetch_data_word(srcoffset+disp);
+           CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF);
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *srcreg,*shiftreg;
+
+           srcreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_LONG_REGISTER(rh);
+           TRACE_AND_STEP();
+           bit = *shiftreg & 0x1F;
+           CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF);
+       } else {
+           u16 *srcreg,*shiftreg;
+
+           srcreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_WORD_REGISTER(rh);
+           TRACE_AND_STEP();
+           bit = *shiftreg & 0xF;
+           CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF);
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -362,58 +362,58 @@ void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("SHLD\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        destoffset = decode_rmXX_address(mod, rl);
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 destval;
-            u32 *shiftreg;
-
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            shift = fetch_byte_imm();
-            DECODE_PRINTF2("%d\n", shift);
-            TRACE_AND_STEP();
-            destval = fetch_data_long(destoffset);
-            destval = shld_long(destval,*shiftreg,shift);
-            store_data_long(destoffset, destval);
-        } else {
-            u16 destval;
-            u16 *shiftreg;
-
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            shift = fetch_byte_imm();
-            DECODE_PRINTF2("%d\n", shift);
-            TRACE_AND_STEP();
-            destval = fetch_data_word(destoffset);
-            destval = shld_word(destval,*shiftreg,shift);
-            store_data_word(destoffset, destval);
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg,*shiftreg;
-
-            destreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            shift = fetch_byte_imm();
-            DECODE_PRINTF2("%d\n", shift);
-            TRACE_AND_STEP();
-            *destreg = shld_long(*destreg,*shiftreg,shift);
-        } else {
-            u16 *destreg,*shiftreg;
-
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            shift = fetch_byte_imm();
-            DECODE_PRINTF2("%d\n", shift);
-            TRACE_AND_STEP();
-            *destreg = shld_word(*destreg,*shiftreg,shift);
-        }
+       destoffset = decode_rmXX_address(mod, rl);
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 destval;
+           u32 *shiftreg;
+
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           shift = fetch_byte_imm();
+           DECODE_PRINTF2("%d\n", shift);
+           TRACE_AND_STEP();
+           destval = fetch_data_long(destoffset);
+           destval = shld_long(destval,*shiftreg,shift);
+           store_data_long(destoffset, destval);
+       } else {
+           u16 destval;
+           u16 *shiftreg;
+
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           shift = fetch_byte_imm();
+           DECODE_PRINTF2("%d\n", shift);
+           TRACE_AND_STEP();
+           destval = fetch_data_word(destoffset);
+           destval = shld_word(destval,*shiftreg,shift);
+           store_data_word(destoffset, destval);
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg,*shiftreg;
+
+           destreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           shift = fetch_byte_imm();
+           DECODE_PRINTF2("%d\n", shift);
+           TRACE_AND_STEP();
+           *destreg = shld_long(*destreg,*shiftreg,shift);
+       } else {
+           u16 *destreg,*shiftreg;
+
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           shift = fetch_byte_imm();
+           DECODE_PRINTF2("%d\n", shift);
+           TRACE_AND_STEP();
+           *destreg = shld_word(*destreg,*shiftreg,shift);
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -432,50 +432,50 @@ void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("SHLD\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        destoffset = decode_rmXX_address(mod, rl);
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 destval;
-            u32 *shiftreg;
-
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",CL\n");
-            TRACE_AND_STEP();
-            destval = fetch_data_long(destoffset);
-            destval = shld_long(destval,*shiftreg,M.x86.R_CL);
-            store_data_long(destoffset, destval);
-        } else {
-            u16 destval;
-            u16 *shiftreg;
-
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",CL\n");
-            TRACE_AND_STEP();
-            destval = fetch_data_word(destoffset);
-            destval = shld_word(destval,*shiftreg,M.x86.R_CL);
-            store_data_word(destoffset, destval);
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg,*shiftreg;
-
-            destreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",CL\n");
-            TRACE_AND_STEP();
-            *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL);
-        } else {
-            u16 *destreg,*shiftreg;
-
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",CL\n");
-            TRACE_AND_STEP();
-            *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL);
-        }
+       destoffset = decode_rmXX_address(mod, rl);
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 destval;
+           u32 *shiftreg;
+
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",CL\n");
+           TRACE_AND_STEP();
+           destval = fetch_data_long(destoffset);
+           destval = shld_long(destval,*shiftreg,M.x86.R_CL);
+           store_data_long(destoffset, destval);
+       } else {
+           u16 destval;
+           u16 *shiftreg;
+
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",CL\n");
+           TRACE_AND_STEP();
+           destval = fetch_data_word(destoffset);
+           destval = shld_word(destval,*shiftreg,M.x86.R_CL);
+           store_data_word(destoffset, destval);
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg,*shiftreg;
+
+           destreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",CL\n");
+           TRACE_AND_STEP();
+           *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL);
+       } else {
+           u16 *destreg,*shiftreg;
+
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",CL\n");
+           TRACE_AND_STEP();
+           *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL);
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -523,60 +523,60 @@ void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("BTS\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        srcoffset = decode_rmXX_address(mod, rl);
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 srcval,mask;
-            u32 *shiftreg;
-
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_LONG_REGISTER(rh);
-            TRACE_AND_STEP();
-            bit = *shiftreg & 0x1F;
-            disp = (s16)*shiftreg >> 5;
-            srcval = fetch_data_long(srcoffset+disp);
-            mask = (0x1 << bit);
-            CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
-            store_data_long(srcoffset+disp, srcval | mask);
-        } else {
-            u16 srcval,mask;
-            u16 *shiftreg;
-
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_WORD_REGISTER(rh);
-            TRACE_AND_STEP();
-            bit = *shiftreg & 0xF;
-            disp = (s16)*shiftreg >> 4;
-            srcval = fetch_data_word(srcoffset+disp);
-            mask = (u16)(0x1 << bit);
-            CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
-            store_data_word(srcoffset+disp, srcval | mask);
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *srcreg,*shiftreg;
-            u32 mask;
-
-            srcreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_LONG_REGISTER(rh);
-            TRACE_AND_STEP();
-            bit = *shiftreg & 0x1F;
-            mask = (0x1 << bit);
-            CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
-            *srcreg |= mask;
-        } else {
-            u16 *srcreg,*shiftreg;
-            u16 mask;
-
-            srcreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_WORD_REGISTER(rh);
-            TRACE_AND_STEP();
-            bit = *shiftreg & 0xF;
-            mask = (u16)(0x1 << bit);
-            CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
-            *srcreg |= mask;
-        }
+       srcoffset = decode_rmXX_address(mod, rl);
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 srcval,mask;
+           u32 *shiftreg;
+
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_LONG_REGISTER(rh);
+           TRACE_AND_STEP();
+           bit = *shiftreg & 0x1F;
+           disp = (s16)*shiftreg >> 5;
+           srcval = fetch_data_long(srcoffset+disp);
+           mask = (0x1 << bit);
+           CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+           store_data_long(srcoffset+disp, srcval | mask);
+       } else {
+           u16 srcval,mask;
+           u16 *shiftreg;
+
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_WORD_REGISTER(rh);
+           TRACE_AND_STEP();
+           bit = *shiftreg & 0xF;
+           disp = (s16)*shiftreg >> 4;
+           srcval = fetch_data_word(srcoffset+disp);
+           mask = (u16)(0x1 << bit);
+           CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+           store_data_word(srcoffset+disp, srcval | mask);
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *srcreg,*shiftreg;
+           u32 mask;
+
+           srcreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_LONG_REGISTER(rh);
+           TRACE_AND_STEP();
+           bit = *shiftreg & 0x1F;
+           mask = (0x1 << bit);
+           CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
+           *srcreg |= mask;
+       } else {
+           u16 *srcreg,*shiftreg;
+           u16 mask;
+
+           srcreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_WORD_REGISTER(rh);
+           TRACE_AND_STEP();
+           bit = *shiftreg & 0xF;
+           mask = (u16)(0x1 << bit);
+           CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
+           *srcreg |= mask;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -596,58 +596,58 @@ void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("SHLD\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        destoffset = decode_rmXX_address(mod, rl);
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 destval;
-            u32 *shiftreg;
-
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            shift = fetch_byte_imm();
-            DECODE_PRINTF2("%d\n", shift);
-            TRACE_AND_STEP();
-            destval = fetch_data_long(destoffset);
-            destval = shrd_long(destval,*shiftreg,shift);
-            store_data_long(destoffset, destval);
-        } else {
-            u16 destval;
-            u16 *shiftreg;
-
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            shift = fetch_byte_imm();
-            DECODE_PRINTF2("%d\n", shift);
-            TRACE_AND_STEP();
-            destval = fetch_data_word(destoffset);
-            destval = shrd_word(destval,*shiftreg,shift);
-            store_data_word(destoffset, destval);
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg,*shiftreg;
-
-            destreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            shift = fetch_byte_imm();
-            DECODE_PRINTF2("%d\n", shift);
-            TRACE_AND_STEP();
-            *destreg = shrd_long(*destreg,*shiftreg,shift);
-        } else {
-            u16 *destreg,*shiftreg;
-
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            shift = fetch_byte_imm();
-            DECODE_PRINTF2("%d\n", shift);
-            TRACE_AND_STEP();
-            *destreg = shrd_word(*destreg,*shiftreg,shift);
-        }
+       destoffset = decode_rmXX_address(mod, rl);
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 destval;
+           u32 *shiftreg;
+
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           shift = fetch_byte_imm();
+           DECODE_PRINTF2("%d\n", shift);
+           TRACE_AND_STEP();
+           destval = fetch_data_long(destoffset);
+           destval = shrd_long(destval,*shiftreg,shift);
+           store_data_long(destoffset, destval);
+       } else {
+           u16 destval;
+           u16 *shiftreg;
+
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           shift = fetch_byte_imm();
+           DECODE_PRINTF2("%d\n", shift);
+           TRACE_AND_STEP();
+           destval = fetch_data_word(destoffset);
+           destval = shrd_word(destval,*shiftreg,shift);
+           store_data_word(destoffset, destval);
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg,*shiftreg;
+
+           destreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           shift = fetch_byte_imm();
+           DECODE_PRINTF2("%d\n", shift);
+           TRACE_AND_STEP();
+           *destreg = shrd_long(*destreg,*shiftreg,shift);
+       } else {
+           u16 *destreg,*shiftreg;
+
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           shift = fetch_byte_imm();
+           DECODE_PRINTF2("%d\n", shift);
+           TRACE_AND_STEP();
+           *destreg = shrd_word(*destreg,*shiftreg,shift);
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -666,49 +666,49 @@ void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("SHLD\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        destoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF(",");
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 destval;
-            u32 *shiftreg;
-
-            shiftreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",CL\n");
-            TRACE_AND_STEP();
-            destval = fetch_data_long(destoffset);
-            destval = shrd_long(destval,*shiftreg,M.x86.R_CL);
-            store_data_long(destoffset, destval);
-        } else {
-            u16 destval;
-            u16 *shiftreg;
-
-            shiftreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",CL\n");
-            TRACE_AND_STEP();
-            destval = fetch_data_word(destoffset);
-            destval = shrd_word(destval,*shiftreg,M.x86.R_CL);
-            store_data_word(destoffset, destval);
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg,*shiftreg;
-
-            destreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",CL\n");
-            TRACE_AND_STEP();
-            *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL);
-        } else {
-            u16 *destreg,*shiftreg;
-
-            destreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",CL\n");
-            TRACE_AND_STEP();
-            *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL);
-        }
+       destoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF(",");
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 destval;
+           u32 *shiftreg;
+
+           shiftreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",CL\n");
+           TRACE_AND_STEP();
+           destval = fetch_data_long(destoffset);
+           destval = shrd_long(destval,*shiftreg,M.x86.R_CL);
+           store_data_long(destoffset, destval);
+       } else {
+           u16 destval;
+           u16 *shiftreg;
+
+           shiftreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",CL\n");
+           TRACE_AND_STEP();
+           destval = fetch_data_word(destoffset);
+           destval = shrd_word(destval,*shiftreg,M.x86.R_CL);
+           store_data_word(destoffset, destval);
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg,*shiftreg;
+
+           destreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",CL\n");
+           TRACE_AND_STEP();
+           *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL);
+       } else {
+           u16 *destreg,*shiftreg;
+
+           destreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",CL\n");
+           TRACE_AND_STEP();
+           *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL);
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -727,80 +727,80 @@ void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("IMUL\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg;
-            u32 srcval;
-            u32 res_lo,res_hi;
-
-            destreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcoffset = decode_rmXX_address(mod, rl);
-            srcval = fetch_data_long(srcoffset);
-            TRACE_AND_STEP();
-            imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval);
-            if (res_hi != 0) {
-                SET_FLAG(F_CF);
-                SET_FLAG(F_OF);
-            } else {
-                CLEAR_FLAG(F_CF);
-                CLEAR_FLAG(F_OF);
-            }
-            *destreg = (u32)res_lo;
-        } else {
-            u16 *destreg;
-            u16 srcval;
-            u32 res;
-
-            destreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcoffset = decode_rmXX_address(mod, rl);
-            srcval = fetch_data_word(srcoffset);
-            TRACE_AND_STEP();
-            res = (s16)*destreg * (s16)srcval;
-            if (res > 0xFFFF) {
-                SET_FLAG(F_CF);
-                SET_FLAG(F_OF);
-            } else {
-                CLEAR_FLAG(F_CF);
-                CLEAR_FLAG(F_OF);
-            }
-            *destreg = (u16)res;
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg,*srcreg;
-            u32 res_lo,res_hi;
-
-            destreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_LONG_REGISTER(rl);
-            TRACE_AND_STEP();
-            imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg);
-            if (res_hi != 0) {
-                SET_FLAG(F_CF);
-                SET_FLAG(F_OF);
-            } else {
-                CLEAR_FLAG(F_CF);
-                CLEAR_FLAG(F_OF);
-            }
-            *destreg = (u32)res_lo;
-        } else {
-            u16 *destreg,*srcreg;
-            u32 res;
-
-            destreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_WORD_REGISTER(rl);
-            res = (s16)*destreg * (s16)*srcreg;
-            if (res > 0xFFFF) {
-                SET_FLAG(F_CF);
-                SET_FLAG(F_OF);
-            } else {
-                CLEAR_FLAG(F_CF);
-                CLEAR_FLAG(F_OF);
-            }
-            *destreg = (u16)res;
-        }
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg;
+           u32 srcval;
+           u32 res_lo,res_hi;
+
+           destreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcoffset = decode_rmXX_address(mod, rl);
+           srcval = fetch_data_long(srcoffset);
+           TRACE_AND_STEP();
+           imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval);
+           if (res_hi != 0) {
+               SET_FLAG(F_CF);
+               SET_FLAG(F_OF);
+           } else {
+               CLEAR_FLAG(F_CF);
+               CLEAR_FLAG(F_OF);
+           }
+           *destreg = (u32)res_lo;
+       } else {
+           u16 *destreg;
+           u16 srcval;
+           u32 res;
+
+           destreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcoffset = decode_rmXX_address(mod, rl);
+           srcval = fetch_data_word(srcoffset);
+           TRACE_AND_STEP();
+           res = (s16)*destreg * (s16)srcval;
+           if (res > 0xFFFF) {
+               SET_FLAG(F_CF);
+               SET_FLAG(F_OF);
+           } else {
+               CLEAR_FLAG(F_CF);
+               CLEAR_FLAG(F_OF);
+           }
+           *destreg = (u16)res;
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg,*srcreg;
+           u32 res_lo,res_hi;
+
+           destreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_LONG_REGISTER(rl);
+           TRACE_AND_STEP();
+           imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg);
+           if (res_hi != 0) {
+               SET_FLAG(F_CF);
+               SET_FLAG(F_OF);
+           } else {
+               CLEAR_FLAG(F_CF);
+               CLEAR_FLAG(F_OF);
+           }
+           *destreg = (u32)res_lo;
+       } else {
+           u16 *destreg,*srcreg;
+           u32 res;
+
+           destreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_WORD_REGISTER(rl);
+           res = (s16)*destreg * (s16)*srcreg;
+           if (res > 0xFFFF) {
+               SET_FLAG(F_CF);
+               SET_FLAG(F_OF);
+           } else {
+               CLEAR_FLAG(F_CF);
+               CLEAR_FLAG(F_OF);
+           }
+           *destreg = (u16)res;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -820,16 +820,16 @@ void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("LSS\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        dstreg = DECODE_RM_WORD_REGISTER(rh);
-        DECODE_PRINTF(",");
-        srcoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *dstreg = fetch_data_word(srcoffset);
-        M.x86.R_SS = fetch_data_word(srcoffset + 2);
-    } else {                     /* register to register */
-        /* UNDEFINED! */
-        TRACE_AND_STEP();
+       dstreg = DECODE_RM_WORD_REGISTER(rh);
+       DECODE_PRINTF(",");
+       srcoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *dstreg = fetch_data_word(srcoffset);
+       M.x86.R_SS = fetch_data_word(srcoffset + 2);
+    } else {                    /* register to register */
+       /* UNDEFINED! */
+       TRACE_AND_STEP();
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -849,59 +849,59 @@ void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("BTR\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        srcoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF(",");
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 srcval,mask;
-            u32 *shiftreg;
-
-            shiftreg = DECODE_RM_LONG_REGISTER(rh);
-            TRACE_AND_STEP();
-            bit = *shiftreg & 0x1F;
-            disp = (s16)*shiftreg >> 5;
-            srcval = fetch_data_long(srcoffset+disp);
-            mask = (0x1 << bit);
-            CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
-            store_data_long(srcoffset+disp, srcval & ~mask);
-        } else {
-            u16 srcval,mask;
-            u16 *shiftreg;
-
-            shiftreg = DECODE_RM_WORD_REGISTER(rh);
-            TRACE_AND_STEP();
-            bit = *shiftreg & 0xF;
-            disp = (s16)*shiftreg >> 4;
-            srcval = fetch_data_word(srcoffset+disp);
-            mask = (u16)(0x1 << bit);
-            CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
-            store_data_word(srcoffset+disp, (u16)(srcval & ~mask));
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *srcreg,*shiftreg;
-            u32 mask;
-
-            srcreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_LONG_REGISTER(rh);
-            TRACE_AND_STEP();
-            bit = *shiftreg & 0x1F;
-            mask = (0x1 << bit);
-            CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
-            *srcreg &= ~mask;
-        } else {
-            u16 *srcreg,*shiftreg;
-            u16 mask;
-
-            srcreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_WORD_REGISTER(rh);
-            TRACE_AND_STEP();
-            bit = *shiftreg & 0xF;
-            mask = (u16)(0x1 << bit);
-            CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
-            *srcreg &= ~mask;
-        }
+       srcoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF(",");
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 srcval,mask;
+           u32 *shiftreg;
+
+           shiftreg = DECODE_RM_LONG_REGISTER(rh);
+           TRACE_AND_STEP();
+           bit = *shiftreg & 0x1F;
+           disp = (s16)*shiftreg >> 5;
+           srcval = fetch_data_long(srcoffset+disp);
+           mask = (0x1 << bit);
+           CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+           store_data_long(srcoffset+disp, srcval & ~mask);
+       } else {
+           u16 srcval,mask;
+           u16 *shiftreg;
+
+           shiftreg = DECODE_RM_WORD_REGISTER(rh);
+           TRACE_AND_STEP();
+           bit = *shiftreg & 0xF;
+           disp = (s16)*shiftreg >> 4;
+           srcval = fetch_data_word(srcoffset+disp);
+           mask = (u16)(0x1 << bit);
+           CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+           store_data_word(srcoffset+disp, (u16)(srcval & ~mask));
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *srcreg,*shiftreg;
+           u32 mask;
+
+           srcreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_LONG_REGISTER(rh);
+           TRACE_AND_STEP();
+           bit = *shiftreg & 0x1F;
+           mask = (0x1 << bit);
+           CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
+           *srcreg &= ~mask;
+       } else {
+           u16 *srcreg,*shiftreg;
+           u16 mask;
+
+           srcreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_WORD_REGISTER(rh);
+           TRACE_AND_STEP();
+           bit = *shiftreg & 0xF;
+           mask = (u16)(0x1 << bit);
+           CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
+           *srcreg &= ~mask;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -921,16 +921,16 @@ void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("LFS\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        dstreg = DECODE_RM_WORD_REGISTER(rh);
-        DECODE_PRINTF(",");
-        srcoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *dstreg = fetch_data_word(srcoffset);
-        M.x86.R_FS = fetch_data_word(srcoffset + 2);
-    } else {                     /* register to register */
-        /* UNDEFINED! */
-        TRACE_AND_STEP();
+       dstreg = DECODE_RM_WORD_REGISTER(rh);
+       DECODE_PRINTF(",");
+       srcoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *dstreg = fetch_data_word(srcoffset);
+       M.x86.R_FS = fetch_data_word(srcoffset + 2);
+    } else {                    /* register to register */
+       /* UNDEFINED! */
+       TRACE_AND_STEP();
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -950,16 +950,16 @@ void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("LGS\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        dstreg = DECODE_RM_WORD_REGISTER(rh);
-        DECODE_PRINTF(",");
-        srcoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *dstreg = fetch_data_word(srcoffset);
-        M.x86.R_GS = fetch_data_word(srcoffset + 2);
-    } else {                     /* register to register */
-        /* UNDEFINED! */
-        TRACE_AND_STEP();
+       dstreg = DECODE_RM_WORD_REGISTER(rh);
+       DECODE_PRINTF(",");
+       srcoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *dstreg = fetch_data_word(srcoffset);
+       M.x86.R_GS = fetch_data_word(srcoffset + 2);
+    } else {                    /* register to register */
+       /* UNDEFINED! */
+       TRACE_AND_STEP();
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -978,51 +978,51 @@ void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("MOVZX\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg;
-            u32 srcval;
-
-            destreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcoffset = decode_rmXX_address(mod, rl);
-            srcval = fetch_data_byte(srcoffset);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = srcval;
-        } else {
-            u16 *destreg;
-            u16 srcval;
-
-            destreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcoffset = decode_rmXX_address(mod, rl);
-            srcval = fetch_data_byte(srcoffset);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = srcval;
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg;
-            u8  *srcreg;
-
-            destreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_BYTE_REGISTER(rl);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = *srcreg;
-        } else {
-            u16 *destreg;
-            u8  *srcreg;
-
-            destreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_BYTE_REGISTER(rl);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = *srcreg;
-        }
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg;
+           u32 srcval;
+
+           destreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcoffset = decode_rmXX_address(mod, rl);
+           srcval = fetch_data_byte(srcoffset);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = srcval;
+       } else {
+           u16 *destreg;
+           u16 srcval;
+
+           destreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcoffset = decode_rmXX_address(mod, rl);
+           srcval = fetch_data_byte(srcoffset);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = srcval;
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg;
+           u8  *srcreg;
+
+           destreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_BYTE_REGISTER(rl);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = *srcreg;
+       } else {
+           u16 *destreg;
+           u8  *srcreg;
+
+           destreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_BYTE_REGISTER(rl);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = *srcreg;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1044,20 +1044,20 @@ void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("MOVZX\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        destreg = DECODE_RM_LONG_REGISTER(rh);
-        DECODE_PRINTF(",");
-        srcoffset = decode_rmXX_address(mod, rl);
-        srcval = fetch_data_word(srcoffset);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *destreg = srcval;
-    } else {                     /* register to register */
-        destreg = DECODE_RM_LONG_REGISTER(rh);
-        DECODE_PRINTF(",");
-        srcreg = DECODE_RM_WORD_REGISTER(rl);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *destreg = *srcreg;
+       destreg = DECODE_RM_LONG_REGISTER(rh);
+       DECODE_PRINTF(",");
+       srcoffset = decode_rmXX_address(mod, rl);
+       srcval = fetch_data_word(srcoffset);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *destreg = srcval;
+    } else {                    /* register to register */
+       destreg = DECODE_RM_LONG_REGISTER(rh);
+       DECODE_PRINTF(",");
+       srcreg = DECODE_RM_WORD_REGISTER(rl);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *destreg = *srcreg;
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1078,122 +1078,122 @@ void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2))
     FETCH_DECODE_MODRM(mod, rh, rl);
     switch (rh) {
     case 4:
-        DECODE_PRINTF("BT\t");
-        break;
+       DECODE_PRINTF("BT\t");
+       break;
     case 5:
-        DECODE_PRINTF("BTS\t");
-        break;
+       DECODE_PRINTF("BTS\t");
+       break;
     case 6:
-        DECODE_PRINTF("BTR\t");
-        break;
+       DECODE_PRINTF("BTR\t");
+       break;
     case 7:
-        DECODE_PRINTF("BTC\t");
-        break;
+       DECODE_PRINTF("BTC\t");
+       break;
     default:
-        DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
-        TRACE_REGS();
-        printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n",
-                M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl);
-        HALT_SYS();
+       DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
+       TRACE_REGS();
+       printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n",
+               M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl);
+       HALT_SYS();
     }
     if (mod < 3) {
 
-        srcoffset = decode_rmXX_address(mod, rl);
-        shift = fetch_byte_imm();
-        DECODE_PRINTF2(",%d\n", shift);
-        TRACE_AND_STEP();
-
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 srcval, mask;
-
-            bit = shift & 0x1F;
-            srcval = fetch_data_long(srcoffset);
-            mask = (0x1 << bit);
-            CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
-            switch (rh) {
-            case 5:
-                store_data_long(srcoffset, srcval | mask);
-                break;
-            case 6:
-                store_data_long(srcoffset, srcval & ~mask);
-                break;
-            case 7:
-                store_data_long(srcoffset, srcval ^ mask);
-                break;
-            default:
-                break;
-            }
-        } else {
-            u16 srcval, mask;
-
-            bit = shift & 0xF;
-            srcval = fetch_data_word(srcoffset);
-            mask = (0x1 << bit);
-            CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
-            switch (rh) {
-            case 5:
-                store_data_word(srcoffset, srcval | mask);
-                break;
-            case 6:
-                store_data_word(srcoffset, srcval & ~mask);
-                break;
-            case 7:
-                store_data_word(srcoffset, srcval ^ mask);
-                break;
-            default:
-                break;
-            }
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *srcreg;
-            u32 mask;
-
-            srcreg = DECODE_RM_LONG_REGISTER(rl);
-            shift = fetch_byte_imm();
-            DECODE_PRINTF2(",%d\n", shift);
-            TRACE_AND_STEP();
-            bit = shift & 0x1F;
-            mask = (0x1 << bit);
-            CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
-            switch (rh) {
-            case 5:
-                *srcreg |= mask;
-                break;
-            case 6:
-                *srcreg &= ~mask;
-                break;
-            case 7:
-                *srcreg ^= mask;
-                break;
-            default:
-                break;
-            }
-        } else {
-            u16 *srcreg;
-            u16 mask;
-
-            srcreg = DECODE_RM_WORD_REGISTER(rl);
-            shift = fetch_byte_imm();
-            DECODE_PRINTF2(",%d\n", shift);
-            TRACE_AND_STEP();
-            bit = shift & 0xF;
-            mask = (0x1 << bit);
-            CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
-            switch (rh) {
-            case 5:
-                *srcreg |= mask;
-                break;
-            case 6:
-                *srcreg &= ~mask;
-                break;
-            case 7:
-                *srcreg ^= mask;
-                break;
-            default:
-                break;
-            }
-        }
+       srcoffset = decode_rmXX_address(mod, rl);
+       shift = fetch_byte_imm();
+       DECODE_PRINTF2(",%d\n", shift);
+       TRACE_AND_STEP();
+
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 srcval, mask;
+
+           bit = shift & 0x1F;
+           srcval = fetch_data_long(srcoffset);
+           mask = (0x1 << bit);
+           CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+           switch (rh) {
+           case 5:
+               store_data_long(srcoffset, srcval | mask);
+               break;
+           case 6:
+               store_data_long(srcoffset, srcval & ~mask);
+               break;
+           case 7:
+               store_data_long(srcoffset, srcval ^ mask);
+               break;
+           default:
+               break;
+           }
+       } else {
+           u16 srcval, mask;
+
+           bit = shift & 0xF;
+           srcval = fetch_data_word(srcoffset);
+           mask = (0x1 << bit);
+           CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+           switch (rh) {
+           case 5:
+               store_data_word(srcoffset, srcval | mask);
+               break;
+           case 6:
+               store_data_word(srcoffset, srcval & ~mask);
+               break;
+           case 7:
+               store_data_word(srcoffset, srcval ^ mask);
+               break;
+           default:
+               break;
+           }
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *srcreg;
+           u32 mask;
+
+           srcreg = DECODE_RM_LONG_REGISTER(rl);
+           shift = fetch_byte_imm();
+           DECODE_PRINTF2(",%d\n", shift);
+           TRACE_AND_STEP();
+           bit = shift & 0x1F;
+           mask = (0x1 << bit);
+           CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
+           switch (rh) {
+           case 5:
+               *srcreg |= mask;
+               break;
+           case 6:
+               *srcreg &= ~mask;
+               break;
+           case 7:
+               *srcreg ^= mask;
+               break;
+           default:
+               break;
+           }
+       } else {
+           u16 *srcreg;
+           u16 mask;
+
+           srcreg = DECODE_RM_WORD_REGISTER(rl);
+           shift = fetch_byte_imm();
+           DECODE_PRINTF2(",%d\n", shift);
+           TRACE_AND_STEP();
+           bit = shift & 0xF;
+           mask = (0x1 << bit);
+           CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
+           switch (rh) {
+           case 5:
+               *srcreg |= mask;
+               break;
+           case 6:
+               *srcreg &= ~mask;
+               break;
+           case 7:
+               *srcreg ^= mask;
+               break;
+           default:
+               break;
+           }
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1213,59 +1213,59 @@ void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("BTC\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        srcoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF(",");
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 srcval,mask;
-            u32 *shiftreg;
-
-            shiftreg = DECODE_RM_LONG_REGISTER(rh);
-            TRACE_AND_STEP();
-            bit = *shiftreg & 0x1F;
-            disp = (s16)*shiftreg >> 5;
-            srcval = fetch_data_long(srcoffset+disp);
-            mask = (0x1 << bit);
-            CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
-            store_data_long(srcoffset+disp, srcval ^ mask);
-        } else {
-            u16 srcval,mask;
-            u16 *shiftreg;
-
-            shiftreg = DECODE_RM_WORD_REGISTER(rh);
-            TRACE_AND_STEP();
-            bit = *shiftreg & 0xF;
-            disp = (s16)*shiftreg >> 4;
-            srcval = fetch_data_word(srcoffset+disp);
-            mask = (u16)(0x1 << bit);
-            CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
-            store_data_word(srcoffset+disp, (u16)(srcval ^ mask));
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *srcreg,*shiftreg;
-            u32 mask;
-
-            srcreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_LONG_REGISTER(rh);
-            TRACE_AND_STEP();
-            bit = *shiftreg & 0x1F;
-            mask = (0x1 << bit);
-            CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
-            *srcreg ^= mask;
-        } else {
-            u16 *srcreg,*shiftreg;
-            u16 mask;
-
-            srcreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF(",");
-            shiftreg = DECODE_RM_WORD_REGISTER(rh);
-            TRACE_AND_STEP();
-            bit = *shiftreg & 0xF;
-            mask = (u16)(0x1 << bit);
-            CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
-            *srcreg ^= mask;
-        }
+       srcoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF(",");
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 srcval,mask;
+           u32 *shiftreg;
+
+           shiftreg = DECODE_RM_LONG_REGISTER(rh);
+           TRACE_AND_STEP();
+           bit = *shiftreg & 0x1F;
+           disp = (s16)*shiftreg >> 5;
+           srcval = fetch_data_long(srcoffset+disp);
+           mask = (0x1 << bit);
+           CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+           store_data_long(srcoffset+disp, srcval ^ mask);
+       } else {
+           u16 srcval,mask;
+           u16 *shiftreg;
+
+           shiftreg = DECODE_RM_WORD_REGISTER(rh);
+           TRACE_AND_STEP();
+           bit = *shiftreg & 0xF;
+           disp = (s16)*shiftreg >> 4;
+           srcval = fetch_data_word(srcoffset+disp);
+           mask = (u16)(0x1 << bit);
+           CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+           store_data_word(srcoffset+disp, (u16)(srcval ^ mask));
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *srcreg,*shiftreg;
+           u32 mask;
+
+           srcreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_LONG_REGISTER(rh);
+           TRACE_AND_STEP();
+           bit = *shiftreg & 0x1F;
+           mask = (0x1 << bit);
+           CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
+           *srcreg ^= mask;
+       } else {
+           u16 *srcreg,*shiftreg;
+           u16 mask;
+
+           srcreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF(",");
+           shiftreg = DECODE_RM_WORD_REGISTER(rh);
+           TRACE_AND_STEP();
+           bit = *shiftreg & 0xF;
+           mask = (u16)(0x1 << bit);
+           CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
+           *srcreg ^= mask;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1284,49 +1284,49 @@ void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("BSF\n");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        srcoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF(",");
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 srcval, *dstreg;
-
-            dstreg = DECODE_RM_LONG_REGISTER(rh);
-            TRACE_AND_STEP();
-            srcval = fetch_data_long(srcoffset);
-            CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
-            for(*dstreg = 0; *dstreg < 32; (*dstreg)++)
-                if ((srcval >> *dstreg) & 1) break;
-        } else {
-            u16 srcval, *dstreg;
-
-            dstreg = DECODE_RM_WORD_REGISTER(rh);
-            TRACE_AND_STEP();
-            srcval = fetch_data_word(srcoffset);
-            CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
-            for(*dstreg = 0; *dstreg < 16; (*dstreg)++)
-                if ((srcval >> *dstreg) & 1) break;
-        }
-    } else {             /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *srcreg, *dstreg;
-
-            srcreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF(",");
-            dstreg = DECODE_RM_LONG_REGISTER(rh);
-            TRACE_AND_STEP();
-            CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
-            for(*dstreg = 0; *dstreg < 32; (*dstreg)++)
-                if ((*srcreg >> *dstreg) & 1) break;
-        } else {
-            u16 *srcreg, *dstreg;
-
-            srcreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF(",");
-            dstreg = DECODE_RM_WORD_REGISTER(rh);
-            TRACE_AND_STEP();
-            CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
-            for(*dstreg = 0; *dstreg < 16; (*dstreg)++)
-                if ((*srcreg >> *dstreg) & 1) break;
-        }
+       srcoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF(",");
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 srcval, *dstreg;
+
+           dstreg = DECODE_RM_LONG_REGISTER(rh);
+           TRACE_AND_STEP();
+           srcval = fetch_data_long(srcoffset);
+           CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
+           for(*dstreg = 0; *dstreg < 32; (*dstreg)++)
+               if ((srcval >> *dstreg) & 1) break;
+       } else {
+           u16 srcval, *dstreg;
+
+           dstreg = DECODE_RM_WORD_REGISTER(rh);
+           TRACE_AND_STEP();
+           srcval = fetch_data_word(srcoffset);
+           CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
+           for(*dstreg = 0; *dstreg < 16; (*dstreg)++)
+               if ((srcval >> *dstreg) & 1) break;
+       }
+    } else {            /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *srcreg, *dstreg;
+
+           srcreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF(",");
+           dstreg = DECODE_RM_LONG_REGISTER(rh);
+           TRACE_AND_STEP();
+           CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
+           for(*dstreg = 0; *dstreg < 32; (*dstreg)++)
+               if ((*srcreg >> *dstreg) & 1) break;
+       } else {
+           u16 *srcreg, *dstreg;
+
+           srcreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF(",");
+           dstreg = DECODE_RM_WORD_REGISTER(rh);
+           TRACE_AND_STEP();
+           CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
+           for(*dstreg = 0; *dstreg < 16; (*dstreg)++)
+               if ((*srcreg >> *dstreg) & 1) break;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1345,49 +1345,49 @@ void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("BSF\n");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        srcoffset = decode_rmXX_address(mod, rl);
-        DECODE_PRINTF(",");
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 srcval, *dstreg;
-
-            dstreg = DECODE_RM_LONG_REGISTER(rh);
-            TRACE_AND_STEP();
-            srcval = fetch_data_long(srcoffset);
-            CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
-            for(*dstreg = 31; *dstreg > 0; (*dstreg)--)
-                if ((srcval >> *dstreg) & 1) break;
-        } else {
-            u16 srcval, *dstreg;
-
-            dstreg = DECODE_RM_WORD_REGISTER(rh);
-            TRACE_AND_STEP();
-            srcval = fetch_data_word(srcoffset);
-            CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
-            for(*dstreg = 15; *dstreg > 0; (*dstreg)--)
-                if ((srcval >> *dstreg) & 1) break;
-        }
-    } else {             /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *srcreg, *dstreg;
-
-            srcreg = DECODE_RM_LONG_REGISTER(rl);
-            DECODE_PRINTF(",");
-            dstreg = DECODE_RM_LONG_REGISTER(rh);
-            TRACE_AND_STEP();
-            CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
-            for(*dstreg = 31; *dstreg > 0; (*dstreg)--)
-                if ((*srcreg >> *dstreg) & 1) break;
-        } else {
-            u16 *srcreg, *dstreg;
-
-            srcreg = DECODE_RM_WORD_REGISTER(rl);
-            DECODE_PRINTF(",");
-            dstreg = DECODE_RM_WORD_REGISTER(rh);
-            TRACE_AND_STEP();
-            CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
-            for(*dstreg = 15; *dstreg > 0; (*dstreg)--)
-                if ((*srcreg >> *dstreg) & 1) break;
-        }
+       srcoffset = decode_rmXX_address(mod, rl);
+       DECODE_PRINTF(",");
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 srcval, *dstreg;
+
+           dstreg = DECODE_RM_LONG_REGISTER(rh);
+           TRACE_AND_STEP();
+           srcval = fetch_data_long(srcoffset);
+           CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
+           for(*dstreg = 31; *dstreg > 0; (*dstreg)--)
+               if ((srcval >> *dstreg) & 1) break;
+       } else {
+           u16 srcval, *dstreg;
+
+           dstreg = DECODE_RM_WORD_REGISTER(rh);
+           TRACE_AND_STEP();
+           srcval = fetch_data_word(srcoffset);
+           CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
+           for(*dstreg = 15; *dstreg > 0; (*dstreg)--)
+               if ((srcval >> *dstreg) & 1) break;
+       }
+    } else {            /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *srcreg, *dstreg;
+
+           srcreg = DECODE_RM_LONG_REGISTER(rl);
+           DECODE_PRINTF(",");
+           dstreg = DECODE_RM_LONG_REGISTER(rh);
+           TRACE_AND_STEP();
+           CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
+           for(*dstreg = 31; *dstreg > 0; (*dstreg)--)
+               if ((*srcreg >> *dstreg) & 1) break;
+       } else {
+           u16 *srcreg, *dstreg;
+
+           srcreg = DECODE_RM_WORD_REGISTER(rl);
+           DECODE_PRINTF(",");
+           dstreg = DECODE_RM_WORD_REGISTER(rh);
+           TRACE_AND_STEP();
+           CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
+           for(*dstreg = 15; *dstreg > 0; (*dstreg)--)
+               if ((*srcreg >> *dstreg) & 1) break;
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1406,51 +1406,51 @@ void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("MOVSX\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg;
-            u32 srcval;
-
-            destreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcoffset = decode_rmXX_address(mod, rl);
-            srcval = (s32)((s8)fetch_data_byte(srcoffset));
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = srcval;
-        } else {
-            u16 *destreg;
-            u16 srcval;
-
-            destreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcoffset = decode_rmXX_address(mod, rl);
-            srcval = (s16)((s8)fetch_data_byte(srcoffset));
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = srcval;
-        }
-    } else {                     /* register to register */
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            u32 *destreg;
-            u8  *srcreg;
-
-            destreg = DECODE_RM_LONG_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_BYTE_REGISTER(rl);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = (s32)((s8)*srcreg);
-        } else {
-            u16 *destreg;
-            u8  *srcreg;
-
-            destreg = DECODE_RM_WORD_REGISTER(rh);
-            DECODE_PRINTF(",");
-            srcreg = DECODE_RM_BYTE_REGISTER(rl);
-            DECODE_PRINTF("\n");
-            TRACE_AND_STEP();
-            *destreg = (s16)((s8)*srcreg);
-        }
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg;
+           u32 srcval;
+
+           destreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcoffset = decode_rmXX_address(mod, rl);
+           srcval = (s32)((s8)fetch_data_byte(srcoffset));
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = srcval;
+       } else {
+           u16 *destreg;
+           u16 srcval;
+
+           destreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcoffset = decode_rmXX_address(mod, rl);
+           srcval = (s16)((s8)fetch_data_byte(srcoffset));
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = srcval;
+       }
+    } else {                    /* register to register */
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           u32 *destreg;
+           u8  *srcreg;
+
+           destreg = DECODE_RM_LONG_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_BYTE_REGISTER(rl);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = (s32)((s8)*srcreg);
+       } else {
+           u16 *destreg;
+           u8  *srcreg;
+
+           destreg = DECODE_RM_WORD_REGISTER(rh);
+           DECODE_PRINTF(",");
+           srcreg = DECODE_RM_BYTE_REGISTER(rl);
+           DECODE_PRINTF("\n");
+           TRACE_AND_STEP();
+           *destreg = (s16)((s8)*srcreg);
+       }
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1472,20 +1472,20 @@ void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2))
     DECODE_PRINTF("MOVSX\t");
     FETCH_DECODE_MODRM(mod, rh, rl);
     if (mod < 3) {
-        destreg = DECODE_RM_LONG_REGISTER(rh);
-        DECODE_PRINTF(",");
-        srcoffset = decode_rmXX_address(mod, rl);
-        srcval = (s32)((s16)fetch_data_word(srcoffset));
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *destreg = srcval;
-    } else {                     /* register to register */
-        destreg = DECODE_RM_LONG_REGISTER(rh);
-        DECODE_PRINTF(",");
-        srcreg = DECODE_RM_WORD_REGISTER(rl);
-        DECODE_PRINTF("\n");
-        TRACE_AND_STEP();
-        *destreg = (s32)((s16)*srcreg);
+       destreg = DECODE_RM_LONG_REGISTER(rh);
+       DECODE_PRINTF(",");
+       srcoffset = decode_rmXX_address(mod, rl);
+       srcval = (s32)((s16)fetch_data_word(srcoffset));
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *destreg = srcval;
+    } else {                    /* register to register */
+       destreg = DECODE_RM_LONG_REGISTER(rh);
+       DECODE_PRINTF(",");
+       srcreg = DECODE_RM_WORD_REGISTER(rl);
+       DECODE_PRINTF("\n");
+       TRACE_AND_STEP();
+       *destreg = (s32)((s16)*srcreg);
     }
     DECODE_CLEAR_SEGOVR();
     END_OF_INSTR();
@@ -1498,13 +1498,13 @@ void (*x86emu_optab2[256])(u8) __attribute__((section(".got2"))) =
 {
 /*  0x00 */ x86emuOp2_illegal_op,  /* Group F (ring 0 PM)      */
 /*  0x01 */ x86emuOp2_illegal_op,  /* Group G (ring 0 PM)      */
-/*  0x02 */ x86emuOp2_illegal_op,  /* lar (ring 0 PM)          */
-/*  0x03 */ x86emuOp2_illegal_op,  /* lsl (ring 0 PM)          */
+/*  0x02 */ x86emuOp2_illegal_op,  /* lar (ring 0 PM)         */
+/*  0x03 */ x86emuOp2_illegal_op,  /* lsl (ring 0 PM)         */
 /*  0x04 */ x86emuOp2_illegal_op,
 /*  0x05 */ x86emuOp2_illegal_op,  /* loadall (undocumented)   */
-/*  0x06 */ x86emuOp2_illegal_op,  /* clts (ring 0 PM)         */
+/*  0x06 */ x86emuOp2_illegal_op,  /* clts (ring 0 PM)        */
 /*  0x07 */ x86emuOp2_illegal_op,  /* loadall (undocumented)   */
-/*  0x08 */ x86emuOp2_illegal_op,  /* invd (ring 0 PM)         */
+/*  0x08 */ x86emuOp2_illegal_op,  /* invd (ring 0 PM)        */
 /*  0x09 */ x86emuOp2_illegal_op,  /* wbinvd (ring 0 PM)       */
 /*  0x0a */ x86emuOp2_illegal_op,
 /*  0x0b */ x86emuOp2_illegal_op,
index dc8cea80039cfbc0c41638e1babf2b6d98638d57..e0827d7478263a784d633c0f527c109beb10ded0 100644 (file)
@@ -1,10 +1,10 @@
 /****************************************************************************
 *
-*                       Realmode X86 Emulator Library
+*                      Realmode X86 Emulator Library
 *
-*               Copyright (C) 1991-2004 SciTech Software, Inc.
-*                    Copyright (C) David Mosberger-Tang
-*                      Copyright (C) 1999 Egbert Eich
+*              Copyright (C) 1991-2004 SciTech Software, Inc.
+*                   Copyright (C) David Mosberger-Tang
+*                     Copyright (C) 1999 Egbert Eich
 *
 *  ========================================================================
 *
@@ -14,7 +14,7 @@
 *  both that copyright notice and this permission notice appear in
 *  supporting documentation, and that the name of the authors not be used
 *  in advertising or publicity pertaining to distribution of the software
-*  without specific, written prior permission.  The authors makes no
+*  without specific, written prior permission. The authors makes no
 *  representations about the suitability of this software for any purpose.
 *  It is provided "as is" without express or implied warranty.
 *
 *
 *  ========================================================================
 *
-* Language:     ANSI C
-* Environment:  Any
-* Developer:    Kendall Bennett
+* Language:    ANSI C
+* Environment: Any
+* Developer:   Kendall Bennett
 *
-* Description:  This file contains the code to implement the primitive
-*               machine operations used by the emulation code in ops.c
+* Description: This file contains the code to implement the primitive
+*              machine operations used by the emulation code in ops.c
 *
 * Carry Chain Calculation
 *
 * So, given the following table, which represents the addition of two
 * bits, we can derive a formula for the carry chain.
 *
-* a   b   cin   r     cout
-* 0   0   0     0     0
-* 0   0   1     1     0
-* 0   1   0     1     0
-* 0   1   1     0     1
-* 1   0   0     1     0
-* 1   0   1     0     1
-* 1   1   0     0     1
-* 1   1   1     1     1
+* a   b          cin   r     cout
+* 0   0          0     0     0
+* 0   0          1     1     0
+* 0   1          0     1     0
+* 0   1          1     0     1
+* 1   0          0     1     0
+* 1   0          1     0     1
+* 1   1          0     0     1
+* 1   1          1     1     1
 *
 * Construction of table for cout:
 *
 * ab
-* r  \  00   01   11  10
+* r  \ 00   01   11  10
 * |------------------
-* 0  |   0    1    1   1
-* 1  |   0    0    1   0
+* 0  |  0    1    1   1
+* 1  |  0    0    1   0
 *
 * By inspection, one gets:  cc = ab +  r'(a + b)
 *
 * The following table represents the subtraction of two bits, from
 * which we can derive a formula for the borrow chain.
 *
-* a   b   bin   r     bout
-* 0   0   0     0     0
-* 0   0   1     1     1
-* 0   1   0     1     1
-* 0   1   1     0     1
-* 1   0   0     1     0
-* 1   0   1     0     0
-* 1   1   0     0     0
-* 1   1   1     1     1
+* a   b          bin   r     bout
+* 0   0          0     0     0
+* 0   0          1     1     1
+* 0   1          0     1     1
+* 0   1          1     0     1
+* 1   0          0     1     0
+* 1   0          1     0     0
+* 1   1          0     0     0
+* 1   1          1     1     1
 *
 * Construction of table for cout:
 *
 * ab
-* r  \  00   01   11  10
+* r  \ 00   01   11  10
 * |------------------
-* 0  |   0    1    0   0
-* 1  |   1    1    1   0
+* 0  |  0    1    0   0
+* 1  |  1    1    1   0
 *
-* By inspection, one gets:  bc = a'b +  r(a' + b)
+* By inspection, one gets:  bc = a'b + r(a' + b)
 *
 ****************************************************************************/
 
@@ -115,7 +115,7 @@ static u32 x86emu_parity_tab[8] =
 };
 
 #define PARITY(x)   (((x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0)
-#define XOR2(x)     (((x) ^ ((x)>>1)) & 0x1)
+#define XOR2(x)            (((x) ^ ((x)>>1)) & 0x1)
 /*----------------------------- Implementation ----------------------------*/
 int abs(int v)
 {
@@ -190,7 +190,7 @@ static void calc_carry_chain(int bits, u32 d, u32 s, u32 res, int set_carry)
     CONDITIONAL_SET_FLAG(XOR2(cc >> (bits - 2)), F_OF);
     CONDITIONAL_SET_FLAG(cc & 0x8, F_AF);
     if (set_carry) {
-        CONDITIONAL_SET_FLAG(res & (1 << bits), F_CF);
+       CONDITIONAL_SET_FLAG(res & (1 << bits), F_CF);
     }
 }
 
@@ -202,7 +202,7 @@ static void calc_borrow_chain(int bits, u32 d, u32 s, u32 res, int set_carry)
     CONDITIONAL_SET_FLAG(XOR2(bc >> (bits - 2)), F_OF);
     CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
     if (set_carry) {
-        CONDITIONAL_SET_FLAG(bc & (1 << (bits - 1)), F_CF);
+       CONDITIONAL_SET_FLAG(bc & (1 << (bits - 1)), F_CF);
     }
 }
 
@@ -214,13 +214,13 @@ u16 aaa_word(u16 d)
 {
     u16 res;
     if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) {
-        d += 0x6;
-        d += 0x100;
-        SET_FLAG(F_AF);
-        SET_FLAG(F_CF);
+       d += 0x6;
+       d += 0x100;
+       SET_FLAG(F_AF);
+       SET_FLAG(F_CF);
     } else {
-        CLEAR_FLAG(F_CF);
-        CLEAR_FLAG(F_AF);
+       CLEAR_FLAG(F_CF);
+       CLEAR_FLAG(F_AF);
     }
     res = (u16)(d & 0xFF0F);
     set_szp_flags_16(res);
@@ -235,13 +235,13 @@ u16 aas_word(u16 d)
 {
     u16 res;
     if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) {
-        d -= 0x6;
-        d -= 0x100;
-        SET_FLAG(F_AF);
-        SET_FLAG(F_CF);
+       d -= 0x6;
+       d -= 0x100;
+       SET_FLAG(F_AF);
+       SET_FLAG(F_CF);
     } else {
-        CLEAR_FLAG(F_CF);
-        CLEAR_FLAG(F_AF);
+       CLEAR_FLAG(F_CF);
+       CLEAR_FLAG(F_AF);
     }
     res = (u16)(d & 0xFF0F);
     set_szp_flags_16(res);
@@ -308,7 +308,7 @@ u16 adc_word(u16 d, u16 s)
 
     res = d + s;
     if (ACCESS_FLAG(F_CF))
-        res++;
+       res++;
 
     set_szp_flags_16((u16)res);
     calc_carry_chain(16,s,d,res,1);
@@ -330,8 +330,8 @@ u32 adc_long(u32 d, u32 s)
     res = d + s;
 
     if (ACCESS_FLAG(F_CF)) {
-        lo++;
-        res++;
+       lo++;
+       res++;
     }
 
     hi = (lo >> 16) + (d >> 16) + (s >> 16);
@@ -485,12 +485,12 @@ u8 daa_byte(u8 d)
 {
     u32 res = d;
     if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) {
-        res += 6;
-        SET_FLAG(F_AF);
+       res += 6;
+       SET_FLAG(F_AF);
     }
     if (res > 0x9F || ACCESS_FLAG(F_CF)) {
-        res += 0x60;
-        SET_FLAG(F_CF);
+       res += 0x60;
+       SET_FLAG(F_CF);
     }
     set_szp_flags_8((u8)res);
     return (u8)res;
@@ -503,12 +503,12 @@ Implements the DAS instruction and side effects.
 u8 das_byte(u8 d)
 {
     if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) {
-        d -= 6;
-        SET_FLAG(F_AF);
+       d -= 6;
+       SET_FLAG(F_AF);
     }
     if (d > 0x9F || ACCESS_FLAG(F_CF)) {
-        d -= 0x60;
-        SET_FLAG(F_CF);
+       d -= 0x60;
+       SET_FLAG(F_CF);
     }
     set_szp_flags_8(d);
     return d;
@@ -749,45 +749,45 @@ u8 rcl_byte(u8 d, u8 s)
        original values, this can be expressed as:
 
        IF n > 0
-       1) CF <-  b_(8-n)
+       1) CF <-         b_(8-n)
        2) B_(7) .. B_(n)  <-  b_(8-(n+1)) .. b_0
        3) B_(n-1) <- cf
        4) B_(n-2) .. B_0 <-  b_7 .. b_(8-(n-1))
      */
     res = d;
     if ((cnt = s % 9) != 0) {
-        /* extract the new CARRY FLAG. */
-        /* CF <-  b_(8-n)             */
-        cf = (d >> (8 - cnt)) & 0x1;
-
-        /* get the low stuff which rotated
-           into the range B_7 .. B_cnt */
-        /* B_(7) .. B_(n)  <-  b_(8-(n+1)) .. b_0  */
-        /* note that the right hand side done by the mask */
-        res = (d << cnt) & 0xff;
-
-        /* now the high stuff which rotated around
-           into the positions B_cnt-2 .. B_0 */
-        /* B_(n-2) .. B_0 <-  b_7 .. b_(8-(n-1)) */
-        /* shift it downward, 7-(n-2) = 9-n positions.
-           and mask off the result before or'ing in.
-         */
-        mask = (1 << (cnt - 1)) - 1;
-        res |= (d >> (9 - cnt)) & mask;
-
-        /* if the carry flag was set, or it in.  */
-        if (ACCESS_FLAG(F_CF)) {     /* carry flag is set */
-            /*  B_(n-1) <- cf */
-            res |= 1 << (cnt - 1);
-        }
-        /* set the new carry flag, based on the variable "cf" */
-        CONDITIONAL_SET_FLAG(cf, F_CF);
-        /* OVERFLOW is set *IFF* cnt==1, then it is the
-           xor of CF and the most significant bit.  Blecck. */
-        /* parenthesized this expression since it appears to
-           be causing OF to be misset */
-        CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)),
-                             F_OF);
+       /* extract the new CARRY FLAG. */
+       /* CF <-  b_(8-n)             */
+       cf = (d >> (8 - cnt)) & 0x1;
+
+       /* get the low stuff which rotated
+          into the range B_7 .. B_cnt */
+       /* B_(7) .. B_(n)  <-  b_(8-(n+1)) .. b_0  */
+       /* note that the right hand side done by the mask */
+       res = (d << cnt) & 0xff;
+
+       /* now the high stuff which rotated around
+          into the positions B_cnt-2 .. B_0 */
+       /* B_(n-2) .. B_0 <-  b_7 .. b_(8-(n-1)) */
+       /* shift it downward, 7-(n-2) = 9-n positions.
+          and mask off the result before or'ing in.
+        */
+       mask = (1 << (cnt - 1)) - 1;
+       res |= (d >> (9 - cnt)) & mask;
+
+       /* if the carry flag was set, or it in.  */
+       if (ACCESS_FLAG(F_CF)) {     /* carry flag is set */
+           /*  B_(n-1) <- cf */
+           res |= 1 << (cnt - 1);
+       }
+       /* set the new carry flag, based on the variable "cf" */
+       CONDITIONAL_SET_FLAG(cf, F_CF);
+       /* OVERFLOW is set *IFF* cnt==1, then it is the
+          xor of CF and the most significant bit.  Blecck. */
+       /* parenthesized this expression since it appears to
+          be causing OF to be misset */
+       CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)),
+                            F_OF);
 
     }
     return (u8)res;
@@ -803,16 +803,16 @@ u16 rcl_word(u16 d, u8 s)
 
     res = d;
     if ((cnt = s % 17) != 0) {
-        cf = (d >> (16 - cnt)) & 0x1;
-        res = (d << cnt) & 0xffff;
-        mask = (1 << (cnt - 1)) - 1;
-        res |= (d >> (17 - cnt)) & mask;
-        if (ACCESS_FLAG(F_CF)) {
-            res |= 1 << (cnt - 1);
-        }
-        CONDITIONAL_SET_FLAG(cf, F_CF);
-        CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)),
-                             F_OF);
+       cf = (d >> (16 - cnt)) & 0x1;
+       res = (d << cnt) & 0xffff;
+       mask = (1 << (cnt - 1)) - 1;
+       res |= (d >> (17 - cnt)) & mask;
+       if (ACCESS_FLAG(F_CF)) {
+           res |= 1 << (cnt - 1);
+       }
+       CONDITIONAL_SET_FLAG(cf, F_CF);
+       CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)),
+                            F_OF);
     }
     return (u16)res;
 }
@@ -827,16 +827,16 @@ u32 rcl_long(u32 d, u8 s)
 
     res = d;
     if ((cnt = s % 33) != 0) {
-        cf = (d >> (32 - cnt)) & 0x1;
-        res = (d << cnt) & 0xffffffff;
-        mask = (1 << (cnt - 1)) - 1;
-        res |= (d >> (33 - cnt)) & mask;
-        if (ACCESS_FLAG(F_CF)) {     /* carry flag is set */
-            res |= 1 << (cnt - 1);
-        }
-        CONDITIONAL_SET_FLAG(cf, F_CF);
-        CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)),
-                             F_OF);
+       cf = (d >> (32 - cnt)) & 0x1;
+       res = (d << cnt) & 0xffffffff;
+       mask = (1 << (cnt - 1)) - 1;
+       res |= (d >> (33 - cnt)) & mask;
+       if (ACCESS_FLAG(F_CF)) {     /* carry flag is set */
+           res |= 1 << (cnt - 1);
+       }
+       CONDITIONAL_SET_FLAG(cf, F_CF);
+       CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)),
+                            F_OF);
     }
     return res;
 }
@@ -867,60 +867,60 @@ u8 rcr_byte(u8 d, u8 s)
        original values, this can be expressed as:
 
        IF n > 0
-       1) CF <-  b_(n-1)
-       2) B_(8-(n+1)) .. B_(0)  <-  b_(7) .. b_(n)
+       1) CF <-         b_(n-1)
+       2) B_(8-(n+1)) .. B_(0) <-  b_(7) .. b_(n)
        3) B_(8-n) <- cf
        4) B_(7) .. B_(8-(n-1)) <-  b_(n-2) .. b_(0)
      */
     res = d;
     if ((cnt = s % 9) != 0) {
-        /* extract the new CARRY FLAG. */
-        /* CF <-  b_(n-1)              */
-        if (cnt == 1) {
-            cf = d & 0x1;
-            /* note hackery here.  Access_flag(..) evaluates to either
-               0 if flag not set
-               non-zero if flag is set.
-               doing access_flag(..) != 0 casts that into either
-               0..1 in any representation of the flags register
-               (i.e. packed bit array or unpacked.)
-             */
-            ocf = ACCESS_FLAG(F_CF) != 0;
-        } else
-            cf = (d >> (cnt - 1)) & 0x1;
-
-        /* B_(8-(n+1)) .. B_(0)  <-  b_(7) .. b_n  */
-        /* note that the right hand side done by the mask
-           This is effectively done by shifting the
-           object to the right.  The result must be masked,
-           in case the object came in and was treated
-           as a negative number.  Needed??? */
-
-        mask = (1 << (8 - cnt)) - 1;
-        res = (d >> cnt) & mask;
-
-        /* now the high stuff which rotated around
-           into the positions B_cnt-2 .. B_0 */
-        /* B_(7) .. B_(8-(n-1)) <-  b_(n-2) .. b_(0) */
-        /* shift it downward, 7-(n-2) = 9-n positions.
-           and mask off the result before or'ing in.
-         */
-        res |= (d << (9 - cnt));
-
-        /* if the carry flag was set, or it in.  */
-        if (ACCESS_FLAG(F_CF)) {     /* carry flag is set */
-            /*  B_(8-n) <- cf */
-            res |= 1 << (8 - cnt);
-        }
-        /* set the new carry flag, based on the variable "cf" */
-        CONDITIONAL_SET_FLAG(cf, F_CF);
-        /* OVERFLOW is set *IFF* cnt==1, then it is the
-           xor of CF and the most significant bit.  Blecck. */
-        /* parenthesized... */
-        if (cnt == 1) {
-            CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)),
-                                 F_OF);
-        }
+       /* extract the new CARRY FLAG. */
+       /* CF <-  b_(n-1)              */
+       if (cnt == 1) {
+           cf = d & 0x1;
+           /* note hackery here.  Access_flag(..) evaluates to either
+              0 if flag not set
+              non-zero if flag is set.
+              doing access_flag(..) != 0 casts that into either
+              0..1 in any representation of the flags register
+              (i.e. packed bit array or unpacked.)
+            */
+           ocf = ACCESS_FLAG(F_CF) != 0;
+       } else
+           cf = (d >> (cnt - 1)) & 0x1;
+
+       /* B_(8-(n+1)) .. B_(0)  <-  b_(7) .. b_n  */
+       /* note that the right hand side done by the mask
+          This is effectively done by shifting the
+          object to the right.  The result must be masked,
+          in case the object came in and was treated
+          as a negative number.  Needed??? */
+
+       mask = (1 << (8 - cnt)) - 1;
+       res = (d >> cnt) & mask;
+
+       /* now the high stuff which rotated around
+          into the positions B_cnt-2 .. B_0 */
+       /* B_(7) .. B_(8-(n-1)) <-  b_(n-2) .. b_(0) */
+       /* shift it downward, 7-(n-2) = 9-n positions.
+          and mask off the result before or'ing in.
+        */
+       res |= (d << (9 - cnt));
+
+       /* if the carry flag was set, or it in.  */
+       if (ACCESS_FLAG(F_CF)) {     /* carry flag is set */
+           /*  B_(8-n) <- cf */
+           res |= 1 << (8 - cnt);
+       }
+       /* set the new carry flag, based on the variable "cf" */
+       CONDITIONAL_SET_FLAG(cf, F_CF);
+       /* OVERFLOW is set *IFF* cnt==1, then it is the
+          xor of CF and the most significant bit.  Blecck. */
+       /* parenthesized... */
+       if (cnt == 1) {
+           CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)),
+                                F_OF);
+       }
     }
     return (u8)res;
 }
@@ -937,22 +937,22 @@ u16 rcr_word(u16 d, u8 s)
     /* rotate right through carry */
     res = d;
     if ((cnt = s % 17) != 0) {
-        if (cnt == 1) {
-            cf = d & 0x1;
-            ocf = ACCESS_FLAG(F_CF) != 0;
-        } else
-            cf = (d >> (cnt - 1)) & 0x1;
-        mask = (1 << (16 - cnt)) - 1;
-        res = (d >> cnt) & mask;
-        res |= (d << (17 - cnt));
-        if (ACCESS_FLAG(F_CF)) {
-            res |= 1 << (16 - cnt);
-        }
-        CONDITIONAL_SET_FLAG(cf, F_CF);
-        if (cnt == 1) {
-            CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)),
-                                 F_OF);
-        }
+       if (cnt == 1) {
+           cf = d & 0x1;
+           ocf = ACCESS_FLAG(F_CF) != 0;
+       } else
+           cf = (d >> (cnt - 1)) & 0x1;
+       mask = (1 << (16 - cnt)) - 1;
+       res = (d >> cnt) & mask;
+       res |= (d << (17 - cnt));
+       if (ACCESS_FLAG(F_CF)) {
+           res |= 1 << (16 - cnt);
+       }
+       CONDITIONAL_SET_FLAG(cf, F_CF);
+       if (cnt == 1) {
+           CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)),
+                                F_OF);
+       }
     }
     return (u16)res;
 }
@@ -969,23 +969,23 @@ u32 rcr_long(u32 d, u8 s)
     /* rotate right through carry */
     res = d;
     if ((cnt = s % 33) != 0) {
-        if (cnt == 1) {
-            cf = d & 0x1;
-            ocf = ACCESS_FLAG(F_CF) != 0;
-        } else
-            cf = (d >> (cnt - 1)) & 0x1;
-        mask = (1 << (32 - cnt)) - 1;
-        res = (d >> cnt) & mask;
-        if (cnt != 1)
-            res |= (d << (33 - cnt));
-        if (ACCESS_FLAG(F_CF)) {     /* carry flag is set */
-            res |= 1 << (32 - cnt);
-        }
-        CONDITIONAL_SET_FLAG(cf, F_CF);
-        if (cnt == 1) {
-            CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)),
-                                 F_OF);
-        }
+       if (cnt == 1) {
+           cf = d & 0x1;
+           ocf = ACCESS_FLAG(F_CF) != 0;
+       } else
+           cf = (d >> (cnt - 1)) & 0x1;
+       mask = (1 << (32 - cnt)) - 1;
+       res = (d >> cnt) & mask;
+       if (cnt != 1)
+           res |= (d << (33 - cnt));
+       if (ACCESS_FLAG(F_CF)) {     /* carry flag is set */
+           res |= 1 << (32 - cnt);
+       }
+       CONDITIONAL_SET_FLAG(cf, F_CF);
+       if (cnt == 1) {
+           CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)),
+                                F_OF);
+       }
     }
     return res;
 }
@@ -1016,25 +1016,25 @@ u8 rol_byte(u8 d, u8 s)
      */
     res = d;
     if ((cnt = s % 8) != 0) {
-        /* B_(7) .. B_(n)  <-  b_(8-(n+1)) .. b_(0) */
-        res = (d << cnt);
-
-        /* B_(n-1) .. B_(0) <-  b_(7) .. b_(8-n) */
-        mask = (1 << cnt) - 1;
-        res |= (d >> (8 - cnt)) & mask;
-
-        /* set the new carry flag, Note that it is the low order
-           bit of the result!!!                               */
-        CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
-        /* OVERFLOW is set *IFF* s==1, then it is the
-           xor of CF and the most significant bit.  Blecck. */
-        CONDITIONAL_SET_FLAG(s == 1 &&
-                             XOR2((res & 0x1) + ((res >> 6) & 0x2)),
-                             F_OF);
+       /* B_(7) .. B_(n)  <-  b_(8-(n+1)) .. b_(0) */
+       res = (d << cnt);
+
+       /* B_(n-1) .. B_(0) <-  b_(7) .. b_(8-n) */
+       mask = (1 << cnt) - 1;
+       res |= (d >> (8 - cnt)) & mask;
+
+       /* set the new carry flag, Note that it is the low order
+          bit of the result!!!                               */
+       CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
+       /* OVERFLOW is set *IFF* s==1, then it is the
+          xor of CF and the most significant bit.  Blecck. */
+       CONDITIONAL_SET_FLAG(s == 1 &&
+                            XOR2((res & 0x1) + ((res >> 6) & 0x2)),
+                            F_OF);
     } if (s != 0) {
-        /* set the new carry flag, Note that it is the low order
-           bit of the result!!!                               */
-        CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
+       /* set the new carry flag, Note that it is the low order
+          bit of the result!!!                               */
+       CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
     }
     return (u8)res;
 }
@@ -1049,17 +1049,17 @@ u16 rol_word(u16 d, u8 s)
 
     res = d;
     if ((cnt = s % 16) != 0) {
-        res = (d << cnt);
-        mask = (1 << cnt) - 1;
-        res |= (d >> (16 - cnt)) & mask;
-        CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
-        CONDITIONAL_SET_FLAG(s == 1 &&
-                             XOR2((res & 0x1) + ((res >> 14) & 0x2)),
-                             F_OF);
+       res = (d << cnt);
+       mask = (1 << cnt) - 1;
+       res |= (d >> (16 - cnt)) & mask;
+       CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
+       CONDITIONAL_SET_FLAG(s == 1 &&
+                            XOR2((res & 0x1) + ((res >> 14) & 0x2)),
+                            F_OF);
     } if (s != 0) {
-        /* set the new carry flag, Note that it is the low order
-           bit of the result!!!                               */
-        CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
+       /* set the new carry flag, Note that it is the low order
+          bit of the result!!!                               */
+       CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
     }
     return (u16)res;
 }
@@ -1074,17 +1074,17 @@ u32 rol_long(u32 d, u8 s)
 
     res = d;
     if ((cnt = s % 32) != 0) {
-        res = (d << cnt);
-        mask = (1 << cnt) - 1;
-        res |= (d >> (32 - cnt)) & mask;
-        CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
-        CONDITIONAL_SET_FLAG(s == 1 &&
-                             XOR2((res & 0x1) + ((res >> 30) & 0x2)),
-                             F_OF);
+       res = (d << cnt);
+       mask = (1 << cnt) - 1;
+       res |= (d >> (32 - cnt)) & mask;
+       CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
+       CONDITIONAL_SET_FLAG(s == 1 &&
+                            XOR2((res & 0x1) + ((res >> 30) & 0x2)),
+                            F_OF);
     } if (s != 0) {
-        /* set the new carry flag, Note that it is the low order
-           bit of the result!!!                               */
-        CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
+       /* set the new carry flag, Note that it is the low order
+          bit of the result!!!                               */
+       CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
     }
     return res;
 }
@@ -1109,28 +1109,28 @@ u8 ror_byte(u8 d, u8 s)
        The rotate is done mod 8.
 
        IF n > 0
-       1) B_(8-(n+1)) .. B_(0)  <-  b_(7) .. b_(n)
+       1) B_(8-(n+1)) .. B_(0) <-  b_(7) .. b_(n)
        2) B_(7) .. B_(8-n) <-  b_(n-1) .. b_(0)
      */
     res = d;
-    if ((cnt = s % 8) != 0) {           /* not a typo, do nada if cnt==0 */
-        /* B_(7) .. B_(8-n) <-  b_(n-1) .. b_(0) */
-        res = (d << (8 - cnt));
-
-        /* B_(8-(n+1)) .. B_(0)  <-  b_(7) .. b_(n) */
-        mask = (1 << (8 - cnt)) - 1;
-        res |= (d >> (cnt)) & mask;
-
-        /* set the new carry flag, Note that it is the low order
-           bit of the result!!!                               */
-        CONDITIONAL_SET_FLAG(res & 0x80, F_CF);
-        /* OVERFLOW is set *IFF* s==1, then it is the
-           xor of the two most significant bits.  Blecck. */
-        CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF);
+    if ((cnt = s % 8) != 0) {          /* not a typo, do nada if cnt==0 */
+       /* B_(7) .. B_(8-n) <-  b_(n-1) .. b_(0) */
+       res = (d << (8 - cnt));
+
+       /* B_(8-(n+1)) .. B_(0)  <-  b_(7) .. b_(n) */
+       mask = (1 << (8 - cnt)) - 1;
+       res |= (d >> (cnt)) & mask;
+
+       /* set the new carry flag, Note that it is the low order
+          bit of the result!!!                               */
+       CONDITIONAL_SET_FLAG(res & 0x80, F_CF);
+       /* OVERFLOW is set *IFF* s==1, then it is the
+          xor of the two most significant bits.  Blecck. */
+       CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF);
     } else if (s != 0) {
-        /* set the new carry flag, Note that it is the low order
-           bit of the result!!!                               */
-        CONDITIONAL_SET_FLAG(res & 0x80, F_CF);
+       /* set the new carry flag, Note that it is the low order
+          bit of the result!!!                               */
+       CONDITIONAL_SET_FLAG(res & 0x80, F_CF);
     }
     return (u8)res;
 }
@@ -1145,15 +1145,15 @@ u16 ror_word(u16 d, u8 s)
 
     res = d;
     if ((cnt = s % 16) != 0) {
-        res = (d << (16 - cnt));
-        mask = (1 << (16 - cnt)) - 1;
-        res |= (d >> (cnt)) & mask;
-        CONDITIONAL_SET_FLAG(res & 0x8000, F_CF);
-        CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF);
+       res = (d << (16 - cnt));
+       mask = (1 << (16 - cnt)) - 1;
+       res |= (d >> (cnt)) & mask;
+       CONDITIONAL_SET_FLAG(res & 0x8000, F_CF);
+       CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF);
     } else if (s != 0) {
-        /* set the new carry flag, Note that it is the low order
-           bit of the result!!!                               */
-        CONDITIONAL_SET_FLAG(res & 0x8000, F_CF);
+       /* set the new carry flag, Note that it is the low order
+          bit of the result!!!                               */
+       CONDITIONAL_SET_FLAG(res & 0x8000, F_CF);
     }
     return (u16)res;
 }
@@ -1168,15 +1168,15 @@ u32 ror_long(u32 d, u8 s)
 
     res = d;
     if ((cnt = s % 32) != 0) {
-        res = (d << (32 - cnt));
-        mask = (1 << (32 - cnt)) - 1;
-        res |= (d >> (cnt)) & mask;
-        CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF);
-        CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF);
+       res = (d << (32 - cnt));
+       mask = (1 << (32 - cnt)) - 1;
+       res |= (d >> (cnt)) & mask;
+       CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF);
+       CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF);
     } else if (s != 0) {
-        /* set the new carry flag, Note that it is the low order
-           bit of the result!!!                               */
-        CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF);
+       /* set the new carry flag, Note that it is the low order
+          bit of the result!!!                               */
+       CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF);
     }
     return res;
 }
@@ -1190,35 +1190,35 @@ u8 shl_byte(u8 d, u8 s)
     unsigned int cnt, res, cf;
 
     if (s < 8) {
-        cnt = s % 8;
-
-        /* last bit shifted out goes into carry flag */
-        if (cnt > 0) {
-            res = d << cnt;
-            cf = d & (1 << (8 - cnt));
-            CONDITIONAL_SET_FLAG(cf, F_CF);
-            set_szp_flags_8((u8)res);
-        } else {
-            res = (u8) d;
-        }
-
-        if (cnt == 1) {
-            /* Needs simplification. */
-            CONDITIONAL_SET_FLAG(
-                                    (((res & 0x80) == 0x80) ^
-                                     (ACCESS_FLAG(F_CF) != 0)),
-            /* was (M.x86.R_FLG&F_CF)==F_CF)), */
-                                    F_OF);
-        } else {
-            CLEAR_FLAG(F_OF);
-        }
+       cnt = s % 8;
+
+       /* last bit shifted out goes into carry flag */
+       if (cnt > 0) {
+           res = d << cnt;
+           cf = d & (1 << (8 - cnt));
+           CONDITIONAL_SET_FLAG(cf, F_CF);
+           set_szp_flags_8((u8)res);
+       } else {
+           res = (u8) d;
+       }
+
+       if (cnt == 1) {
+           /* Needs simplification. */
+           CONDITIONAL_SET_FLAG(
+                                   (((res & 0x80) == 0x80) ^
+                                    (ACCESS_FLAG(F_CF) != 0)),
+           /* was (M.x86.R_FLG&F_CF)==F_CF)), */
+                                   F_OF);
+       } else {
+           CLEAR_FLAG(F_OF);
+       }
     } else {
-        res = 0;
-        CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF);
-        CLEAR_FLAG(F_OF);
-        CLEAR_FLAG(F_SF);
-        SET_FLAG(F_PF);
-        SET_FLAG(F_ZF);
+       res = 0;
+       CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF);
+       CLEAR_FLAG(F_OF);
+       CLEAR_FLAG(F_SF);
+       SET_FLAG(F_PF);
+       SET_FLAG(F_ZF);
     }
     return (u8)res;
 }
@@ -1232,31 +1232,31 @@ u16 shl_word(u16 d, u8 s)
     unsigned int cnt, res, cf;
 
     if (s < 16) {
-        cnt = s % 16;
-        if (cnt > 0) {
-            res = d << cnt;
-            cf = d & (1 << (16 - cnt));
-            CONDITIONAL_SET_FLAG(cf, F_CF);
-            set_szp_flags_16((u16)res);
-        } else {
-            res = (u16) d;
-        }
-
-        if (cnt == 1) {
-            CONDITIONAL_SET_FLAG(
-                                    (((res & 0x8000) == 0x8000) ^
-                                     (ACCESS_FLAG(F_CF) != 0)),
-                                    F_OF);
-        } else {
-            CLEAR_FLAG(F_OF);
-        }
+       cnt = s % 16;
+       if (cnt > 0) {
+           res = d << cnt;
+           cf = d & (1 << (16 - cnt));
+           CONDITIONAL_SET_FLAG(cf, F_CF);
+           set_szp_flags_16((u16)res);
+       } else {
+           res = (u16) d;
+       }
+
+       if (cnt == 1) {
+           CONDITIONAL_SET_FLAG(
+                                   (((res & 0x8000) == 0x8000) ^
+                                    (ACCESS_FLAG(F_CF) != 0)),
+                                   F_OF);
+       } else {
+           CLEAR_FLAG(F_OF);
+       }
     } else {
-        res = 0;
-        CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF);
-        CLEAR_FLAG(F_OF);
-        CLEAR_FLAG(F_SF);
-        SET_FLAG(F_PF);
-        SET_FLAG(F_ZF);
+       res = 0;
+       CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF);
+       CLEAR_FLAG(F_OF);
+       CLEAR_FLAG(F_SF);
+       SET_FLAG(F_PF);
+       SET_FLAG(F_ZF);
     }
     return (u16)res;
 }
@@ -1270,28 +1270,28 @@ u32 shl_long(u32 d, u8 s)
     unsigned int cnt, res, cf;
 
     if (s < 32) {
-        cnt = s % 32;
-        if (cnt > 0) {
-            res = d << cnt;
-            cf = d & (1 << (32 - cnt));
-            CONDITIONAL_SET_FLAG(cf, F_CF);
-            set_szp_flags_32((u32)res);
-        } else {
-            res = d;
-        }
-        if (cnt == 1) {
-            CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^
-                                  (ACCESS_FLAG(F_CF) != 0)), F_OF);
-        } else {
-            CLEAR_FLAG(F_OF);
-        }
+       cnt = s % 32;
+       if (cnt > 0) {
+           res = d << cnt;
+           cf = d & (1 << (32 - cnt));
+           CONDITIONAL_SET_FLAG(cf, F_CF);
+           set_szp_flags_32((u32)res);
+       } else {
+           res = d;
+       }
+       if (cnt == 1) {
+           CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^
+                                 (ACCESS_FLAG(F_CF) != 0)), F_OF);
+       } else {
+           CLEAR_FLAG(F_OF);
+       }
     } else {
-        res = 0;
-        CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF);
-        CLEAR_FLAG(F_OF);
-        CLEAR_FLAG(F_SF);
-        SET_FLAG(F_PF);
-        SET_FLAG(F_ZF);
+       res = 0;
+       CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF);
+       CLEAR_FLAG(F_OF);
+       CLEAR_FLAG(F_SF);
+       SET_FLAG(F_PF);
+       SET_FLAG(F_ZF);
     }
     return res;
 }
@@ -1305,28 +1305,28 @@ u8 shr_byte(u8 d, u8 s)
     unsigned int cnt, res, cf;
 
     if (s < 8) {
-        cnt = s % 8;
-        if (cnt > 0) {
-            cf = d & (1 << (cnt - 1));
-            res = d >> cnt;
-            CONDITIONAL_SET_FLAG(cf, F_CF);
-            set_szp_flags_8((u8)res);
-        } else {
-            res = (u8) d;
-        }
-
-        if (cnt == 1) {
-            CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF);
-        } else {
-            CLEAR_FLAG(F_OF);
-        }
+       cnt = s % 8;
+       if (cnt > 0) {
+           cf = d & (1 << (cnt - 1));
+           res = d >> cnt;
+           CONDITIONAL_SET_FLAG(cf, F_CF);
+           set_szp_flags_8((u8)res);
+       } else {
+           res = (u8) d;
+       }
+
+       if (cnt == 1) {
+           CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF);
+       } else {
+           CLEAR_FLAG(F_OF);
+       }
     } else {
-        res = 0;
-        CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF);
-        CLEAR_FLAG(F_OF);
-        CLEAR_FLAG(F_SF);
-        SET_FLAG(F_PF);
-        SET_FLAG(F_ZF);
+       res = 0;
+       CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF);
+       CLEAR_FLAG(F_OF);
+       CLEAR_FLAG(F_SF);
+       SET_FLAG(F_PF);
+       SET_FLAG(F_ZF);
     }
     return (u8)res;
 }
@@ -1340,28 +1340,28 @@ u16 shr_word(u16 d, u8 s)
     unsigned int cnt, res, cf;
 
     if (s < 16) {
-        cnt = s % 16;
-        if (cnt > 0) {
-            cf = d & (1 << (cnt - 1));
-            res = d >> cnt;
-            CONDITIONAL_SET_FLAG(cf, F_CF);
-            set_szp_flags_16((u16)res);
-        } else {
-            res = d;
-        }
-
-        if (cnt == 1) {
-            CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF);
-        } else {
-            CLEAR_FLAG(F_OF);
-        }
+       cnt = s % 16;
+       if (cnt > 0) {
+           cf = d & (1 << (cnt - 1));
+           res = d >> cnt;
+           CONDITIONAL_SET_FLAG(cf, F_CF);
+           set_szp_flags_16((u16)res);
+       } else {
+           res = d;
+       }
+
+       if (cnt == 1) {
+           CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF);
+       } else {
+           CLEAR_FLAG(F_OF);
+       }
     } else {
-        res = 0;
-        CLEAR_FLAG(F_CF);
-        CLEAR_FLAG(F_OF);
-        SET_FLAG(F_ZF);
-        CLEAR_FLAG(F_SF);
-        CLEAR_FLAG(F_PF);
+       res = 0;
+       CLEAR_FLAG(F_CF);
+       CLEAR_FLAG(F_OF);
+       SET_FLAG(F_ZF);
+       CLEAR_FLAG(F_SF);
+       CLEAR_FLAG(F_PF);
     }
     return (u16)res;
 }
@@ -1375,27 +1375,27 @@ u32 shr_long(u32 d, u8 s)
     unsigned int cnt, res, cf;
 
     if (s < 32) {
-        cnt = s % 32;
-        if (cnt > 0) {
-            cf = d & (1 << (cnt - 1));
-            res = d >> cnt;
-            CONDITIONAL_SET_FLAG(cf, F_CF);
-            set_szp_flags_32((u32)res);
-        } else {
-            res = d;
-        }
-        if (cnt == 1) {
-            CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF);
-        } else {
-            CLEAR_FLAG(F_OF);
-        }
+       cnt = s % 32;
+       if (cnt > 0) {
+           cf = d & (1 << (cnt - 1));
+           res = d >> cnt;
+           CONDITIONAL_SET_FLAG(cf, F_CF);
+           set_szp_flags_32((u32)res);
+       } else {
+           res = d;
+       }
+       if (cnt == 1) {
+           CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF);
+       } else {
+           CLEAR_FLAG(F_OF);
+       }
     } else {
-        res = 0;
-        CLEAR_FLAG(F_CF);
-        CLEAR_FLAG(F_OF);
-        SET_FLAG(F_ZF);
-        CLEAR_FLAG(F_SF);
-        CLEAR_FLAG(F_PF);
+       res = 0;
+       CLEAR_FLAG(F_CF);
+       CLEAR_FLAG(F_OF);
+       SET_FLAG(F_ZF);
+       CLEAR_FLAG(F_SF);
+       CLEAR_FLAG(F_PF);
     }
     return res;
 }
@@ -1412,28 +1412,28 @@ u8 sar_byte(u8 d, u8 s)
     sf = d & 0x80;
     cnt = s % 8;
     if (cnt > 0 && cnt < 8) {
-        mask = (1 << (8 - cnt)) - 1;
-        cf = d & (1 << (cnt - 1));
-        res = (d >> cnt) & mask;
-        CONDITIONAL_SET_FLAG(cf, F_CF);
-        if (sf) {
-            res |= ~mask;
-        }
-        set_szp_flags_8((u8)res);
+       mask = (1 << (8 - cnt)) - 1;
+       cf = d & (1 << (cnt - 1));
+       res = (d >> cnt) & mask;
+       CONDITIONAL_SET_FLAG(cf, F_CF);
+       if (sf) {
+           res |= ~mask;
+       }
+       set_szp_flags_8((u8)res);
     } else if (cnt >= 8) {
-        if (sf) {
-            res = 0xff;
-            SET_FLAG(F_CF);
-            CLEAR_FLAG(F_ZF);
-            SET_FLAG(F_SF);
-            SET_FLAG(F_PF);
-        } else {
-            res = 0;
-            CLEAR_FLAG(F_CF);
-            SET_FLAG(F_ZF);
-            CLEAR_FLAG(F_SF);
-            CLEAR_FLAG(F_PF);
-        }
+       if (sf) {
+           res = 0xff;
+           SET_FLAG(F_CF);
+           CLEAR_FLAG(F_ZF);
+           SET_FLAG(F_SF);
+           SET_FLAG(F_PF);
+       } else {
+           res = 0;
+           CLEAR_FLAG(F_CF);
+           SET_FLAG(F_ZF);
+           CLEAR_FLAG(F_SF);
+           CLEAR_FLAG(F_PF);
+       }
     }
     return (u8)res;
 }
@@ -1450,28 +1450,28 @@ u16 sar_word(u16 d, u8 s)
     cnt = s % 16;
     res = d;
     if (cnt > 0 && cnt < 16) {
-        mask = (1 << (16 - cnt)) - 1;
-        cf = d & (1 << (cnt - 1));
-        res = (d >> cnt) & mask;
-        CONDITIONAL_SET_FLAG(cf, F_CF);
-        if (sf) {
-            res |= ~mask;
-        }
-        set_szp_flags_16((u16)res);
+       mask = (1 << (16 - cnt)) - 1;
+       cf = d & (1 << (cnt - 1));
+       res = (d >> cnt) & mask;
+       CONDITIONAL_SET_FLAG(cf, F_CF);
+       if (sf) {
+           res |= ~mask;
+       }
+       set_szp_flags_16((u16)res);
     } else if (cnt >= 16) {
-        if (sf) {
-            res = 0xffff;
-            SET_FLAG(F_CF);
-            CLEAR_FLAG(F_ZF);
-            SET_FLAG(F_SF);
-            SET_FLAG(F_PF);
-        } else {
-            res = 0;
-            CLEAR_FLAG(F_CF);
-            SET_FLAG(F_ZF);
-            CLEAR_FLAG(F_SF);
-            CLEAR_FLAG(F_PF);
-        }
+       if (sf) {
+           res = 0xffff;
+           SET_FLAG(F_CF);
+           CLEAR_FLAG(F_ZF);
+           SET_FLAG(F_SF);
+           SET_FLAG(F_PF);
+       } else {
+           res = 0;
+           CLEAR_FLAG(F_CF);
+           SET_FLAG(F_ZF);
+           CLEAR_FLAG(F_SF);
+           CLEAR_FLAG(F_PF);
+       }
     }
     return (u16)res;
 }
@@ -1488,28 +1488,28 @@ u32 sar_long(u32 d, u8 s)
     cnt = s % 32;
     res = d;
     if (cnt > 0 && cnt < 32) {
-        mask = (1 << (32 - cnt)) - 1;
-        cf = d & (1 << (cnt - 1));
-        res = (d >> cnt) & mask;
-        CONDITIONAL_SET_FLAG(cf, F_CF);
-        if (sf) {
-            res |= ~mask;
-        }
-        set_szp_flags_32(res);
+       mask = (1 << (32 - cnt)) - 1;
+       cf = d & (1 << (cnt - 1));
+       res = (d >> cnt) & mask;
+       CONDITIONAL_SET_FLAG(cf, F_CF);
+       if (sf) {
+           res |= ~mask;
+       }
+       set_szp_flags_32(res);
     } else if (cnt >= 32) {
-        if (sf) {
-            res = 0xffffffff;
-            SET_FLAG(F_CF);
-            CLEAR_FLAG(F_ZF);
-            SET_FLAG(F_SF);
-            SET_FLAG(F_PF);
-        } else {
-            res = 0;
-            CLEAR_FLAG(F_CF);
-            SET_FLAG(F_ZF);
-            CLEAR_FLAG(F_SF);
-            CLEAR_FLAG(F_PF);
-        }
+       if (sf) {
+           res = 0xffffffff;
+           SET_FLAG(F_CF);
+           CLEAR_FLAG(F_ZF);
+           SET_FLAG(F_SF);
+           SET_FLAG(F_PF);
+       } else {
+           res = 0;
+           CLEAR_FLAG(F_CF);
+           SET_FLAG(F_ZF);
+           CLEAR_FLAG(F_SF);
+           CLEAR_FLAG(F_PF);
+       }
     }
     return res;
 }
@@ -1523,28 +1523,28 @@ u16 shld_word (u16 d, u16 fill, u8 s)
     unsigned int cnt, res, cf;
 
     if (s < 16) {
-        cnt = s % 16;
-        if (cnt > 0) {
-            res = (d << cnt) | (fill >> (16-cnt));
-            cf = d & (1 << (16 - cnt));
-            CONDITIONAL_SET_FLAG(cf, F_CF);
-            set_szp_flags_16((u16)res);
-        } else {
-            res = d;
-        }
-        if (cnt == 1) {
-            CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^
-                                  (ACCESS_FLAG(F_CF) != 0)), F_OF);
-        } else {
-            CLEAR_FLAG(F_OF);
-        }
+       cnt = s % 16;
+       if (cnt > 0) {
+           res = (d << cnt) | (fill >> (16-cnt));
+           cf = d & (1 << (16 - cnt));
+           CONDITIONAL_SET_FLAG(cf, F_CF);
+           set_szp_flags_16((u16)res);
+       } else {
+           res = d;
+       }
+       if (cnt == 1) {
+           CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^
+                                 (ACCESS_FLAG(F_CF) != 0)), F_OF);
+       } else {
+           CLEAR_FLAG(F_OF);
+       }
     } else {
-        res = 0;
-        CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF);
-        CLEAR_FLAG(F_OF);
-        CLEAR_FLAG(F_SF);
-        SET_FLAG(F_PF);
-        SET_FLAG(F_ZF);
+       res = 0;
+       CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF);
+       CLEAR_FLAG(F_OF);
+       CLEAR_FLAG(F_SF);
+       SET_FLAG(F_PF);
+       SET_FLAG(F_ZF);
     }
     return (u16)res;
 }
@@ -1558,28 +1558,28 @@ u32 shld_long (u32 d, u32 fill, u8 s)
     unsigned int cnt, res, cf;
 
     if (s < 32) {
-        cnt = s % 32;
-        if (cnt > 0) {
-            res = (d << cnt) | (fill >> (32-cnt));
-            cf = d & (1 << (32 - cnt));
-            CONDITIONAL_SET_FLAG(cf, F_CF);
-            set_szp_flags_32((u32)res);
-        } else {
-            res = d;
-        }
-        if (cnt == 1) {
-            CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^
-                                  (ACCESS_FLAG(F_CF) != 0)), F_OF);
-        } else {
-            CLEAR_FLAG(F_OF);
-        }
+       cnt = s % 32;
+       if (cnt > 0) {
+           res = (d << cnt) | (fill >> (32-cnt));
+           cf = d & (1 << (32 - cnt));
+           CONDITIONAL_SET_FLAG(cf, F_CF);
+           set_szp_flags_32((u32)res);
+       } else {
+           res = d;
+       }
+       if (cnt == 1) {
+           CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^
+                                 (ACCESS_FLAG(F_CF) != 0)), F_OF);
+       } else {
+           CLEAR_FLAG(F_OF);
+       }
     } else {
-        res = 0;
-        CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF);
-        CLEAR_FLAG(F_OF);
-        CLEAR_FLAG(F_SF);
-        SET_FLAG(F_PF);
-        SET_FLAG(F_ZF);
+       res = 0;
+       CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF);
+       CLEAR_FLAG(F_OF);
+       CLEAR_FLAG(F_SF);
+       SET_FLAG(F_PF);
+       SET_FLAG(F_ZF);
     }
     return res;
 }
@@ -1593,28 +1593,28 @@ u16 shrd_word (u16 d, u16 fill, u8 s)
     unsigned int cnt, res, cf;
 
     if (s < 16) {
-        cnt = s % 16;
-        if (cnt > 0) {
-            cf = d & (1 << (cnt - 1));
-            res = (d >> cnt) | (fill << (16 - cnt));
-            CONDITIONAL_SET_FLAG(cf, F_CF);
-            set_szp_flags_16((u16)res);
-        } else {
-            res = d;
-        }
-
-        if (cnt == 1) {
-            CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF);
-        } else {
-            CLEAR_FLAG(F_OF);
-        }
+       cnt = s % 16;
+       if (cnt > 0) {
+           cf = d & (1 << (cnt - 1));
+           res = (d >> cnt) | (fill << (16 - cnt));
+           CONDITIONAL_SET_FLAG(cf, F_CF);
+           set_szp_flags_16((u16)res);
+       } else {
+           res = d;
+       }
+
+       if (cnt == 1) {
+           CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF);
+       } else {
+           CLEAR_FLAG(F_OF);
+       }
     } else {
-        res = 0;
-        CLEAR_FLAG(F_CF);
-        CLEAR_FLAG(F_OF);
-        SET_FLAG(F_ZF);
-        CLEAR_FLAG(F_SF);
-        CLEAR_FLAG(F_PF);
+       res = 0;
+       CLEAR_FLAG(F_CF);
+       CLEAR_FLAG(F_OF);
+       SET_FLAG(F_ZF);
+       CLEAR_FLAG(F_SF);
+       CLEAR_FLAG(F_PF);
     }
     return (u16)res;
 }
@@ -1628,27 +1628,27 @@ u32 shrd_long (u32 d, u32 fill, u8 s)
     unsigned int cnt, res, cf;
 
     if (s < 32) {
-        cnt = s % 32;
-        if (cnt > 0) {
-            cf = d & (1 << (cnt - 1));
-            res = (d >> cnt) | (fill << (32 - cnt));
-            CONDITIONAL_SET_FLAG(cf, F_CF);
-            set_szp_flags_32((u32)res);
-        } else {
-            res = d;
-        }
-        if (cnt == 1) {
-            CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF);
-        } else {
-            CLEAR_FLAG(F_OF);
-        }
+       cnt = s % 32;
+       if (cnt > 0) {
+           cf = d & (1 << (cnt - 1));
+           res = (d >> cnt) | (fill << (32 - cnt));
+           CONDITIONAL_SET_FLAG(cf, F_CF);
+           set_szp_flags_32((u32)res);
+       } else {
+           res = d;
+       }
+       if (cnt == 1) {
+           CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF);
+       } else {
+           CLEAR_FLAG(F_OF);
+       }
     } else {
-        res = 0;
-        CLEAR_FLAG(F_CF);
-        CLEAR_FLAG(F_OF);
-        SET_FLAG(F_ZF);
-        CLEAR_FLAG(F_SF);
-        CLEAR_FLAG(F_PF);
+       res = 0;
+       CLEAR_FLAG(F_CF);
+       CLEAR_FLAG(F_OF);
+       SET_FLAG(F_ZF);
+       CLEAR_FLAG(F_SF);
+       CLEAR_FLAG(F_PF);
     }
     return res;
 }
@@ -1663,9 +1663,9 @@ u8 sbb_byte(u8 d, u8 s)
     u32 bc;
 
     if (ACCESS_FLAG(F_CF))
-        res = d - s - 1;
+       res = d - s - 1;
     else
-        res = d - s;
+       res = d - s;
     set_szp_flags_8((u8)res);
 
     /* calculate the borrow chain.  See note at top */
@@ -1686,9 +1686,9 @@ u16 sbb_word(u16 d, u16 s)
     u32 bc;
 
     if (ACCESS_FLAG(F_CF))
-        res = d - s - 1;
+       res = d - s - 1;
     else
-        res = d - s;
+       res = d - s;
     set_szp_flags_16((u16)res);
 
     /* calculate the borrow chain.  See note at top */
@@ -1709,9 +1709,9 @@ u32 sbb_long(u32 d, u32 s)
     u32 bc;
 
     if (ACCESS_FLAG(F_CF))
-        res = d - s - 1;
+       res = d - s - 1;
     else
-        res = d - s;
+       res = d - s;
 
     set_szp_flags_32(res);
 
@@ -1880,12 +1880,12 @@ void imul_byte(u8 s)
 
     M.x86.R_AX = res;
     if (((M.x86.R_AL & 0x80) == 0 && M.x86.R_AH == 0x00) ||
-        ((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) {
-        CLEAR_FLAG(F_CF);
-        CLEAR_FLAG(F_OF);
+       ((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) {
+       CLEAR_FLAG(F_CF);
+       CLEAR_FLAG(F_OF);
     } else {
-        SET_FLAG(F_CF);
-        SET_FLAG(F_OF);
+       SET_FLAG(F_CF);
+       SET_FLAG(F_OF);
     }
 }
 
@@ -1900,12 +1900,12 @@ void imul_word(u16 s)
     M.x86.R_AX = (u16)res;
     M.x86.R_DX = (u16)(res >> 16);
     if (((M.x86.R_AX & 0x8000) == 0 && M.x86.R_DX == 0x0000) ||
-        ((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFFFF)) {
-        CLEAR_FLAG(F_CF);
-        CLEAR_FLAG(F_OF);
+       ((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFFFF)) {
+       CLEAR_FLAG(F_CF);
+       CLEAR_FLAG(F_OF);
     } else {
-        SET_FLAG(F_CF);
-        SET_FLAG(F_OF);
+       SET_FLAG(F_CF);
+       SET_FLAG(F_OF);
     }
 }
 
@@ -1915,7 +1915,7 @@ Implements the IMUL instruction and side effects.
 ****************************************************************************/
 void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s)
 {
-#ifdef  __HAS_LONG_LONG__
+#ifdef __HAS_LONG_LONG__
     s64 res = (s32)d * (s32)s;
 
     *res_lo = (u32)res;
@@ -1926,11 +1926,11 @@ void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s)
     u32 rlo_lo,rlo_hi,rhi_lo;
 
     if ((d_sign = d & 0x80000000) != 0)
-        d = -d;
+       d = -d;
     d_lo = d & 0xFFFF;
     d_hi = d >> 16;
     if ((s_sign = s & 0x80000000) != 0)
-        s = -s;
+       s = -s;
     s_lo = s & 0xFFFF;
     s_hi = s >> 16;
     rlo_lo = d_lo * s_lo;
@@ -1939,11 +1939,11 @@ void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s)
     *res_lo = (rlo_hi << 16) | (rlo_lo & 0xFFFF);
     *res_hi = rhi_lo;
     if (d_sign != s_sign) {
-        d = ~*res_lo;
-        s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16);
-        *res_lo = ~*res_lo+1;
-        *res_hi = ~*res_hi+(s >> 16);
-        }
+       d = ~*res_lo;
+       s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16);
+       *res_lo = ~*res_lo+1;
+       *res_hi = ~*res_hi+(s >> 16);
+       }
 #endif
 }
 
@@ -1955,12 +1955,12 @@ void imul_long(u32 s)
 {
     imul_long_direct(&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s);
     if (((M.x86.R_EAX & 0x80000000) == 0 && M.x86.R_EDX == 0x00000000) ||
-        ((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFFFFFFFF)) {
-        CLEAR_FLAG(F_CF);
-        CLEAR_FLAG(F_OF);
+       ((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFFFFFFFF)) {
+       CLEAR_FLAG(F_CF);
+       CLEAR_FLAG(F_OF);
     } else {
-        SET_FLAG(F_CF);
-        SET_FLAG(F_OF);
+       SET_FLAG(F_CF);
+       SET_FLAG(F_OF);
     }
 }
 
@@ -1974,11 +1974,11 @@ void mul_byte(u8 s)
 
     M.x86.R_AX = res;
     if (M.x86.R_AH == 0) {
-        CLEAR_FLAG(F_CF);
-        CLEAR_FLAG(F_OF);
+       CLEAR_FLAG(F_CF);
+       CLEAR_FLAG(F_OF);
     } else {
-        SET_FLAG(F_CF);
-        SET_FLAG(F_OF);
+       SET_FLAG(F_CF);
+       SET_FLAG(F_OF);
     }
 }
 
@@ -1993,11 +1993,11 @@ void mul_word(u16 s)
     M.x86.R_AX = (u16)res;
     M.x86.R_DX = (u16)(res >> 16);
     if (M.x86.R_DX == 0) {
-        CLEAR_FLAG(F_CF);
-        CLEAR_FLAG(F_OF);
+       CLEAR_FLAG(F_CF);
+       CLEAR_FLAG(F_OF);
     } else {
-        SET_FLAG(F_CF);
-        SET_FLAG(F_OF);
+       SET_FLAG(F_CF);
+       SET_FLAG(F_OF);
     }
 }
 
@@ -2007,7 +2007,7 @@ Implements the MUL instruction and side effects.
 ****************************************************************************/
 void mul_long(u32 s)
 {
-#ifdef  __HAS_LONG_LONG__
+#ifdef __HAS_LONG_LONG__
     u64 res = (u32)M.x86.R_EAX * (u32)s;
 
     M.x86.R_EAX = (u32)res;
@@ -2029,11 +2029,11 @@ void mul_long(u32 s)
     M.x86.R_EDX = rhi_lo;
 #endif
     if (M.x86.R_EDX == 0) {
-        CLEAR_FLAG(F_CF);
-        CLEAR_FLAG(F_OF);
+       CLEAR_FLAG(F_CF);
+       CLEAR_FLAG(F_OF);
     } else {
-        SET_FLAG(F_CF);
-        SET_FLAG(F_OF);
+       SET_FLAG(F_CF);
+       SET_FLAG(F_OF);
     }
 }
 
@@ -2047,14 +2047,14 @@ void idiv_byte(u8 s)
 
     dvd = (s16)M.x86.R_AX;
     if (s == 0) {
-        x86emu_intr_raise(0);
-        return;
+       x86emu_intr_raise(0);
+       return;
     }
     div = dvd / (s8)s;
     mod = dvd % (s8)s;
     if (abs(div) > 0x7f) {
-        x86emu_intr_raise(0);
-        return;
+       x86emu_intr_raise(0);
+       return;
     }
     M.x86.R_AL = (s8) div;
     M.x86.R_AH = (s8) mod;
@@ -2070,14 +2070,14 @@ void idiv_word(u16 s)
 
     dvd = (((s32)M.x86.R_DX) << 16) | M.x86.R_AX;
     if (s == 0) {
-        x86emu_intr_raise(0);
-        return;
+       x86emu_intr_raise(0);
+       return;
     }
     div = dvd / (s16)s;
     mod = dvd % (s16)s;
     if (abs(div) > 0x7fff) {
-        x86emu_intr_raise(0);
-        return;
+       x86emu_intr_raise(0);
+       return;
     }
     CLEAR_FLAG(F_CF);
     CLEAR_FLAG(F_SF);
@@ -2094,19 +2094,19 @@ Implements the IDIV instruction and side effects.
 ****************************************************************************/
 void idiv_long(u32 s)
 {
-#ifdef  __HAS_LONG_LONG__
+#ifdef __HAS_LONG_LONG__
     s64 dvd, div, mod;
 
     dvd = (((s64)M.x86.R_EDX) << 32) | M.x86.R_EAX;
     if (s == 0) {
-        x86emu_intr_raise(0);
-        return;
+       x86emu_intr_raise(0);
+       return;
     }
     div = dvd / (s32)s;
     mod = dvd % (s32)s;
     if (abs(div) > 0x7fffffff) {
-        x86emu_intr_raise(0);
-        return;
+       x86emu_intr_raise(0);
+       return;
     }
 #else
     s32 div = 0, mod;
@@ -2120,32 +2120,32 @@ void idiv_long(u32 s)
     int carry;
 
     if (s == 0) {
-        x86emu_intr_raise(0);
-        return;
+       x86emu_intr_raise(0);
+       return;
     }
     do {
-        div <<= 1;
-        carry = (l_dvd >= l_s) ? 0 : 1;
-
-        if (abs_h_dvd < (h_s + carry)) {
-            h_s >>= 1;
-            l_s = abs_s << (--counter);
-            continue;
-        } else {
-            abs_h_dvd -= (h_s + carry);
-            l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1)
-                : (l_dvd - l_s);
-            h_s >>= 1;
-            l_s = abs_s << (--counter);
-            div |= 1;
-            continue;
-        }
+       div <<= 1;
+       carry = (l_dvd >= l_s) ? 0 : 1;
+
+       if (abs_h_dvd < (h_s + carry)) {
+           h_s >>= 1;
+           l_s = abs_s << (--counter);
+           continue;
+       } else {
+           abs_h_dvd -= (h_s + carry);
+           l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1)
+               : (l_dvd - l_s);
+           h_s >>= 1;
+           l_s = abs_s << (--counter);
+           div |= 1;
+           continue;
+       }
 
     } while (counter > -1);
     /* overflow */
     if (abs_h_dvd || (l_dvd > abs_s)) {
-        x86emu_intr_raise(0);
-        return;
+       x86emu_intr_raise(0);
+       return;
     }
     /* sign */
     div |= ((h_dvd & 0x10000000) ^ (s & 0x10000000));
@@ -2172,14 +2172,14 @@ void div_byte(u8 s)
 
     dvd = M.x86.R_AX;
     if (s == 0) {
-        x86emu_intr_raise(0);
-        return;
+       x86emu_intr_raise(0);
+       return;
     }
     div = dvd / (u8)s;
     mod = dvd % (u8)s;
     if (abs(div) > 0xff) {
-        x86emu_intr_raise(0);
-        return;
+       x86emu_intr_raise(0);
+       return;
     }
     M.x86.R_AL = (u8)div;
     M.x86.R_AH = (u8)mod;
@@ -2195,14 +2195,14 @@ void div_word(u16 s)
 
     dvd = (((u32)M.x86.R_DX) << 16) | M.x86.R_AX;
     if (s == 0) {
-        x86emu_intr_raise(0);
-        return;
+       x86emu_intr_raise(0);
+       return;
     }
     div = dvd / (u16)s;
     mod = dvd % (u16)s;
     if (abs(div) > 0xffff) {
-        x86emu_intr_raise(0);
-        return;
+       x86emu_intr_raise(0);
+       return;
     }
     CLEAR_FLAG(F_CF);
     CLEAR_FLAG(F_SF);
@@ -2219,19 +2219,19 @@ Implements the DIV instruction and side effects.
 ****************************************************************************/
 void div_long(u32 s)
 {
-#ifdef  __HAS_LONG_LONG__
+#ifdef __HAS_LONG_LONG__
     u64 dvd, div, mod;
 
     dvd = (((u64)M.x86.R_EDX) << 32) | M.x86.R_EAX;
     if (s == 0) {
-        x86emu_intr_raise(0);
-        return;
+       x86emu_intr_raise(0);
+       return;
     }
     div = dvd / (u32)s;
     mod = dvd % (u32)s;
     if (abs(div) > 0xffffffff) {
-        x86emu_intr_raise(0);
-        return;
+       x86emu_intr_raise(0);
+       return;
     }
 #else
     s32 div = 0, mod;
@@ -2244,32 +2244,32 @@ void div_long(u32 s)
     int carry;
 
     if (s == 0) {
-        x86emu_intr_raise(0);
-        return;
+       x86emu_intr_raise(0);
+       return;
     }
     do {
-        div <<= 1;
-        carry = (l_dvd >= l_s) ? 0 : 1;
-
-        if (h_dvd < (h_s + carry)) {
-            h_s >>= 1;
-            l_s = s << (--counter);
-            continue;
-        } else {
-            h_dvd -= (h_s + carry);
-            l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1)
-                : (l_dvd - l_s);
-            h_s >>= 1;
-            l_s = s << (--counter);
-            div |= 1;
-            continue;
-        }
+       div <<= 1;
+       carry = (l_dvd >= l_s) ? 0 : 1;
+
+       if (h_dvd < (h_s + carry)) {
+           h_s >>= 1;
+           l_s = s << (--counter);
+           continue;
+       } else {
+           h_dvd -= (h_s + carry);
+           l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1)
+               : (l_dvd - l_s);
+           h_s >>= 1;
+           l_s = s << (--counter);
+           div |= 1;
+           continue;
+       }
 
     } while (counter > -1);
     /* overflow */
     if (h_dvd || (l_dvd > s)) {
-        x86emu_intr_raise(0);
-        return;
+       x86emu_intr_raise(0);
+       return;
     }
     mod = l_dvd;
 #endif
@@ -2291,11 +2291,11 @@ Implements the IN string instruction and side effects.
 static void single_in(int size)
 {
     if(size == 1)
-        store_data_byte_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inb)(M.x86.R_DX));
+       store_data_byte_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inb)(M.x86.R_DX));
     else if (size == 2)
-        store_data_word_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inw)(M.x86.R_DX));
+       store_data_word_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inw)(M.x86.R_DX));
     else
-        store_data_long_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inl)(M.x86.R_DX));
+       store_data_long_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inl)(M.x86.R_DX));
 }
 
 void ins(int size)
@@ -2303,26 +2303,26 @@ void ins(int size)
     int inc = size;
 
     if (ACCESS_FLAG(F_DF)) {
-        inc = -size;
+       inc = -size;
     }
     if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
-        /* dont care whether REPE or REPNE */
-        /* in until CX is ZERO. */
-        u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ?
-                     M.x86.R_ECX : M.x86.R_CX);
-
-        while (count--) {
-          single_in(size);
-          M.x86.R_DI += inc;
-          }
-        M.x86.R_CX = 0;
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            M.x86.R_ECX = 0;
-        }
-        M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+       /* dont care whether REPE or REPNE */
+       /* in until CX is ZERO. */
+       u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ?
+                    M.x86.R_ECX : M.x86.R_CX);
+
+       while (count--) {
+         single_in(size);
+         M.x86.R_DI += inc;
+         }
+       M.x86.R_CX = 0;
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           M.x86.R_ECX = 0;
+       }
+       M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
     } else {
-        single_in(size);
-        M.x86.R_DI += inc;
+       single_in(size);
+       M.x86.R_DI += inc;
     }
 }
 
@@ -2346,31 +2346,31 @@ void outs(int size)
     int inc = size;
 
     if (ACCESS_FLAG(F_DF)) {
-        inc = -size;
+       inc = -size;
     }
     if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
-        /* dont care whether REPE or REPNE */
-        /* out until CX is ZERO. */
-        u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ?
-                     M.x86.R_ECX : M.x86.R_CX);
-        while (count--) {
-          single_out(size);
-          M.x86.R_SI += inc;
-          }
-        M.x86.R_CX = 0;
-        if (M.x86.mode & SYSMODE_PREFIX_DATA) {
-            M.x86.R_ECX = 0;
-        }
-        M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+       /* dont care whether REPE or REPNE */
+       /* out until CX is ZERO. */
+       u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ?
+                    M.x86.R_ECX : M.x86.R_CX);
+       while (count--) {
+         single_out(size);
+         M.x86.R_SI += inc;
+         }
+       M.x86.R_CX = 0;
+       if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+           M.x86.R_ECX = 0;
+       }
+       M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
     } else {
-        single_out(size);
-        M.x86.R_SI += inc;
+       single_out(size);
+       M.x86.R_SI += inc;
     }
 }
 
 /****************************************************************************
 PARAMETERS:
-addr    - Address to fetch word from
+addr   - Address to fetch word from
 
 REMARKS:
 Fetches a word from emulator memory using an absolute address.
@@ -2443,4 +2443,3 @@ DB( if (CHECK_SP_ACCESS())
     M.x86.R_SP += 4;
     return res;
 }
-
index f4e24a7134b213a8195ebd145fdd3d7600336a8e..3d11b0572b2619ca2de99c47f4cbd076817a25e1 100644 (file)
 #define RADEON_REGSIZE                 0x4000
 
 
-#define MM_INDEX                               0x0000
-#define MM_DATA                                0x0004
-#define BUS_CNTL                               0x0030
-#define HI_STAT                                0x004C
-#define BUS_CNTL1                              0x0034
-#define I2C_CNTL_1                             0x0094
-#define CONFIG_CNTL                            0x00E0
-#define CONFIG_MEMSIZE                         0x00F8
-#define CONFIG_APER_0_BASE                     0x0100
-#define CONFIG_APER_1_BASE                     0x0104
-#define CONFIG_APER_SIZE                       0x0108
-#define CONFIG_REG_1_BASE                      0x010C
-#define CONFIG_REG_APER_SIZE                   0x0110
-#define PAD_AGPINPUT_DELAY                     0x0164
-#define PAD_CTLR_STRENGTH                      0x0168
-#define PAD_CTLR_UPDATE                        0x016C
-#define PAD_CTLR_MISC                          0x0aa0
-#define AGP_CNTL                               0x0174
-#define BM_STATUS                              0x0160
-#define CAP0_TRIG_CNTL                         0x0950
-#define CAP1_TRIG_CNTL                         0x09c0
-#define VIPH_CONTROL                           0x0C40
-#define VENDOR_ID                              0x0F00
-#define DEVICE_ID                              0x0F02
-#define COMMAND                                0x0F04
-#define STATUS                                 0x0F06
-#define REVISION_ID                            0x0F08
-#define REGPROG_INF                            0x0F09
-#define SUB_CLASS                              0x0F0A
-#define BASE_CODE                              0x0F0B
-#define CACHE_LINE                             0x0F0C
-#define LATENCY                                0x0F0D
-#define HEADER                                 0x0F0E
-#define BIST                                   0x0F0F
-#define REG_MEM_BASE                           0x0F10
-#define REG_IO_BASE                            0x0F14
-#define REG_REG_BASE                           0x0F18
-#define ADAPTER_ID                             0x0F2C
-#define BIOS_ROM                               0x0F30
-#define CAPABILITIES_PTR                       0x0F34
-#define INTERRUPT_LINE                         0x0F3C
-#define INTERRUPT_PIN                          0x0F3D
-#define MIN_GRANT                              0x0F3E
-#define MAX_LATENCY                            0x0F3F
-#define ADAPTER_ID_W                           0x0F4C
-#define PMI_CAP_ID                             0x0F50
-#define PMI_NXT_CAP_PTR                        0x0F51
-#define PMI_PMC_REG                            0x0F52
-#define PM_STATUS                              0x0F54
-#define PMI_DATA                               0x0F57
-#define AGP_CAP_ID                             0x0F58
-#define AGP_STATUS                             0x0F5C
-#define AGP_COMMAND                            0x0F60
-#define AIC_CTRL                               0x01D0
-#define AIC_STAT                               0x01D4
-#define AIC_PT_BASE                            0x01D8
-#define AIC_LO_ADDR                            0x01DC
-#define AIC_HI_ADDR                            0x01E0
-#define AIC_TLB_ADDR                           0x01E4
-#define AIC_TLB_DATA                           0x01E8
-#define DAC_CNTL                               0x0058
-#define DAC_CNTL2                              0x007c
-#define CRTC_GEN_CNTL                          0x0050
-#define MEM_CNTL                               0x0140
-#define MC_CNTL                                0x0140
-#define EXT_MEM_CNTL                           0x0144
-#define MC_TIMING_CNTL                         0x0144
-#define MC_AGP_LOCATION                        0x014C
-#define MEM_IO_CNTL_A0                         0x0178
-#define MEM_REFRESH_CNTL                       0x0178
-#define MEM_INIT_LATENCY_TIMER                 0x0154
-#define MC_INIT_GFX_LAT_TIMER                  0x0154
-#define MEM_SDRAM_MODE_REG                     0x0158
-#define AGP_BASE                               0x0170
-#define MEM_IO_CNTL_A1                         0x017C
-#define MC_READ_CNTL_AB                        0x017C
-#define MEM_IO_CNTL_B0                         0x0180
-#define MC_INIT_MISC_LAT_TIMER                 0x0180
-#define MEM_IO_CNTL_B1                         0x0184
-#define MC_IOPAD_CNTL                          0x0184
-#define MC_DEBUG                               0x0188
-#define MC_STATUS                              0x0150
-#define MEM_IO_OE_CNTL                         0x018C
-#define MC_CHIP_IO_OE_CNTL_AB                  0x018C
-#define MC_FB_LOCATION                         0x0148
-//#define MC_FB_LOCATION                         0x0188
-#define HOST_PATH_CNTL                         0x0130
-#define MEM_VGA_WP_SEL                         0x0038
-#define MEM_VGA_RP_SEL                         0x003C
-#define HDP_DEBUG                              0x0138
-#define SW_SEMAPHORE                           0x013C
-#define CRTC2_GEN_CNTL                         0x03f8
-#define CRTC2_DISPLAY_BASE_ADDR                0x033c
-#define SURFACE_CNTL                           0x0B00
-#define SURFACE0_LOWER_BOUND                   0x0B04
-#define SURFACE1_LOWER_BOUND                   0x0B14
-#define SURFACE2_LOWER_BOUND                   0x0B24
-#define SURFACE3_LOWER_BOUND                   0x0B34
-#define SURFACE4_LOWER_BOUND                   0x0B44
-#define SURFACE5_LOWER_BOUND                   0x0B54
-#define SURFACE6_LOWER_BOUND                   0x0B64
-#define SURFACE7_LOWER_BOUND                   0x0B74
-#define SURFACE0_UPPER_BOUND                   0x0B08
-#define SURFACE1_UPPER_BOUND                   0x0B18
-#define SURFACE2_UPPER_BOUND                   0x0B28
-#define SURFACE3_UPPER_BOUND                   0x0B38
-#define SURFACE4_UPPER_BOUND                   0x0B48
-#define SURFACE5_UPPER_BOUND                   0x0B58
-#define SURFACE6_UPPER_BOUND                   0x0B68
-#define SURFACE7_UPPER_BOUND                   0x0B78
-#define SURFACE0_INFO                          0x0B0C
-#define SURFACE1_INFO                          0x0B1C
-#define SURFACE2_INFO                          0x0B2C
-#define SURFACE3_INFO                          0x0B3C
-#define SURFACE4_INFO                          0x0B4C
-#define SURFACE5_INFO                          0x0B5C
-#define SURFACE6_INFO                          0x0B6C
-#define SURFACE7_INFO                          0x0B7C
-#define SURFACE_ACCESS_FLAGS                   0x0BF8
-#define SURFACE_ACCESS_CLR                     0x0BFC
-#define GEN_INT_CNTL                           0x0040
-#define GEN_INT_STATUS                         0x0044
-#define CRTC_EXT_CNTL                          0x0054
-#define RB3D_CNTL                              0x1C3C
-#define WAIT_UNTIL                             0x1720
-#define ISYNC_CNTL                             0x1724
-#define RBBM_GUICNTL                           0x172C
-#define RBBM_STATUS                            0x0E40
-#define RBBM_STATUS_alt_1                      0x1740
-#define RBBM_CNTL                              0x00EC
-#define RBBM_CNTL_alt_1                        0x0E44
-#define RBBM_SOFT_RESET                        0x00F0
-#define RBBM_SOFT_RESET_alt_1                  0x0E48
-#define NQWAIT_UNTIL                           0x0E50
-#define RBBM_DEBUG                             0x0E6C
-#define RBBM_CMDFIFO_ADDR                      0x0E70
-#define RBBM_CMDFIFO_DATAL                     0x0E74
-#define RBBM_CMDFIFO_DATAH                     0x0E78
-#define RBBM_CMDFIFO_STAT                      0x0E7C
-#define CRTC_STATUS                            0x005C
-#define GPIO_VGA_DDC                           0x0060
-#define GPIO_DVI_DDC                           0x0064
-#define GPIO_MONID                             0x0068
-#define GPIO_CRT2_DDC                          0x006c
-#define PALETTE_INDEX                          0x00B0
-#define PALETTE_DATA                           0x00B4
-#define PALETTE_30_DATA                        0x00B8
-#define CRTC_H_TOTAL_DISP                      0x0200
-#define CRTC_H_SYNC_STRT_WID                   0x0204
-#define CRTC_V_TOTAL_DISP                      0x0208
-#define CRTC_V_SYNC_STRT_WID                   0x020C
-#define CRTC_VLINE_CRNT_VLINE                  0x0210
-#define CRTC_CRNT_FRAME                        0x0214
-#define CRTC_GUI_TRIG_VLINE                    0x0218
-#define CRTC_DEBUG                             0x021C
-#define CRTC_OFFSET_RIGHT                      0x0220
-#define CRTC_OFFSET                            0x0224
-#define CRTC_OFFSET_CNTL                       0x0228
-#define CRTC_PITCH                             0x022C
-#define OVR_CLR                                0x0230
-#define OVR_WID_LEFT_RIGHT                     0x0234
-#define OVR_WID_TOP_BOTTOM                     0x0238
-#define DISPLAY_BASE_ADDR                      0x023C
-#define SNAPSHOT_VH_COUNTS                     0x0240
-#define SNAPSHOT_F_COUNT                       0x0244
-#define N_VIF_COUNT                            0x0248
-#define SNAPSHOT_VIF_COUNT                     0x024C
-#define FP_CRTC_H_TOTAL_DISP                   0x0250
-#define FP_CRTC_V_TOTAL_DISP                   0x0254
-#define CRT_CRTC_H_SYNC_STRT_WID               0x0258
-#define CRT_CRTC_V_SYNC_STRT_WID               0x025C
-#define CUR_OFFSET                             0x0260
-#define CUR_HORZ_VERT_POSN                     0x0264
-#define CUR_HORZ_VERT_OFF                      0x0268
-#define CUR_CLR0                               0x026C
-#define CUR_CLR1                               0x0270
-#define FP_HORZ_VERT_ACTIVE                    0x0278
-#define CRTC_MORE_CNTL                         0x027C
-#define CRTC_H_CUTOFF_ACTIVE_EN                (1<<4)
-#define CRTC_V_CUTOFF_ACTIVE_EN                (1<<5)
-#define DAC_EXT_CNTL                           0x0280
-#define FP_GEN_CNTL                            0x0284
-#define FP_HORZ_STRETCH                        0x028C
-#define FP_VERT_STRETCH                        0x0290
-#define FP_H_SYNC_STRT_WID                     0x02C4
-#define FP_V_SYNC_STRT_WID                     0x02C8
-#define AUX_WINDOW_HORZ_CNTL                   0x02D8
-#define AUX_WINDOW_VERT_CNTL                   0x02DC
-//#define DDA_CONFIG                           0x02e0
-//#define DDA_ON_OFF                           0x02e4
-#define DVI_I2C_CNTL_1                         0x02e4
-#define GRPH_BUFFER_CNTL                       0x02F0
-#define GRPH2_BUFFER_CNTL                      0x03F0
-#define VGA_BUFFER_CNTL                        0x02F4
-#define OV0_Y_X_START                          0x0400
-#define OV0_Y_X_END                            0x0404
-#define OV0_PIPELINE_CNTL                      0x0408
-#define OV0_REG_LOAD_CNTL                      0x0410
-#define OV0_SCALE_CNTL                         0x0420
-#define OV0_V_INC                              0x0424
-#define OV0_P1_V_ACCUM_INIT                    0x0428
-#define OV0_P23_V_ACCUM_INIT                   0x042C
-#define OV0_P1_BLANK_LINES_AT_TOP              0x0430
-#define OV0_P23_BLANK_LINES_AT_TOP             0x0434
-#define OV0_BASE_ADDR                          0x043C
-#define OV0_VID_BUF0_BASE_ADRS                 0x0440
-#define OV0_VID_BUF1_BASE_ADRS                 0x0444
-#define OV0_VID_BUF2_BASE_ADRS                 0x0448
-#define OV0_VID_BUF3_BASE_ADRS                 0x044C
-#define OV0_VID_BUF4_BASE_ADRS                 0x0450
-#define OV0_VID_BUF5_BASE_ADRS                 0x0454
-#define OV0_VID_BUF_PITCH0_VALUE               0x0460
-#define OV0_VID_BUF_PITCH1_VALUE               0x0464
-#define OV0_AUTO_FLIP_CNTRL                    0x0470
-#define OV0_DEINTERLACE_PATTERN                0x0474
-#define OV0_SUBMIT_HISTORY                     0x0478
-#define OV0_H_INC                              0x0480
-#define OV0_STEP_BY                            0x0484
-#define OV0_P1_H_ACCUM_INIT                    0x0488
-#define OV0_P23_H_ACCUM_INIT                   0x048C
-#define OV0_P1_X_START_END                     0x0494
-#define OV0_P2_X_START_END                     0x0498
-#define OV0_P3_X_START_END                     0x049C
-#define OV0_FILTER_CNTL                        0x04A0
-#define OV0_FOUR_TAP_COEF_0                    0x04B0
-#define OV0_FOUR_TAP_COEF_1                    0x04B4
-#define OV0_FOUR_TAP_COEF_2                    0x04B8
-#define OV0_FOUR_TAP_COEF_3                    0x04BC
-#define OV0_FOUR_TAP_COEF_4                    0x04C0
-#define OV0_FLAG_CNTRL                         0x04DC
-#define OV0_SLICE_CNTL                         0x04E0
-#define OV0_VID_KEY_CLR_LOW                    0x04E4
-#define OV0_VID_KEY_CLR_HIGH                   0x04E8
-#define OV0_GRPH_KEY_CLR_LOW                   0x04EC
-#define OV0_GRPH_KEY_CLR_HIGH                  0x04F0
-#define OV0_KEY_CNTL                           0x04F4
-#define OV0_TEST                               0x04F8
-#define SUBPIC_CNTL                            0x0540
-#define SUBPIC_DEFCOLCON                       0x0544
-#define SUBPIC_Y_X_START                       0x054C
-#define SUBPIC_Y_X_END                         0x0550
-#define SUBPIC_V_INC                           0x0554
-#define SUBPIC_H_INC                           0x0558
-#define SUBPIC_BUF0_OFFSET                     0x055C
-#define SUBPIC_BUF1_OFFSET                     0x0560
-#define SUBPIC_LC0_OFFSET                      0x0564
-#define SUBPIC_LC1_OFFSET                      0x0568
-#define SUBPIC_PITCH                           0x056C
-#define SUBPIC_BTN_HLI_COLCON                  0x0570
-#define SUBPIC_BTN_HLI_Y_X_START               0x0574
-#define SUBPIC_BTN_HLI_Y_X_END                 0x0578
-#define SUBPIC_PALETTE_INDEX                   0x057C
-#define SUBPIC_PALETTE_DATA                    0x0580
-#define SUBPIC_H_ACCUM_INIT                    0x0584
-#define SUBPIC_V_ACCUM_INIT                    0x0588
-#define DISP_MISC_CNTL                         0x0D00
-#define DAC_MACRO_CNTL                         0x0D04
-#define DISP_PWR_MAN                           0x0D08
-#define DISP_TEST_DEBUG_CNTL                   0x0D10
-#define DISP_HW_DEBUG                          0x0D14
-#define DAC_CRC_SIG1                           0x0D18
-#define DAC_CRC_SIG2                           0x0D1C
-#define OV0_LIN_TRANS_A                        0x0D20
-#define OV0_LIN_TRANS_B                        0x0D24
-#define OV0_LIN_TRANS_C                        0x0D28
-#define OV0_LIN_TRANS_D                        0x0D2C
-#define OV0_LIN_TRANS_E                        0x0D30
-#define OV0_LIN_TRANS_F                        0x0D34
-#define OV0_GAMMA_0_F                          0x0D40
-#define OV0_GAMMA_10_1F                        0x0D44
-#define OV0_GAMMA_20_3F                        0x0D48
-#define OV0_GAMMA_40_7F                        0x0D4C
-#define OV0_GAMMA_380_3BF                      0x0D50
-#define OV0_GAMMA_3C0_3FF                      0x0D54
-#define DISP_MERGE_CNTL                        0x0D60
-#define DISP_OUTPUT_CNTL                       0x0D64
-#define DISP_LIN_TRANS_GRPH_A                  0x0D80
-#define DISP_LIN_TRANS_GRPH_B                  0x0D84
-#define DISP_LIN_TRANS_GRPH_C                  0x0D88
-#define DISP_LIN_TRANS_GRPH_D                  0x0D8C
-#define DISP_LIN_TRANS_GRPH_E                  0x0D90
-#define DISP_LIN_TRANS_GRPH_F                  0x0D94
-#define DISP_LIN_TRANS_VID_A                   0x0D98
-#define DISP_LIN_TRANS_VID_B                   0x0D9C
-#define DISP_LIN_TRANS_VID_C                   0x0DA0
-#define DISP_LIN_TRANS_VID_D                   0x0DA4
-#define DISP_LIN_TRANS_VID_E                   0x0DA8
-#define DISP_LIN_TRANS_VID_F                   0x0DAC
-#define RMX_HORZ_FILTER_0TAP_COEF              0x0DB0
-#define RMX_HORZ_FILTER_1TAP_COEF              0x0DB4
-#define RMX_HORZ_FILTER_2TAP_COEF              0x0DB8
-#define RMX_HORZ_PHASE                         0x0DBC
-#define DAC_EMBEDDED_SYNC_CNTL                 0x0DC0
-#define DAC_BROAD_PULSE                        0x0DC4
-#define DAC_SKEW_CLKS                          0x0DC8
-#define DAC_INCR                               0x0DCC
-#define DAC_NEG_SYNC_LEVEL                     0x0DD0
-#define DAC_POS_SYNC_LEVEL                     0x0DD4
-#define DAC_BLANK_LEVEL                        0x0DD8
-#define CLOCK_CNTL_INDEX                       0x0008
-#define CLOCK_CNTL_DATA                        0x000C
-#define CP_RB_CNTL                             0x0704
-#define CP_RB_BASE                             0x0700
-#define CP_RB_RPTR_ADDR                        0x070C
-#define CP_RB_RPTR                             0x0710
-#define CP_RB_WPTR                             0x0714
-#define CP_RB_WPTR_DELAY                       0x0718
-#define CP_IB_BASE                             0x0738
-#define CP_IB_BUFSZ                            0x073C
-#define SCRATCH_REG0                           0x15E0
-#define GUI_SCRATCH_REG0                       0x15E0
-#define SCRATCH_REG1                           0x15E4
-#define GUI_SCRATCH_REG1                       0x15E4
-#define SCRATCH_REG2                           0x15E8
-#define GUI_SCRATCH_REG2                       0x15E8
-#define SCRATCH_REG3                           0x15EC
-#define GUI_SCRATCH_REG3                       0x15EC
-#define SCRATCH_REG4                           0x15F0
-#define GUI_SCRATCH_REG4                       0x15F0
-#define SCRATCH_REG5                           0x15F4
-#define GUI_SCRATCH_REG5                       0x15F4
-#define SCRATCH_UMSK                           0x0770
-#define SCRATCH_ADDR                           0x0774
-#define DP_BRUSH_FRGD_CLR                      0x147C
-#define DP_BRUSH_BKGD_CLR                      0x1478
-#define DST_LINE_START                         0x1600
-#define DST_LINE_END                           0x1604
-#define SRC_OFFSET                             0x15AC
-#define SRC_PITCH                              0x15B0
-#define SRC_TILE                               0x1704
-#define SRC_PITCH_OFFSET                       0x1428
-#define SRC_X                                  0x1414
-#define SRC_Y                                  0x1418
-#define SRC_X_Y                                0x1590
-#define SRC_Y_X                                0x1434
+#define MM_INDEX                       0x0000
+#define MM_DATA                                0x0004
+#define BUS_CNTL                       0x0030
+#define HI_STAT                                0x004C
+#define BUS_CNTL1                      0x0034
+#define I2C_CNTL_1                     0x0094
+#define CONFIG_CNTL                    0x00E0
+#define CONFIG_MEMSIZE                 0x00F8
+#define CONFIG_APER_0_BASE             0x0100
+#define CONFIG_APER_1_BASE             0x0104
+#define CONFIG_APER_SIZE               0x0108
+#define CONFIG_REG_1_BASE              0x010C
+#define CONFIG_REG_APER_SIZE           0x0110
+#define PAD_AGPINPUT_DELAY             0x0164
+#define PAD_CTLR_STRENGTH              0x0168
+#define PAD_CTLR_UPDATE                        0x016C
+#define PAD_CTLR_MISC                  0x0aa0
+#define AGP_CNTL                       0x0174
+#define BM_STATUS                      0x0160
+#define CAP0_TRIG_CNTL                 0x0950
+#define CAP1_TRIG_CNTL                 0x09c0
+#define VIPH_CONTROL                   0x0C40
+#define VENDOR_ID                      0x0F00
+#define DEVICE_ID                      0x0F02
+#define COMMAND                                0x0F04
+#define STATUS                         0x0F06
+#define REVISION_ID                    0x0F08
+#define REGPROG_INF                    0x0F09
+#define SUB_CLASS                      0x0F0A
+#define BASE_CODE                      0x0F0B
+#define CACHE_LINE                     0x0F0C
+#define LATENCY                                0x0F0D
+#define HEADER                         0x0F0E
+#define BIST                           0x0F0F
+#define REG_MEM_BASE                   0x0F10
+#define REG_IO_BASE                    0x0F14
+#define REG_REG_BASE                   0x0F18
+#define ADAPTER_ID                     0x0F2C
+#define BIOS_ROM                       0x0F30
+#define CAPABILITIES_PTR               0x0F34
+#define INTERRUPT_LINE                 0x0F3C
+#define INTERRUPT_PIN                  0x0F3D
+#define MIN_GRANT                      0x0F3E
+#define MAX_LATENCY                    0x0F3F
+#define ADAPTER_ID_W                   0x0F4C
+#define PMI_CAP_ID                     0x0F50
+#define PMI_NXT_CAP_PTR                        0x0F51
+#define PMI_PMC_REG                    0x0F52
+#define PM_STATUS                      0x0F54
+#define PMI_DATA                       0x0F57
+#define AGP_CAP_ID                     0x0F58
+#define AGP_STATUS                     0x0F5C
+#define AGP_COMMAND                    0x0F60
+#define AIC_CTRL                       0x01D0
+#define AIC_STAT                       0x01D4
+#define AIC_PT_BASE                    0x01D8
+#define AIC_LO_ADDR                    0x01DC
+#define AIC_HI_ADDR                    0x01E0
+#define AIC_TLB_ADDR                   0x01E4
+#define AIC_TLB_DATA                   0x01E8
+#define DAC_CNTL                       0x0058
+#define DAC_CNTL2                      0x007c
+#define CRTC_GEN_CNTL                  0x0050
+#define MEM_CNTL                       0x0140
+#define MC_CNTL                                0x0140
+#define EXT_MEM_CNTL                   0x0144
+#define MC_TIMING_CNTL                 0x0144
+#define MC_AGP_LOCATION                        0x014C
+#define MEM_IO_CNTL_A0                 0x0178
+#define MEM_REFRESH_CNTL               0x0178
+#define MEM_INIT_LATENCY_TIMER         0x0154
+#define MC_INIT_GFX_LAT_TIMER          0x0154
+#define MEM_SDRAM_MODE_REG             0x0158
+#define AGP_BASE                       0x0170
+#define MEM_IO_CNTL_A1                 0x017C
+#define MC_READ_CNTL_AB                        0x017C
+#define MEM_IO_CNTL_B0                 0x0180
+#define MC_INIT_MISC_LAT_TIMER         0x0180
+#define MEM_IO_CNTL_B1                 0x0184
+#define MC_IOPAD_CNTL                  0x0184
+#define MC_DEBUG                       0x0188
+#define MC_STATUS                      0x0150
+#define MEM_IO_OE_CNTL                 0x018C
+#define MC_CHIP_IO_OE_CNTL_AB          0x018C
+#define MC_FB_LOCATION                 0x0148
+/* #define MC_FB_LOCATION              0x0188 */
+#define HOST_PATH_CNTL                 0x0130
+#define MEM_VGA_WP_SEL                 0x0038
+#define MEM_VGA_RP_SEL                 0x003C
+#define HDP_DEBUG                      0x0138
+#define SW_SEMAPHORE                   0x013C
+#define CRTC2_GEN_CNTL                 0x03f8
+#define CRTC2_DISPLAY_BASE_ADDR                0x033c
+#define SURFACE_CNTL                   0x0B00
+#define SURFACE0_LOWER_BOUND           0x0B04
+#define SURFACE1_LOWER_BOUND           0x0B14
+#define SURFACE2_LOWER_BOUND           0x0B24
+#define SURFACE3_LOWER_BOUND           0x0B34
+#define SURFACE4_LOWER_BOUND           0x0B44
+#define SURFACE5_LOWER_BOUND           0x0B54
+#define SURFACE6_LOWER_BOUND           0x0B64
+#define SURFACE7_LOWER_BOUND           0x0B74
+#define SURFACE0_UPPER_BOUND           0x0B08
+#define SURFACE1_UPPER_BOUND           0x0B18
+#define SURFACE2_UPPER_BOUND           0x0B28
+#define SURFACE3_UPPER_BOUND           0x0B38
+#define SURFACE4_UPPER_BOUND           0x0B48
+#define SURFACE5_UPPER_BOUND           0x0B58
+#define SURFACE6_UPPER_BOUND           0x0B68
+#define SURFACE7_UPPER_BOUND           0x0B78
+#define SURFACE0_INFO                  0x0B0C
+#define SURFACE1_INFO                  0x0B1C
+#define SURFACE2_INFO                  0x0B2C
+#define SURFACE3_INFO                  0x0B3C
+#define SURFACE4_INFO                  0x0B4C
+#define SURFACE5_INFO                  0x0B5C
+#define SURFACE6_INFO                  0x0B6C
+#define SURFACE7_INFO                  0x0B7C
+#define SURFACE_ACCESS_FLAGS           0x0BF8
+#define SURFACE_ACCESS_CLR             0x0BFC
+#define GEN_INT_CNTL                   0x0040
+#define GEN_INT_STATUS                 0x0044
+#define CRTC_EXT_CNTL                  0x0054
+#define RB3D_CNTL                      0x1C3C
+#define WAIT_UNTIL                     0x1720
+#define ISYNC_CNTL                     0x1724
+#define RBBM_GUICNTL                   0x172C
+#define RBBM_STATUS                    0x0E40
+#define RBBM_STATUS_alt_1              0x1740
+#define RBBM_CNTL                      0x00EC
+#define RBBM_CNTL_alt_1                        0x0E44
+#define RBBM_SOFT_RESET                        0x00F0
+#define RBBM_SOFT_RESET_alt_1          0x0E48
+#define NQWAIT_UNTIL                   0x0E50
+#define RBBM_DEBUG                     0x0E6C
+#define RBBM_CMDFIFO_ADDR              0x0E70
+#define RBBM_CMDFIFO_DATAL             0x0E74
+#define RBBM_CMDFIFO_DATAH             0x0E78
+#define RBBM_CMDFIFO_STAT              0x0E7C
+#define CRTC_STATUS                    0x005C
+#define GPIO_VGA_DDC                   0x0060
+#define GPIO_DVI_DDC                   0x0064
+#define GPIO_MONID                     0x0068
+#define GPIO_CRT2_DDC                  0x006c
+#define PALETTE_INDEX                  0x00B0
+#define PALETTE_DATA                   0x00B4
+#define PALETTE_30_DATA                        0x00B8
+#define CRTC_H_TOTAL_DISP              0x0200
+#define CRTC_H_SYNC_STRT_WID           0x0204
+#define CRTC_V_TOTAL_DISP              0x0208
+#define CRTC_V_SYNC_STRT_WID           0x020C
+#define CRTC_VLINE_CRNT_VLINE          0x0210
+#define CRTC_CRNT_FRAME                        0x0214
+#define CRTC_GUI_TRIG_VLINE            0x0218
+#define CRTC_DEBUG                     0x021C
+#define CRTC_OFFSET_RIGHT              0x0220
+#define CRTC_OFFSET                    0x0224
+#define CRTC_OFFSET_CNTL               0x0228
+#define CRTC_PITCH                     0x022C
+#define OVR_CLR                                0x0230
+#define OVR_WID_LEFT_RIGHT             0x0234
+#define OVR_WID_TOP_BOTTOM             0x0238
+#define DISPLAY_BASE_ADDR              0x023C
+#define SNAPSHOT_VH_COUNTS             0x0240
+#define SNAPSHOT_F_COUNT               0x0244
+#define N_VIF_COUNT                    0x0248
+#define SNAPSHOT_VIF_COUNT             0x024C
+#define FP_CRTC_H_TOTAL_DISP           0x0250
+#define FP_CRTC_V_TOTAL_DISP           0x0254
+#define CRT_CRTC_H_SYNC_STRT_WID       0x0258
+#define CRT_CRTC_V_SYNC_STRT_WID       0x025C
+#define CUR_OFFSET                     0x0260
+#define CUR_HORZ_VERT_POSN             0x0264
+#define CUR_HORZ_VERT_OFF              0x0268
+#define CUR_CLR0                       0x026C
+#define CUR_CLR1                       0x0270
+#define FP_HORZ_VERT_ACTIVE            0x0278
+#define CRTC_MORE_CNTL                 0x027C
+#define CRTC_H_CUTOFF_ACTIVE_EN                (1<<4)
+#define CRTC_V_CUTOFF_ACTIVE_EN                (1<<5)
+#define DAC_EXT_CNTL                   0x0280
+#define FP_GEN_CNTL                    0x0284
+#define FP_HORZ_STRETCH                        0x028C
+#define FP_VERT_STRETCH                        0x0290
+#define FP_H_SYNC_STRT_WID             0x02C4
+#define FP_V_SYNC_STRT_WID             0x02C8
+#define AUX_WINDOW_HORZ_CNTL           0x02D8
+#define AUX_WINDOW_VERT_CNTL           0x02DC
+/* #define DDA_CONFIG                  0x02e0 */
+/* #define DDA_ON_OFF                  0x02e4 */
+#define DVI_I2C_CNTL_1                 0x02e4
+#define GRPH_BUFFER_CNTL               0x02F0
+#define GRPH2_BUFFER_CNTL              0x03F0
+#define VGA_BUFFER_CNTL                        0x02F4
+#define OV0_Y_X_START                  0x0400
+#define OV0_Y_X_END                    0x0404
+#define OV0_PIPELINE_CNTL              0x0408
+#define OV0_REG_LOAD_CNTL              0x0410
+#define OV0_SCALE_CNTL                 0x0420
+#define OV0_V_INC                      0x0424
+#define OV0_P1_V_ACCUM_INIT            0x0428
+#define OV0_P23_V_ACCUM_INIT           0x042C
+#define OV0_P1_BLANK_LINES_AT_TOP      0x0430
+#define OV0_P23_BLANK_LINES_AT_TOP     0x0434
+#define OV0_BASE_ADDR                  0x043C
+#define OV0_VID_BUF0_BASE_ADRS         0x0440
+#define OV0_VID_BUF1_BASE_ADRS         0x0444
+#define OV0_VID_BUF2_BASE_ADRS         0x0448
+#define OV0_VID_BUF3_BASE_ADRS         0x044C
+#define OV0_VID_BUF4_BASE_ADRS         0x0450
+#define OV0_VID_BUF5_BASE_ADRS         0x0454
+#define OV0_VID_BUF_PITCH0_VALUE       0x0460
+#define OV0_VID_BUF_PITCH1_VALUE       0x0464
+#define OV0_AUTO_FLIP_CNTRL            0x0470
+#define OV0_DEINTERLACE_PATTERN                0x0474
+#define OV0_SUBMIT_HISTORY             0x0478
+#define OV0_H_INC                      0x0480
+#define OV0_STEP_BY                    0x0484
+#define OV0_P1_H_ACCUM_INIT            0x0488
+#define OV0_P23_H_ACCUM_INIT           0x048C
+#define OV0_P1_X_START_END             0x0494
+#define OV0_P2_X_START_END             0x0498
+#define OV0_P3_X_START_END             0x049C
+#define OV0_FILTER_CNTL                        0x04A0
+#define OV0_FOUR_TAP_COEF_0            0x04B0
+#define OV0_FOUR_TAP_COEF_1            0x04B4
+#define OV0_FOUR_TAP_COEF_2            0x04B8
+#define OV0_FOUR_TAP_COEF_3            0x04BC
+#define OV0_FOUR_TAP_COEF_4            0x04C0
+#define OV0_FLAG_CNTRL                 0x04DC
+#define OV0_SLICE_CNTL                 0x04E0
+#define OV0_VID_KEY_CLR_LOW            0x04E4
+#define OV0_VID_KEY_CLR_HIGH           0x04E8
+#define OV0_GRPH_KEY_CLR_LOW           0x04EC
+#define OV0_GRPH_KEY_CLR_HIGH          0x04F0
+#define OV0_KEY_CNTL                   0x04F4
+#define OV0_TEST                       0x04F8
+#define SUBPIC_CNTL                    0x0540
+#define SUBPIC_DEFCOLCON               0x0544
+#define SUBPIC_Y_X_START               0x054C
+#define SUBPIC_Y_X_END                 0x0550
+#define SUBPIC_V_INC                   0x0554
+#define SUBPIC_H_INC                   0x0558
+#define SUBPIC_BUF0_OFFSET             0x055C
+#define SUBPIC_BUF1_OFFSET             0x0560
+#define SUBPIC_LC0_OFFSET              0x0564
+#define SUBPIC_LC1_OFFSET              0x0568
+#define SUBPIC_PITCH                   0x056C
+#define SUBPIC_BTN_HLI_COLCON          0x0570
+#define SUBPIC_BTN_HLI_Y_X_START       0x0574
+#define SUBPIC_BTN_HLI_Y_X_END         0x0578
+#define SUBPIC_PALETTE_INDEX           0x057C
+#define SUBPIC_PALETTE_DATA            0x0580
+#define SUBPIC_H_ACCUM_INIT            0x0584
+#define SUBPIC_V_ACCUM_INIT            0x0588
+#define DISP_MISC_CNTL                 0x0D00
+#define DAC_MACRO_CNTL                 0x0D04
+#define DISP_PWR_MAN                   0x0D08
+#define DISP_TEST_DEBUG_CNTL           0x0D10
+#define DISP_HW_DEBUG                  0x0D14
+#define DAC_CRC_SIG1                   0x0D18
+#define DAC_CRC_SIG2                   0x0D1C
+#define OV0_LIN_TRANS_A                        0x0D20
+#define OV0_LIN_TRANS_B                        0x0D24
+#define OV0_LIN_TRANS_C                        0x0D28
+#define OV0_LIN_TRANS_D                        0x0D2C
+#define OV0_LIN_TRANS_E                        0x0D30
+#define OV0_LIN_TRANS_F                        0x0D34
+#define OV0_GAMMA_0_F                  0x0D40
+#define OV0_GAMMA_10_1F                        0x0D44
+#define OV0_GAMMA_20_3F                        0x0D48
+#define OV0_GAMMA_40_7F                        0x0D4C
+#define OV0_GAMMA_380_3BF              0x0D50
+#define OV0_GAMMA_3C0_3FF              0x0D54
+#define DISP_MERGE_CNTL                        0x0D60
+#define DISP_OUTPUT_CNTL               0x0D64
+#define DISP_LIN_TRANS_GRPH_A          0x0D80
+#define DISP_LIN_TRANS_GRPH_B          0x0D84
+#define DISP_LIN_TRANS_GRPH_C          0x0D88
+#define DISP_LIN_TRANS_GRPH_D          0x0D8C
+#define DISP_LIN_TRANS_GRPH_E          0x0D90
+#define DISP_LIN_TRANS_GRPH_F          0x0D94
+#define DISP_LIN_TRANS_VID_A           0x0D98
+#define DISP_LIN_TRANS_VID_B           0x0D9C
+#define DISP_LIN_TRANS_VID_C           0x0DA0
+#define DISP_LIN_TRANS_VID_D           0x0DA4
+#define DISP_LIN_TRANS_VID_E           0x0DA8
+#define DISP_LIN_TRANS_VID_F           0x0DAC
+#define RMX_HORZ_FILTER_0TAP_COEF      0x0DB0
+#define RMX_HORZ_FILTER_1TAP_COEF      0x0DB4
+#define RMX_HORZ_FILTER_2TAP_COEF      0x0DB8
+#define RMX_HORZ_PHASE                 0x0DBC
+#define DAC_EMBEDDED_SYNC_CNTL         0x0DC0
+#define DAC_BROAD_PULSE                        0x0DC4
+#define DAC_SKEW_CLKS                  0x0DC8
+#define DAC_INCR                       0x0DCC
+#define DAC_NEG_SYNC_LEVEL             0x0DD0
+#define DAC_POS_SYNC_LEVEL             0x0DD4
+#define DAC_BLANK_LEVEL                        0x0DD8
+#define CLOCK_CNTL_INDEX               0x0008
+#define CLOCK_CNTL_DATA                        0x000C
+#define CP_RB_CNTL                     0x0704
+#define CP_RB_BASE                     0x0700
+#define CP_RB_RPTR_ADDR                        0x070C
+#define CP_RB_RPTR                     0x0710
+#define CP_RB_WPTR                     0x0714
+#define CP_RB_WPTR_DELAY               0x0718
+#define CP_IB_BASE                     0x0738
+#define CP_IB_BUFSZ                    0x073C
+#define SCRATCH_REG0                   0x15E0
+#define GUI_SCRATCH_REG0               0x15E0
+#define SCRATCH_REG1                   0x15E4
+#define GUI_SCRATCH_REG1               0x15E4
+#define SCRATCH_REG2                   0x15E8
+#define GUI_SCRATCH_REG2               0x15E8
+#define SCRATCH_REG3                   0x15EC
+#define GUI_SCRATCH_REG3               0x15EC
+#define SCRATCH_REG4                   0x15F0
+#define GUI_SCRATCH_REG4               0x15F0
+#define SCRATCH_REG5                   0x15F4
+#define GUI_SCRATCH_REG5               0x15F4
+#define SCRATCH_UMSK                   0x0770
+#define SCRATCH_ADDR                   0x0774
+#define DP_BRUSH_FRGD_CLR              0x147C
+#define DP_BRUSH_BKGD_CLR              0x1478
+#define DST_LINE_START                 0x1600
+#define DST_LINE_END                   0x1604
+#define SRC_OFFSET                     0x15AC
+#define SRC_PITCH                      0x15B0
+#define SRC_TILE                       0x1704
+#define SRC_PITCH_OFFSET               0x1428
+#define SRC_X                          0x1414
+#define SRC_Y                          0x1418
+#define SRC_X_Y                                0x1590
+#define SRC_Y_X                                0x1434
 #define DST_Y_X                                0x1438
-#define DST_WIDTH_HEIGHT                       0x1598
-#define DST_HEIGHT_WIDTH                       0x143c
-#define DST_OFFSET                             0x1404
-#define SRC_CLUT_ADDRESS                       0x1780
-#define SRC_CLUT_DATA                          0x1784
-#define SRC_CLUT_DATA_RD                       0x1788
-#define HOST_DATA0                             0x17C0
-#define HOST_DATA1                             0x17C4
-#define HOST_DATA2                             0x17C8
-#define HOST_DATA3                             0x17CC
-#define HOST_DATA4                             0x17D0
-#define HOST_DATA5                             0x17D4
-#define HOST_DATA6                             0x17D8
-#define HOST_DATA7                             0x17DC
-#define HOST_DATA_LAST                         0x17E0
-#define DP_SRC_ENDIAN                          0x15D4
-#define DP_SRC_FRGD_CLR                        0x15D8
-#define DP_SRC_BKGD_CLR                        0x15DC
-#define SC_LEFT                                0x1640
-#define SC_RIGHT                               0x1644
-#define SC_TOP                                 0x1648
-#define SC_BOTTOM                              0x164C
-#define SRC_SC_RIGHT                           0x1654
-#define SRC_SC_BOTTOM                          0x165C
-#define DP_CNTL                                0x16C0
-#define DP_CNTL_XDIR_YDIR_YMAJOR               0x16D0
-#define DP_DATATYPE                            0x16C4
-#define DP_MIX                                 0x16C8
-#define DP_WRITE_MSK                           0x16CC
-#define DP_XOP                                 0x17F8
-#define CLR_CMP_CLR_SRC                        0x15C4
-#define CLR_CMP_CLR_DST                        0x15C8
-#define CLR_CMP_CNTL                           0x15C0
-#define CLR_CMP_MSK                            0x15CC
-#define DSTCACHE_MODE                          0x1710
-#define DSTCACHE_CTLSTAT                       0x1714
-#define DEFAULT_PITCH_OFFSET                   0x16E0
-#define DEFAULT_SC_BOTTOM_RIGHT                0x16E8
-#define DEFAULT_SC_TOP_LEFT                    0x16EC
-#define SRC_PITCH_OFFSET                       0x1428
-#define DST_PITCH_OFFSET                       0x142C
-#define DP_GUI_MASTER_CNTL                     0x146C
-#define SC_TOP_LEFT                            0x16EC
-#define SC_BOTTOM_RIGHT                        0x16F0
-#define SRC_SC_BOTTOM_RIGHT                    0x16F4
-#define RB2D_DSTCACHE_MODE                     0x3428
-#define RB2D_DSTCACHE_CTLSTAT                  0x342C
-#define LVDS_GEN_CNTL                          0x02d0
-#define LVDS_PLL_CNTL                          0x02d4
-#define FP2_GEN_CNTL                           0x0288
-#define TMDS_CNTL                              0x0294
-#define TMDS_CRC                               0x02a0
-#define TMDS_TRANSMITTER_CNTL                  0x02a4
-#define MPP_TB_CONFIG                          0x01c0
-#define PAMAC0_DLY_CNTL                        0x0a94
-#define PAMAC1_DLY_CNTL                        0x0a98
-#define PAMAC2_DLY_CNTL                        0x0a9c
-#define FW_CNTL                                0x0118
-#define FCP_CNTL                               0x0910
-#define VGA_DDA_ON_OFF                         0x02ec
-#define TV_MASTER_CNTL                         0x0800
-
-//#define BASE_CODE                           0x0f0b
-#define BIOS_0_SCRATCH                        0x0010
-#define BIOS_1_SCRATCH                        0x0014
-#define BIOS_2_SCRATCH                        0x0018
-#define BIOS_3_SCRATCH                        0x001c
-#define BIOS_4_SCRATCH                        0x0020
-#define BIOS_5_SCRATCH                        0x0024
-#define BIOS_6_SCRATCH                        0x0028
-#define BIOS_7_SCRATCH                        0x002c
-
-#define HDP_SOFT_RESET                         (1 << 26)
-
-#define TV_DAC_CNTL                            0x088c
-#define GPIOPAD_MASK                           0x0198
-#define GPIOPAD_A                              0x019c
-#define GPIOPAD_EN                             0x01a0
-#define GPIOPAD_Y                              0x01a4
-#define ZV_LCDPAD_MASK                         0x01a8
-#define ZV_LCDPAD_A                            0x01ac
-#define ZV_LCDPAD_EN                           0x01b0
-#define ZV_LCDPAD_Y                            0x01b4
+#define DST_WIDTH_HEIGHT               0x1598
+#define DST_HEIGHT_WIDTH               0x143c
+#define DST_OFFSET                     0x1404
+#define SRC_CLUT_ADDRESS               0x1780
+#define SRC_CLUT_DATA                  0x1784
+#define SRC_CLUT_DATA_RD               0x1788
+#define HOST_DATA0                     0x17C0
+#define HOST_DATA1                     0x17C4
+#define HOST_DATA2                     0x17C8
+#define HOST_DATA3                     0x17CC
+#define HOST_DATA4                     0x17D0
+#define HOST_DATA5                     0x17D4
+#define HOST_DATA6                     0x17D8
+#define HOST_DATA7                     0x17DC
+#define HOST_DATA_LAST                 0x17E0
+#define DP_SRC_ENDIAN                  0x15D4
+#define DP_SRC_FRGD_CLR                        0x15D8
+#define DP_SRC_BKGD_CLR                        0x15DC
+#define SC_LEFT                                0x1640
+#define SC_RIGHT                       0x1644
+#define SC_TOP                         0x1648
+#define SC_BOTTOM                      0x164C
+#define SRC_SC_RIGHT                   0x1654
+#define SRC_SC_BOTTOM                  0x165C
+#define DP_CNTL                                0x16C0
+#define DP_CNTL_XDIR_YDIR_YMAJOR       0x16D0
+#define DP_DATATYPE                    0x16C4
+#define DP_MIX                         0x16C8
+#define DP_WRITE_MSK                   0x16CC
+#define DP_XOP                         0x17F8
+#define CLR_CMP_CLR_SRC                        0x15C4
+#define CLR_CMP_CLR_DST                        0x15C8
+#define CLR_CMP_CNTL                   0x15C0
+#define CLR_CMP_MSK                    0x15CC
+#define DSTCACHE_MODE                  0x1710
+#define DSTCACHE_CTLSTAT               0x1714
+#define DEFAULT_PITCH_OFFSET           0x16E0
+#define DEFAULT_SC_BOTTOM_RIGHT                0x16E8
+#define DEFAULT_SC_TOP_LEFT            0x16EC
+#define SRC_PITCH_OFFSET               0x1428
+#define DST_PITCH_OFFSET               0x142C
+#define DP_GUI_MASTER_CNTL             0x146C
+#define SC_TOP_LEFT                    0x16EC
+#define SC_BOTTOM_RIGHT                        0x16F0
+#define SRC_SC_BOTTOM_RIGHT            0x16F4
+#define RB2D_DSTCACHE_MODE             0x3428
+#define RB2D_DSTCACHE_CTLSTAT          0x342C
+#define LVDS_GEN_CNTL                  0x02d0
+#define LVDS_PLL_CNTL                  0x02d4
+#define FP2_GEN_CNTL                   0x0288
+#define TMDS_CNTL                      0x0294
+#define TMDS_CRC                       0x02a0
+#define TMDS_TRANSMITTER_CNTL          0x02a4
+#define MPP_TB_CONFIG                  0x01c0
+#define PAMAC0_DLY_CNTL                        0x0a94
+#define PAMAC1_DLY_CNTL                        0x0a98
+#define PAMAC2_DLY_CNTL                        0x0a9c
+#define FW_CNTL                                0x0118
+#define FCP_CNTL                       0x0910
+#define VGA_DDA_ON_OFF                 0x02ec
+#define TV_MASTER_CNTL                 0x0800
+
+/* #define BASE_CODE                   0x0f0b */
+#define BIOS_0_SCRATCH                 0x0010
+#define BIOS_1_SCRATCH                 0x0014
+#define BIOS_2_SCRATCH                 0x0018
+#define BIOS_3_SCRATCH                 0x001c
+#define BIOS_4_SCRATCH                 0x0020
+#define BIOS_5_SCRATCH                 0x0024
+#define BIOS_6_SCRATCH                 0x0028
+#define BIOS_7_SCRATCH                 0x002c
+
+#define HDP_SOFT_RESET                 (1 << 26)
+
+#define TV_DAC_CNTL                    0x088c
+#define GPIOPAD_MASK                   0x0198
+#define GPIOPAD_A                      0x019c
+#define GPIOPAD_EN                     0x01a0
+#define GPIOPAD_Y                      0x01a4
+#define ZV_LCDPAD_MASK                 0x01a8
+#define ZV_LCDPAD_A                    0x01ac
+#define ZV_LCDPAD_EN                   0x01b0
+#define ZV_LCDPAD_Y                    0x01b4
 
 /* PLL Registers */
-#define CLK_PIN_CNTL                               0x0001
-#define PPLL_CNTL                                  0x0002
-#define PPLL_REF_DIV                               0x0003
-#define PPLL_DIV_0                                 0x0004
-#define PPLL_DIV_1                                 0x0005
-#define PPLL_DIV_2                                 0x0006
-#define PPLL_DIV_3                                 0x0007
-#define VCLK_ECP_CNTL                              0x0008
-#define HTOTAL_CNTL                                0x0009
-#define M_SPLL_REF_FB_DIV                          0x000a
-#define AGP_PLL_CNTL                               0x000b
-#define SPLL_CNTL                                  0x000c
-#define SCLK_CNTL                                  0x000d
-#define MPLL_CNTL                                  0x000e
-#define MDLL_CKO                                   0x000f
-#define MDLL_RDCKA                                 0x0010
-#define MCLK_CNTL                                  0x0012
-#define AGP_PLL_CNTL                               0x000b
-#define PLL_TEST_CNTL                              0x0013
-#define CLK_PWRMGT_CNTL                            0x0014
-#define PLL_PWRMGT_CNTL                            0x0015
-#define MCLK_MISC                                  0x001f
-#define P2PLL_CNTL                                 0x002a
-#define P2PLL_REF_DIV                              0x002b
-#define PIXCLKS_CNTL                               0x002d
-#define SCLK_MORE_CNTL                             0x0035
+#define CLK_PIN_CNTL                   0x0001
+#define PPLL_CNTL                      0x0002
+#define PPLL_REF_DIV                   0x0003
+#define PPLL_DIV_0                     0x0004
+#define PPLL_DIV_1                     0x0005
+#define PPLL_DIV_2                     0x0006
+#define PPLL_DIV_3                     0x0007
+#define VCLK_ECP_CNTL                  0x0008
+#define HTOTAL_CNTL                    0x0009
+#define M_SPLL_REF_FB_DIV              0x000a
+#define AGP_PLL_CNTL                   0x000b
+#define SPLL_CNTL                      0x000c
+#define SCLK_CNTL                      0x000d
+#define MPLL_CNTL                      0x000e
+#define MDLL_CKO                       0x000f
+#define MDLL_RDCKA                     0x0010
+#define MCLK_CNTL                      0x0012
+#define AGP_PLL_CNTL                   0x000b
+#define PLL_TEST_CNTL                  0x0013
+#define CLK_PWRMGT_CNTL                        0x0014
+#define PLL_PWRMGT_CNTL                        0x0015
+#define MCLK_MISC                      0x001f
+#define P2PLL_CNTL                     0x002a
+#define P2PLL_REF_DIV                  0x002b
+#define PIXCLKS_CNTL                   0x002d
+#define SCLK_MORE_CNTL                 0x0035
 
 /* MCLK_CNTL bit constants */
-#define FORCEON_MCLKA                             (1 << 16)
-#define FORCEON_MCLKB                             (1 << 17)
-#define FORCEON_YCLKA                             (1 << 18)
-#define FORCEON_YCLKB                             (1 << 19)
-#define FORCEON_MC                                (1 << 20)
-#define FORCEON_AIC                               (1 << 21)
+#define FORCEON_MCLKA                  (1 << 16)
+#define FORCEON_MCLKB                  (1 << 17)
+#define FORCEON_YCLKA                  (1 << 18)
+#define FORCEON_YCLKB                  (1 << 19)
+#define FORCEON_MC                     (1 << 20)
+#define FORCEON_AIC                    (1 << 21)
 
 /* SCLK_CNTL bit constants */
-#define DYN_STOP_LAT_MASK                         0x00007ff8
-#define CP_MAX_DYN_STOP_LAT                       0x0008
-#define SCLK_FORCEON_MASK                         0xffff8000
+#define DYN_STOP_LAT_MASK              0x00007ff8
+#define CP_MAX_DYN_STOP_LAT            0x0008
+#define SCLK_FORCEON_MASK              0xffff8000
 
 /* SCLK_MORE_CNTL bit constants */
-#define SCLK_MORE_FORCEON                         0x0700
+#define SCLK_MORE_FORCEON              0x0700
 
 /* BUS_CNTL bit constants */
-#define BUS_DBL_RESYNC                             0x00000001
-#define BUS_MSTR_RESET                             0x00000002
-#define BUS_FLUSH_BUF                              0x00000004
-#define BUS_STOP_REQ_DIS                           0x00000008
-#define BUS_ROTATION_DIS                           0x00000010
-#define BUS_MASTER_DIS                             0x00000040
-#define BUS_ROM_WRT_EN                             0x00000080
-#define BUS_DIS_ROM                                0x00001000
-#define BUS_PCI_READ_RETRY_EN                      0x00002000
-#define BUS_AGP_AD_STEPPING_EN                     0x00004000
-#define BUS_PCI_WRT_RETRY_EN                       0x00008000
-#define BUS_MSTR_RD_MULT                           0x00100000
-#define BUS_MSTR_RD_LINE                           0x00200000
-#define BUS_SUSPEND                                0x00400000
-#define LAT_16X                                    0x00800000
-#define BUS_RD_DISCARD_EN                          0x01000000
-#define BUS_RD_ABORT_EN                            0x02000000
-#define BUS_MSTR_WS                                0x04000000
-#define BUS_PARKING_DIS                            0x08000000
-#define BUS_MSTR_DISCONNECT_EN                     0x10000000
-#define BUS_WRT_BURST                              0x20000000
-#define BUS_READ_BURST                             0x40000000
-#define BUS_RDY_READ_DLY                           0x80000000
+#define BUS_DBL_RESYNC                 0x00000001
+#define BUS_MSTR_RESET                 0x00000002
+#define BUS_FLUSH_BUF                  0x00000004
+#define BUS_STOP_REQ_DIS               0x00000008
+#define BUS_ROTATION_DIS               0x00000010
+#define BUS_MASTER_DIS                 0x00000040
+#define BUS_ROM_WRT_EN                 0x00000080
+#define BUS_DIS_ROM                    0x00001000
+#define BUS_PCI_READ_RETRY_EN          0x00002000
+#define BUS_AGP_AD_STEPPING_EN         0x00004000
+#define BUS_PCI_WRT_RETRY_EN           0x00008000
+#define BUS_MSTR_RD_MULT               0x00100000
+#define BUS_MSTR_RD_LINE               0x00200000
+#define BUS_SUSPEND                    0x00400000
+#define LAT_16X                                0x00800000
+#define BUS_RD_DISCARD_EN              0x01000000
+#define BUS_RD_ABORT_EN                        0x02000000
+#define BUS_MSTR_WS                    0x04000000
+#define BUS_PARKING_DIS                        0x08000000
+#define BUS_MSTR_DISCONNECT_EN         0x10000000
+#define BUS_WRT_BURST                  0x20000000
+#define BUS_READ_BURST                 0x40000000
+#define BUS_RDY_READ_DLY               0x80000000
 
 /* PIXCLKS_CNTL */
-#define PIX2CLK_SRC_SEL_MASK                       0x03
-#define PIX2CLK_SRC_SEL_CPUCLK                     0x00
-#define PIX2CLK_SRC_SEL_PSCANCLK                   0x01
-#define PIX2CLK_SRC_SEL_BYTECLK                    0x02
-#define PIX2CLK_SRC_SEL_P2PLLCLK                   0x03
-#define PIX2CLK_ALWAYS_ONb                         (1<<6)
-#define PIX2CLK_DAC_ALWAYS_ONb                     (1<<7)
-#define PIXCLK_TV_SRC_SEL                          (1 << 8)
-#define PIXCLK_LVDS_ALWAYS_ONb                     (1 << 14)
-#define PIXCLK_TMDS_ALWAYS_ONb                     (1 << 15)
+#define PIX2CLK_SRC_SEL_MASK           0x03
+#define PIX2CLK_SRC_SEL_CPUCLK         0x00
+#define PIX2CLK_SRC_SEL_PSCANCLK       0x01
+#define PIX2CLK_SRC_SEL_BYTECLK                0x02
+#define PIX2CLK_SRC_SEL_P2PLLCLK       0x03
+#define PIX2CLK_ALWAYS_ONb             (1<<6)
+#define PIX2CLK_DAC_ALWAYS_ONb         (1<<7)
+#define PIXCLK_TV_SRC_SEL              (1 << 8)
+#define PIXCLK_LVDS_ALWAYS_ONb         (1 << 14)
+#define PIXCLK_TMDS_ALWAYS_ONb         (1 << 15)
 
 
 /* CLOCK_CNTL_INDEX bit constants */
-#define PLL_WR_EN                                  0x00000080
+#define PLL_WR_EN                      0x00000080
 
 /* CONFIG_CNTL bit constants */
-#define CFG_VGA_RAM_EN                             0x00000100
-#define CFG_ATI_REV_ID_MASK                       (0xf << 16)
-#define CFG_ATI_REV_A11                                   (0 << 16)
-#define CFG_ATI_REV_A12                                   (1 << 16)
-#define CFG_ATI_REV_A13                                   (2 << 16)
+#define CFG_VGA_RAM_EN                 0x00000100
+#define CFG_ATI_REV_ID_MASK            (0xf << 16)
+#define CFG_ATI_REV_A11                        (0 << 16)
+#define CFG_ATI_REV_A12                        (1 << 16)
+#define CFG_ATI_REV_A13                        (2 << 16)
 
 /* CRTC_EXT_CNTL bit constants */
-#define VGA_ATI_LINEAR                             0x00000008
-#define VGA_128KAP_PAGING                          0x00000010
-#define        XCRT_CNT_EN                                (1 << 6)
-#define CRTC_HSYNC_DIS                            (1 << 8)
-#define CRTC_VSYNC_DIS                            (1 << 9)
-#define CRTC_DISPLAY_DIS                          (1 << 10)
-#define CRTC_CRT_ON                               (1 << 15)
+#define VGA_ATI_LINEAR                 0x00000008
+#define VGA_128KAP_PAGING              0x00000010
+#define XCRT_CNT_EN                    (1 << 6)
+#define CRTC_HSYNC_DIS                 (1 << 8)
+#define CRTC_VSYNC_DIS                 (1 << 9)
+#define CRTC_DISPLAY_DIS               (1 << 10)
+#define CRTC_CRT_ON                    (1 << 15)
 
 
 /* DSTCACHE_CTLSTAT bit constants */
-#define RB2D_DC_FLUSH                             (3 << 0)
-#define RB2D_DC_FLUSH_ALL                         0xf
-#define RB2D_DC_BUSY                              (1 << 31)
+#define RB2D_DC_FLUSH                  (3 << 0)
+#define RB2D_DC_FLUSH_ALL              0xf
+#define RB2D_DC_BUSY                   (1 << 31)
 
 
 /* CRTC_GEN_CNTL bit constants */
-#define CRTC_DBL_SCAN_EN                           0x00000001
-#define CRTC_CUR_EN                                0x00010000
-#define CRTC_INTERLACE_EN                         (1 << 1)
-#define CRTC_BYPASS_LUT_EN                                (1 << 14)
-#define CRTC_EXT_DISP_EN                          (1 << 24)
-#define CRTC_EN                                           (1 << 25)
-#define CRTC_DISP_REQ_EN_B                         (1 << 26)
+#define CRTC_DBL_SCAN_EN               0x00000001
+#define CRTC_CUR_EN                    0x00010000
+#define CRTC_INTERLACE_EN              (1 << 1)
+#define CRTC_BYPASS_LUT_EN             (1 << 14)
+#define CRTC_EXT_DISP_EN               (1 << 24)
+#define CRTC_EN                                (1 << 25)
+#define CRTC_DISP_REQ_EN_B             (1 << 26)
 
 /* CRTC_STATUS bit constants */
-#define CRTC_VBLANK                                0x00000001
+#define CRTC_VBLANK                    0x00000001
 
 /* CRTC2_GEN_CNTL bit constants */
-#define CRT2_ON                                    (1 << 7)
-#define CRTC2_DISPLAY_DIS                          (1 << 23)
-#define CRTC2_EN                                   (1 << 25)
-#define CRTC2_DISP_REQ_EN_B                        (1 << 26)
+#define CRT2_ON                                (1 << 7)
+#define CRTC2_DISPLAY_DIS              (1 << 23)
+#define CRTC2_EN                       (1 << 25)
+#define CRTC2_DISP_REQ_EN_B            (1 << 26)
 
 /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
-#define CUR_LOCK                                   0x80000000
+#define CUR_LOCK                       0x80000000
 
 /* GPIO bit constants */
-#define GPIO_A_0               (1 <<  0)
-#define GPIO_A_1               (1 <<  1)
-#define GPIO_Y_0               (1 <<  8)
-#define GPIO_Y_1               (1 <<  9)
-#define GPIO_EN_0              (1 << 16)
-#define GPIO_EN_1              (1 << 17)
-#define GPIO_MASK_0            (1 << 24)
-#define GPIO_MASK_1            (1 << 25)
-#define VGA_DDC_DATA_OUTPUT    GPIO_A_0
-#define VGA_DDC_CLK_OUTPUT     GPIO_A_1
-#define VGA_DDC_DATA_INPUT     GPIO_Y_0
-#define VGA_DDC_CLK_INPUT      GPIO_Y_1
-#define VGA_DDC_DATA_OUT_EN    GPIO_EN_0
-#define VGA_DDC_CLK_OUT_EN     GPIO_EN_1
+#define GPIO_A_0                       (1 <<  0)
+#define GPIO_A_1                       (1 <<  1)
+#define GPIO_Y_0                       (1 <<  8)
+#define GPIO_Y_1                       (1 <<  9)
+#define GPIO_EN_0                      (1 << 16)
+#define GPIO_EN_1                      (1 << 17)
+#define GPIO_MASK_0                    (1 << 24)
+#define GPIO_MASK_1                    (1 << 25)
+#define VGA_DDC_DATA_OUTPUT            GPIO_A_0
+#define VGA_DDC_CLK_OUTPUT             GPIO_A_1
+#define VGA_DDC_DATA_INPUT             GPIO_Y_0
+#define VGA_DDC_CLK_INPUT              GPIO_Y_1
+#define VGA_DDC_DATA_OUT_EN            GPIO_EN_0
+#define VGA_DDC_CLK_OUT_EN             GPIO_EN_1
 
 
 /* FP bit constants */
-#define FP_CRTC_H_TOTAL_MASK                      0x000003ff
-#define FP_CRTC_H_DISP_MASK                       0x01ff0000
-#define FP_CRTC_V_TOTAL_MASK                      0x00000fff
-#define FP_CRTC_V_DISP_MASK                       0x0fff0000
-#define FP_H_SYNC_STRT_CHAR_MASK                  0x00001ff8
-#define FP_H_SYNC_WID_MASK                        0x003f0000
-#define FP_V_SYNC_STRT_MASK                       0x00000fff
-#define FP_V_SYNC_WID_MASK                        0x001f0000
-#define FP_CRTC_H_TOTAL_SHIFT                     0x00000000
-#define FP_CRTC_H_DISP_SHIFT                      0x00000010
-#define FP_CRTC_V_TOTAL_SHIFT                     0x00000000
-#define FP_CRTC_V_DISP_SHIFT                      0x00000010
-#define FP_H_SYNC_STRT_CHAR_SHIFT                 0x00000003
-#define FP_H_SYNC_WID_SHIFT                       0x00000010
-#define FP_V_SYNC_STRT_SHIFT                      0x00000000
-#define FP_V_SYNC_WID_SHIFT                       0x00000010
+#define FP_CRTC_H_TOTAL_MASK           000003ff
+#define FP_CRTC_H_DISP_MASK            0x01ff0000
+#define FP_CRTC_V_TOTAL_MASK           0x00000fff
+#define FP_CRTC_V_DISP_MASK            0x0fff0000
+#define FP_H_SYNC_STRT_CHAR_MASK       0x00001ff8
+#define FP_H_SYNC_WID_MASK             0x003f0000
+#define FP_V_SYNC_STRT_MASK            0x00000fff
+#define FP_V_SYNC_WID_MASK             0x001f0000
+#define FP_CRTC_H_TOTAL_SHIFT          0x00000000
+#define FP_CRTC_H_DISP_SHIFT           0x00000010
+#define FP_CRTC_V_TOTAL_SHIFT          0x00000000
+#define FP_CRTC_V_DISP_SHIFT           0x00000010
+#define FP_H_SYNC_STRT_CHAR_SHIFT      0x00000003
+#define FP_H_SYNC_WID_SHIFT            0x00000010
+#define FP_V_SYNC_STRT_SHIFT           0x00000000
+#define FP_V_SYNC_WID_SHIFT            0x00000010
 
 /* FP_GEN_CNTL bit constants */
-#define FP_FPON                                           (1 << 0)
-#define FP_TMDS_EN                                (1 << 2)
-#define FP_PANEL_FORMAT                            (1 << 3)
-#define FP_EN_TMDS                                (1 << 7)
-#define FP_DETECT_SENSE                                   (1 << 8)
-#define R200_FP_SOURCE_SEL_MASK                    (3 << 10)
-#define R200_FP_SOURCE_SEL_CRTC1                   (0 << 10)
-#define R200_FP_SOURCE_SEL_CRTC2                   (1 << 10)
-#define R200_FP_SOURCE_SEL_RMX                     (2 << 10)
-#define R200_FP_SOURCE_SEL_TRANS                   (3 << 10)
-#define FP_SEL_CRTC1                              (0 << 13)
-#define FP_SEL_CRTC2                              (1 << 13)
-#define FP_USE_VGA_HSYNC                           (1 << 14)
-#define FP_CRTC_DONT_SHADOW_HPAR                  (1 << 15)
-#define FP_CRTC_DONT_SHADOW_VPAR                  (1 << 16)
-#define FP_CRTC_DONT_SHADOW_HEND                  (1 << 17)
-#define FP_CRTC_USE_SHADOW_VEND                           (1 << 18)
-#define FP_RMX_HVSYNC_CONTROL_EN                  (1 << 20)
-#define FP_DFP_SYNC_SEL                                   (1 << 21)
-#define FP_CRTC_LOCK_8DOT                         (1 << 22)
-#define FP_CRT_SYNC_SEL                                   (1 << 23)
-#define FP_USE_SHADOW_EN                          (1 << 24)
-#define FP_CRT_SYNC_ALT                                   (1 << 26)
+#define FP_FPON                                (1 << 0)
+#define FP_TMDS_EN                     (1 << 2)
+#define FP_PANEL_FORMAT                        (1 << 3)
+#define FP_EN_TMDS                     (1 << 7)
+#define FP_DETECT_SENSE                        (1 << 8)
+#define R200_FP_SOURCE_SEL_MASK                (3 << 10)
+#define R200_FP_SOURCE_SEL_CRTC1       (0 << 10)
+#define R200_FP_SOURCE_SEL_CRTC2       (1 << 10)
+#define R200_FP_SOURCE_SEL_RMX         (2 << 10)
+#define R200_FP_SOURCE_SEL_TRANS       (3 << 10)
+#define FP_SEL_CRTC1                   (0 << 13)
+#define FP_SEL_CRTC2                   (1 << 13)
+#define FP_USE_VGA_HSYNC               (1 << 14)
+#define FP_CRTC_DONT_SHADOW_HPAR       (1 << 15)
+#define FP_CRTC_DONT_SHADOW_VPAR       (1 << 16)
+#define FP_CRTC_DONT_SHADOW_HEND       (1 << 17)
+#define FP_CRTC_USE_SHADOW_VEND                (1 << 18)
+#define FP_RMX_HVSYNC_CONTROL_EN       (1 << 20)
+#define FP_DFP_SYNC_SEL                        (1 << 21)
+#define FP_CRTC_LOCK_8DOT              (1 << 22)
+#define FP_CRT_SYNC_SEL                        (1 << 23)
+#define FP_USE_SHADOW_EN               (1 << 24)
+#define FP_CRT_SYNC_ALT                        (1 << 26)
 
 /* FP2_GEN_CNTL bit constants */
-#define FP2_BLANK_EN             (1 <<  1)
-#define FP2_ON                   (1 <<  2)
-#define FP2_PANEL_FORMAT         (1 <<  3)
-#define FP2_SOURCE_SEL_MASK      (3 << 10)
-#define FP2_SOURCE_SEL_CRTC2     (1 << 10)
-#define FP2_SRC_SEL_MASK         (3 << 13)
-#define FP2_SRC_SEL_CRTC2        (1 << 13)
-#define FP2_FP_POL               (1 << 16)
-#define FP2_LP_POL               (1 << 17)
-#define FP2_SCK_POL              (1 << 18)
-#define FP2_LCD_CNTL_MASK        (7 << 19)
-#define FP2_PAD_FLOP_EN          (1 << 22)
-#define FP2_CRC_EN               (1 << 23)
-#define FP2_CRC_READ_EN          (1 << 24)
-#define FP2_DV0_EN               (1 << 25)
-#define FP2_DV0_RATE_SEL_SDR     (1 << 26)
+#define FP2_BLANK_EN                   (1 <<   1)
+#define FP2_ON                         (1 <<   2)
+#define FP2_PANEL_FORMAT               (1 <<   3)
+#define FP2_SOURCE_SEL_MASK            (3 << 10)
+#define FP2_SOURCE_SEL_CRTC2           (1 << 10)
+#define FP2_SRC_SEL_MASK               (3 << 13)
+#define FP2_SRC_SEL_CRTC2              (1 << 13)
+#define FP2_FP_POL                     (1 << 16)
+#define FP2_LP_POL                     (1 << 17)
+#define FP2_SCK_POL                    (1 << 18)
+#define FP2_LCD_CNTL_MASK              (7 << 19)
+#define FP2_PAD_FLOP_EN                        (1 << 22)
+#define FP2_CRC_EN                     (1 << 23)
+#define FP2_CRC_READ_EN                        (1 << 24)
+#define FP2_DV0_EN                     (1 << 25)
+#define FP2_DV0_RATE_SEL_SDR           (1 << 26)
 
 
 /* LVDS_GEN_CNTL bit constants */
-#define LVDS_ON                                           (1 << 0)
-#define LVDS_DISPLAY_DIS                          (1 << 1)
-#define LVDS_PANEL_TYPE                                   (1 << 2)
-#define LVDS_PANEL_FORMAT                         (1 << 3)
-#define LVDS_EN                                           (1 << 7)
-#define LVDS_BL_MOD_LEVEL_MASK                    0x0000ff00
-#define LVDS_BL_MOD_LEVEL_SHIFT                           8
-#define LVDS_BL_MOD_EN                            (1 << 16)
-#define LVDS_DIGON                                (1 << 18)
-#define LVDS_BLON                                 (1 << 19)
-#define LVDS_SEL_CRTC2                            (1 << 23)
-#define LVDS_STATE_MASK        \
+#define LVDS_ON                                (1 << 0)
+#define LVDS_DISPLAY_DIS               (1 << 1)
+#define LVDS_PANEL_TYPE                        (1 << 2)
+#define LVDS_PANEL_FORMAT              (1 << 3)
+#define LVDS_EN                                (1 << 7)
+#define LVDS_BL_MOD_LEVEL_MASK         0x0000ff00
+#define LVDS_BL_MOD_LEVEL_SHIFT                8
+#define LVDS_BL_MOD_EN                 (1 << 16)
+#define LVDS_DIGON                     (1 << 18)
+#define LVDS_BLON                      (1 << 19)
+#define LVDS_SEL_CRTC2                 (1 << 23)
+#define LVDS_STATE_MASK \
        (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON)
 
 /* LVDS_PLL_CNTL bit constatns */
-#define HSYNC_DELAY_SHIFT                         0x1c
-#define HSYNC_DELAY_MASK                          (0xf << 0x1c)
+#define HSYNC_DELAY_SHIFT              0x1c
+#define HSYNC_DELAY_MASK               (0xf << 0x1c)
 
 /* TMDS_TRANSMITTER_CNTL bit constants */
-#define TMDS_PLL_EN                               (1 << 0)
-#define TMDS_PLLRST                               (1 << 1)
-#define TMDS_RAN_PAT_RST                          (1 << 7)
-#define TMDS_ICHCSEL                              (1 << 28)
+#define TMDS_PLL_EN                    (1 << 0)
+#define TMDS_PLLRST                    (1 << 1)
+#define TMDS_RAN_PAT_RST               (1 << 7)
+#define TMDS_ICHCSEL                   (1 << 28)
 
 /* FP_HORZ_STRETCH bit constants */
-#define HORZ_STRETCH_RATIO_MASK                           0xffff
-#define HORZ_STRETCH_RATIO_MAX                    4096
-#define HORZ_PANEL_SIZE                                   (0x1ff << 16)
-#define HORZ_PANEL_SHIFT                          16
-#define HORZ_STRETCH_PIXREP                       (0 << 25)
-#define HORZ_STRETCH_BLEND                        (1 << 26)
-#define HORZ_STRETCH_ENABLE                       (1 << 25)
-#define HORZ_AUTO_RATIO                                   (1 << 27)
-#define HORZ_FP_LOOP_STRETCH                      (0x7 << 28)
-#define HORZ_AUTO_RATIO_INC                       (1 << 31)
+#define HORZ_STRETCH_RATIO_MASK                0xffff
+#define HORZ_STRETCH_RATIO_MAX         4096
+#define HORZ_PANEL_SIZE                        (0x1ff << 16)
+#define HORZ_PANEL_SHIFT               16
+#define HORZ_STRETCH_PIXREP            (0 << 25)
+#define HORZ_STRETCH_BLEND             (1 << 26)
+#define HORZ_STRETCH_ENABLE            (1 << 25)
+#define HORZ_AUTO_RATIO                        (1 << 27)
+#define HORZ_FP_LOOP_STRETCH           (0x7 << 28)
+#define HORZ_AUTO_RATIO_INC            (1 << 31)
 
 
 /* FP_VERT_STRETCH bit constants */
-#define VERT_STRETCH_RATIO_MASK                           0xfff
-#define VERT_STRETCH_RATIO_MAX                    4096
-#define VERT_PANEL_SIZE                                   (0xfff << 12)
-#define VERT_PANEL_SHIFT                          12
-#define VERT_STRETCH_LINREP                       (0 << 26)
-#define VERT_STRETCH_BLEND                        (1 << 26)
-#define VERT_STRETCH_ENABLE                       (1 << 25)
-#define VERT_AUTO_RATIO_EN                        (1 << 27)
-#define VERT_FP_LOOP_STRETCH                      (0x7 << 28)
-#define VERT_STRETCH_RESERVED                     0xf1000000
+#define VERT_STRETCH_RATIO_MASK                0xfff
+#define VERT_STRETCH_RATIO_MAX         4096
+#define VERT_PANEL_SIZE                        (0xfff << 12)
+#define VERT_PANEL_SHIFT               12
+#define VERT_STRETCH_LINREP            (0 << 26)
+#define VERT_STRETCH_BLEND             (1 << 26)
+#define VERT_STRETCH_ENABLE            (1 << 25)
+#define VERT_AUTO_RATIO_EN             (1 << 27)
+#define VERT_FP_LOOP_STRETCH           (0x7 << 28)
+#define VERT_STRETCH_RESERVED          0xf1000000
 
 /* DAC_CNTL bit constants */
-#define DAC_8BIT_EN                                0x00000100
-#define DAC_4BPP_PIX_ORDER                         0x00000200
-#define DAC_CRC_EN                                 0x00080000
-#define DAC_MASK_ALL                              (0xff << 24)
-#define DAC_PDWN                                   (1 << 15)
-#define DAC_EXPAND_MODE                                   (1 << 14)
-#define DAC_VGA_ADR_EN                            (1 << 13)
-#define DAC_RANGE_CNTL                            (3 <<  0)
-#define DAC_RANGE_CNTL_MASK                               0x03
-#define DAC_BLANKING                              (1 <<  2)
-#define DAC_CMP_EN                                 (1 <<  3)
-#define DAC_CMP_OUTPUT                             (1 <<  7)
+#define DAC_8BIT_EN                    0x00000100
+#define DAC_4BPP_PIX_ORDER             0x00000200
+#define DAC_CRC_EN                     0x00080000
+#define DAC_MASK_ALL                   (0xff << 24)
+#define DAC_PDWN                       (1 << 15)
+#define DAC_EXPAND_MODE                        (1 << 14)
+#define DAC_VGA_ADR_EN                 (1 << 13)
+#define DAC_RANGE_CNTL                 (3 <<  0)
+#define DAC_RANGE_CNTL_MASK            0x03
+#define DAC_BLANKING                   (1 <<  2)
+#define DAC_CMP_EN                     (1 <<  3)
+#define DAC_CMP_OUTPUT                 (1 <<  7)
 
 /* DAC_CNTL2 bit constants */
-#define DAC2_EXPAND_MODE                          (1 << 14)
-#define DAC2_CMP_EN                                (1 << 7)
-#define DAC2_PALETTE_ACCESS_CNTL                   (1 << 5)
+#define DAC2_EXPAND_MODE               (1 << 14)
+#define DAC2_CMP_EN                    (1 << 7)
+#define DAC2_PALETTE_ACCESS_CNTL       (1 << 5)
 
 /* DAC_EXT_CNTL bit constants */
-#define DAC_FORCE_BLANK_OFF_EN                     (1 << 4)
-#define DAC_FORCE_DATA_EN                          (1 << 5)
-#define DAC_FORCE_DATA_SEL_MASK                    (3 << 6)
-#define DAC_FORCE_DATA_MASK                        0x0003ff00
-#define DAC_FORCE_DATA_SHIFT                       8
+#define DAC_FORCE_BLANK_OFF_EN         (1 << 4)
+#define DAC_FORCE_DATA_EN              (1 << 5)
+#define DAC_FORCE_DATA_SEL_MASK                (3 << 6)
+#define DAC_FORCE_DATA_MASK            0x0003ff00
+#define DAC_FORCE_DATA_SHIFT           8
 
 /* GEN_RESET_CNTL bit constants */
-#define SOFT_RESET_GUI                             0x00000001
-#define SOFT_RESET_VCLK                            0x00000100
-#define SOFT_RESET_PCLK                            0x00000200
-#define SOFT_RESET_ECP                             0x00000400
-#define SOFT_RESET_DISPENG_XCLK                    0x00000800
+#define SOFT_RESET_GUI                 0x00000001
+#define SOFT_RESET_VCLK                        0x00000100
+#define SOFT_RESET_PCLK                        0x00000200
+#define SOFT_RESET_ECP                 0x00000400
+#define SOFT_RESET_DISPENG_XCLK                0x00000800
 
 /* MEM_CNTL bit constants */
-#define MEM_CTLR_STATUS_IDLE                       0x00000000
-#define MEM_CTLR_STATUS_BUSY                       0x00100000
-#define MEM_SEQNCR_STATUS_IDLE                     0x00000000
-#define MEM_SEQNCR_STATUS_BUSY                     0x00200000
-#define MEM_ARBITER_STATUS_IDLE                    0x00000000
-#define MEM_ARBITER_STATUS_BUSY                    0x00400000
-#define MEM_REQ_UNLOCK                             0x00000000
-#define MEM_REQ_LOCK                               0x00800000
-#define MEM_NUM_CHANNELS_MASK                     0x00000001
-#define MEM_USE_B_CH_ONLY                          0x00000002
-#define RV100_MEM_HALF_MODE                        0x00000008
-#define R300_MEM_NUM_CHANNELS_MASK                 0x00000003
-#define R300_MEM_USE_CD_CH_ONLY                    0x00000004
+#define MEM_CTLR_STATUS_IDLE           0x00000000
+#define MEM_CTLR_STATUS_BUSY           0x00100000
+#define MEM_SEQNCR_STATUS_IDLE         0x00000000
+#define MEM_SEQNCR_STATUS_BUSY         0x00200000
+#define MEM_ARBITER_STATUS_IDLE                0x00000000
+#define MEM_ARBITER_STATUS_BUSY                0x00400000
+#define MEM_REQ_UNLOCK                 0x00000000
+#define MEM_REQ_LOCK                   0x00800000
+#define MEM_NUM_CHANNELS_MASK          0x00000001
+#define MEM_USE_B_CH_ONLY              0x00000002
+#define RV100_MEM_HALF_MODE            0x00000008
+#define R300_MEM_NUM_CHANNELS_MASK     0x00000003
+#define R300_MEM_USE_CD_CH_ONLY                0x00000004
 
 
 /* RBBM_SOFT_RESET bit constants */
-#define SOFT_RESET_CP                             (1 <<  0)
-#define SOFT_RESET_HI                             (1 <<  1)
-#define SOFT_RESET_SE                             (1 <<  2)
-#define SOFT_RESET_RE                             (1 <<  3)
-#define SOFT_RESET_PP                             (1 <<  4)
-#define SOFT_RESET_E2                             (1 <<  5)
-#define SOFT_RESET_RB                             (1 <<  6)
-#define SOFT_RESET_HDP                            (1 <<  7)
+#define SOFT_RESET_CP                  (1 <<  0)
+#define SOFT_RESET_HI                  (1 <<  1)
+#define SOFT_RESET_SE                  (1 <<  2)
+#define SOFT_RESET_RE                  (1 <<  3)
+#define SOFT_RESET_PP                  (1 <<  4)
+#define SOFT_RESET_E2                  (1 <<  5)
+#define SOFT_RESET_RB                  (1 <<  6)
+#define SOFT_RESET_HDP                 (1 <<  7)
 
 /* SURFACE_CNTL bit consants */
-#define SURF_TRANSLATION_DIS                      (1 << 8)
-#define NONSURF_AP0_SWP_16BPP                     (1 << 20)
-#define NONSURF_AP0_SWP_32BPP                     (1 << 21)
-#define NONSURF_AP1_SWP_16BPP                     (1 << 22)
-#define NONSURF_AP1_SWP_32BPP                     (1 << 23)
+#define SURF_TRANSLATION_DIS           (1 << 8)
+#define NONSURF_AP0_SWP_16BPP          (1 << 20)
+#define NONSURF_AP0_SWP_32BPP          (1 << 21)
+#define NONSURF_AP1_SWP_16BPP          (1 << 22)
+#define NONSURF_AP1_SWP_32BPP          (1 << 23)
 
 /* DEFAULT_SC_BOTTOM_RIGHT bit constants */
-#define DEFAULT_SC_RIGHT_MAX                      (0x1fff << 0)
-#define DEFAULT_SC_BOTTOM_MAX                     (0x1fff << 16)
+#define DEFAULT_SC_RIGHT_MAX           (0x1fff << 0)
+#define DEFAULT_SC_BOTTOM_MAX          (0x1fff << 16)
 
 /* MM_INDEX bit constants */
-#define MM_APER                                    0x80000000
+#define MM_APER                                0x80000000
 
 /* CLR_CMP_CNTL bit constants */
-#define COMPARE_SRC_FALSE                          0x00000000
-#define COMPARE_SRC_TRUE                           0x00000001
-#define COMPARE_SRC_NOT_EQUAL                      0x00000004
-#define COMPARE_SRC_EQUAL                          0x00000005
-#define COMPARE_SRC_EQUAL_FLIP                     0x00000007
-#define COMPARE_DST_FALSE                          0x00000000
-#define COMPARE_DST_TRUE                           0x00000100
-#define COMPARE_DST_NOT_EQUAL                      0x00000400
-#define COMPARE_DST_EQUAL                          0x00000500
-#define COMPARE_DESTINATION                        0x00000000
-#define COMPARE_SOURCE                             0x01000000
-#define COMPARE_SRC_AND_DST                        0x02000000
+#define COMPARE_SRC_FALSE              0x00000000
+#define COMPARE_SRC_TRUE               0x00000001
+#define COMPARE_SRC_NOT_EQUAL          0x00000004
+#define COMPARE_SRC_EQUAL              0x00000005
+#define COMPARE_SRC_EQUAL_FLIP         0x00000007
+#define COMPARE_DST_FALSE              0x00000000
+#define COMPARE_DST_TRUE               0x00000100
+#define COMPARE_DST_NOT_EQUAL          0x00000400
+#define COMPARE_DST_EQUAL              0x00000500
+#define COMPARE_DESTINATION            0x00000000
+#define COMPARE_SOURCE                 0x01000000
+#define COMPARE_SRC_AND_DST            0x02000000
 
 
 /* DP_CNTL bit constants */
-#define DST_X_RIGHT_TO_LEFT                        0x00000000
-#define DST_X_LEFT_TO_RIGHT                        0x00000001
-#define DST_Y_BOTTOM_TO_TOP                        0x00000000
-#define DST_Y_TOP_TO_BOTTOM                        0x00000002
-#define DST_X_MAJOR                                0x00000000
-#define DST_Y_MAJOR                                0x00000004
-#define DST_X_TILE                                 0x00000008
-#define DST_Y_TILE                                 0x00000010
-#define DST_LAST_PEL                               0x00000020
-#define DST_TRAIL_X_RIGHT_TO_LEFT                  0x00000000
-#define DST_TRAIL_X_LEFT_TO_RIGHT                  0x00000040
-#define DST_TRAP_FILL_RIGHT_TO_LEFT                0x00000000
-#define DST_TRAP_FILL_LEFT_TO_RIGHT                0x00000080
-#define DST_BRES_SIGN                              0x00000100
-#define DST_HOST_BIG_ENDIAN_EN                     0x00000200
-#define DST_POLYLINE_NONLAST                       0x00008000
-#define DST_RASTER_STALL                           0x00010000
-#define DST_POLY_EDGE                              0x00040000
+#define DST_X_RIGHT_TO_LEFT            0x00000000
+#define DST_X_LEFT_TO_RIGHT            0x00000001
+#define DST_Y_BOTTOM_TO_TOP            0x00000000
+#define DST_Y_TOP_TO_BOTTOM            0x00000002
+#define DST_X_MAJOR                    0x00000000
+#define DST_Y_MAJOR                    0x00000004
+#define DST_X_TILE                     0x00000008
+#define DST_Y_TILE                     0x00000010
+#define DST_LAST_PEL                   0x00000020
+#define DST_TRAIL_X_RIGHT_TO_LEFT      0x00000000
+#define DST_TRAIL_X_LEFT_TO_RIGHT      0x00000040
+#define DST_TRAP_FILL_RIGHT_TO_LEFT    0x00000000
+#define DST_TRAP_FILL_LEFT_TO_RIGHT    0x00000080
+#define DST_BRES_SIGN                  0x00000100
+#define DST_HOST_BIG_ENDIAN_EN         0x00000200
+#define DST_POLYLINE_NONLAST           0x00008000
+#define DST_RASTER_STALL               0x00010000
+#define DST_POLY_EDGE                  0x00040000
 
 
 /* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */
-#define DST_X_MAJOR_S                              0x00000000
-#define DST_Y_MAJOR_S                              0x00000001
-#define DST_Y_BOTTOM_TO_TOP_S                      0x00000000
-#define DST_Y_TOP_TO_BOTTOM_S                      0x00008000
-#define DST_X_RIGHT_TO_LEFT_S                      0x00000000
-#define DST_X_LEFT_TO_RIGHT_S                      0x80000000
+#define DST_X_MAJOR_S                  0x00000000
+#define DST_Y_MAJOR_S                  0x00000001
+#define DST_Y_BOTTOM_TO_TOP_S          0x00000000
+#define DST_Y_TOP_TO_BOTTOM_S          0x00008000
+#define DST_X_RIGHT_TO_LEFT_S          0x00000000
+#define DST_X_LEFT_TO_RIGHT_S          0x80000000
 
 
 /* DP_DATATYPE bit constants */
-#define DST_8BPP                                   0x00000002
-#define DST_15BPP                                  0x00000003
-#define DST_16BPP                                  0x00000004
-#define DST_24BPP                                  0x00000005
-#define DST_32BPP                                  0x00000006
-#define DST_8BPP_RGB332                            0x00000007
-#define DST_8BPP_Y8                                0x00000008
-#define DST_8BPP_RGB8                              0x00000009
-#define DST_16BPP_VYUY422                          0x0000000b
-#define DST_16BPP_YVYU422                          0x0000000c
-#define DST_32BPP_AYUV444                          0x0000000e
-#define DST_16BPP_ARGB4444                         0x0000000f
-#define BRUSH_SOLIDCOLOR                           0x00000d00
-#define SRC_MONO                                   0x00000000
-#define SRC_MONO_LBKGD                             0x00010000
-#define SRC_DSTCOLOR                               0x00030000
-#define BYTE_ORDER_MSB_TO_LSB                      0x00000000
-#define BYTE_ORDER_LSB_TO_MSB                      0x40000000
-#define DP_CONVERSION_TEMP                         0x80000000
-#define HOST_BIG_ENDIAN_EN                        (1 << 29)
+#define DST_8BPP                       0x00000002
+#define DST_15BPP                      0x00000003
+#define DST_16BPP                      0x00000004
+#define DST_24BPP                      0x00000005
+#define DST_32BPP                      0x00000006
+#define DST_8BPP_RGB332                        0x00000007
+#define DST_8BPP_Y8                    0x00000008
+#define DST_8BPP_RGB8                  0x00000009
+#define DST_16BPP_VYUY422              0x0000000b
+#define DST_16BPP_YVYU422              0x0000000c
+#define DST_32BPP_AYUV444              0x0000000e
+#define DST_16BPP_ARGB4444             0x0000000f
+#define BRUSH_SOLIDCOLOR               0x00000d00
+#define SRC_MONO                       0x00000000
+#define SRC_MONO_LBKGD                 0x00010000
+#define SRC_DSTCOLOR                   0x00030000
+#define BYTE_ORDER_MSB_TO_LSB          0x00000000
+#define BYTE_ORDER_LSB_TO_MSB          0x40000000
+#define DP_CONVERSION_TEMP             0x80000000
+#define HOST_BIG_ENDIAN_EN             (1 << 29)
 
 
 /* DP_GUI_MASTER_CNTL bit constants */
-#define GMC_SRC_PITCH_OFFSET_DEFAULT               0x00000000
-#define GMC_SRC_PITCH_OFFSET_LEAVE                 0x00000001
-#define GMC_DST_PITCH_OFFSET_DEFAULT               0x00000000
-#define GMC_DST_PITCH_OFFSET_LEAVE                 0x00000002
-#define GMC_SRC_CLIP_DEFAULT                       0x00000000
-#define GMC_SRC_CLIP_LEAVE                         0x00000004
-#define GMC_DST_CLIP_DEFAULT                       0x00000000
-#define GMC_DST_CLIP_LEAVE                         0x00000008
-#define GMC_BRUSH_8x8MONO                          0x00000000
-#define GMC_BRUSH_8x8MONO_LBKGD                    0x00000010
-#define GMC_BRUSH_8x1MONO                          0x00000020
-#define GMC_BRUSH_8x1MONO_LBKGD                    0x00000030
-#define GMC_BRUSH_1x8MONO                          0x00000040
-#define GMC_BRUSH_1x8MONO_LBKGD                    0x00000050
-#define GMC_BRUSH_32x1MONO                         0x00000060
-#define GMC_BRUSH_32x1MONO_LBKGD                   0x00000070
-#define GMC_BRUSH_32x32MONO                        0x00000080
-#define GMC_BRUSH_32x32MONO_LBKGD                  0x00000090
-#define GMC_BRUSH_8x8COLOR                         0x000000a0
-#define GMC_BRUSH_8x1COLOR                         0x000000b0
-#define GMC_BRUSH_1x8COLOR                         0x000000c0
-#define GMC_BRUSH_SOLID_COLOR                       0x000000d0
-#define GMC_DST_8BPP                               0x00000200
-#define GMC_DST_15BPP                              0x00000300
-#define GMC_DST_16BPP                              0x00000400
-#define GMC_DST_24BPP                              0x00000500
-#define GMC_DST_32BPP                              0x00000600
-#define GMC_DST_8BPP_RGB332                        0x00000700
-#define GMC_DST_8BPP_Y8                            0x00000800
-#define GMC_DST_8BPP_RGB8                          0x00000900
-#define GMC_DST_16BPP_VYUY422                      0x00000b00
-#define GMC_DST_16BPP_YVYU422                      0x00000c00
-#define GMC_DST_32BPP_AYUV444                      0x00000e00
-#define GMC_DST_16BPP_ARGB4444                     0x00000f00
-#define GMC_SRC_MONO                               0x00000000
-#define GMC_SRC_MONO_LBKGD                         0x00001000
-#define GMC_SRC_DSTCOLOR                           0x00003000
-#define GMC_BYTE_ORDER_MSB_TO_LSB                  0x00000000
-#define GMC_BYTE_ORDER_LSB_TO_MSB                  0x00004000
-#define GMC_DP_CONVERSION_TEMP_9300                0x00008000
-#define GMC_DP_CONVERSION_TEMP_6500                0x00000000
-#define GMC_DP_SRC_RECT                            0x02000000
-#define GMC_DP_SRC_HOST                            0x03000000
-#define GMC_DP_SRC_HOST_BYTEALIGN                  0x04000000
-#define GMC_3D_FCN_EN_CLR                          0x00000000
-#define GMC_3D_FCN_EN_SET                          0x08000000
-#define GMC_DST_CLR_CMP_FCN_LEAVE                  0x00000000
-#define GMC_DST_CLR_CMP_FCN_CLEAR                  0x10000000
-#define GMC_AUX_CLIP_LEAVE                         0x00000000
-#define GMC_AUX_CLIP_CLEAR                         0x20000000
-#define GMC_WRITE_MASK_LEAVE                       0x00000000
-#define GMC_WRITE_MASK_SET                         0x40000000
-#define GMC_CLR_CMP_CNTL_DIS                      (1 << 28)
-#define GMC_SRC_DATATYPE_COLOR                    (3 << 12)
-#define ROP3_S                                    0x00cc0000
-#define ROP3_SRCCOPY                              0x00cc0000
-#define ROP3_P                                    0x00f00000
-#define ROP3_PATCOPY                              0x00f00000
-#define DP_SRC_SOURCE_MASK                        (7    << 24)
-#define GMC_BRUSH_NONE                            (15   <<  4)
-#define DP_SRC_SOURCE_MEMORY                      (2    << 24)
-#define GMC_BRUSH_SOLIDCOLOR                      0x000000d0
+#define GMC_SRC_PITCH_OFFSET_DEFAULT   0x00000000
+#define GMC_SRC_PITCH_OFFSET_LEAVE     0x00000001
+#define GMC_DST_PITCH_OFFSET_DEFAULT   0x00000000
+#define GMC_DST_PITCH_OFFSET_LEAVE     0x00000002
+#define GMC_SRC_CLIP_DEFAULT           0x00000000
+#define GMC_SRC_CLIP_LEAVE             0x00000004
+#define GMC_DST_CLIP_DEFAULT           0x00000000
+#define GMC_DST_CLIP_LEAVE             0x00000008
+#define GMC_BRUSH_8x8MONO              0x00000000
+#define GMC_BRUSH_8x8MONO_LBKGD                0x00000010
+#define GMC_BRUSH_8x1MONO              0x00000020
+#define GMC_BRUSH_8x1MONO_LBKGD                0x00000030
+#define GMC_BRUSH_1x8MONO              0x00000040
+#define GMC_BRUSH_1x8MONO_LBKGD                0x00000050
+#define GMC_BRUSH_32x1MONO             0x00000060
+#define GMC_BRUSH_32x1MONO_LBKGD       0x00000070
+#define GMC_BRUSH_32x32MONO            0x00000080
+#define GMC_BRUSH_32x32MONO_LBKGD      0x00000090
+#define GMC_BRUSH_8x8COLOR             0x000000a0
+#define GMC_BRUSH_8x1COLOR             0x000000b0
+#define GMC_BRUSH_1x8COLOR             0x000000c0
+#define GMC_BRUSH_SOLID_COLOR          0x000000d0
+#define GMC_DST_8BPP                   0x00000200
+#define GMC_DST_15BPP                  0x00000300
+#define GMC_DST_16BPP                  0x00000400
+#define GMC_DST_24BPP                  0x00000500
+#define GMC_DST_32BPP                  0x00000600
+#define GMC_DST_8BPP_RGB332            0x00000700
+#define GMC_DST_8BPP_Y8                        0x00000800
+#define GMC_DST_8BPP_RGB8              0x00000900
+#define GMC_DST_16BPP_VYUY422          0x00000b00
+#define GMC_DST_16BPP_YVYU422          0x00000c00
+#define GMC_DST_32BPP_AYUV444          0x00000e00
+#define GMC_DST_16BPP_ARGB4444         0x00000f00
+#define GMC_SRC_MONO                   0x00000000
+#define GMC_SRC_MONO_LBKGD             0x00001000
+#define GMC_SRC_DSTCOLOR               0x00003000
+#define GMC_BYTE_ORDER_MSB_TO_LSB      0x00000000
+#define GMC_BYTE_ORDER_LSB_TO_MSB      0x00004000
+#define GMC_DP_CONVERSION_TEMP_9300    0x00008000
+#define GMC_DP_CONVERSION_TEMP_6500    0x00000000
+#define GMC_DP_SRC_RECT                        0x02000000
+#define GMC_DP_SRC_HOST                        0x03000000
+#define GMC_DP_SRC_HOST_BYTEALIGN      0x04000000
+#define GMC_3D_FCN_EN_CLR              0x00000000
+#define GMC_3D_FCN_EN_SET              0x08000000
+#define GMC_DST_CLR_CMP_FCN_LEAVE      0x00000000
+#define GMC_DST_CLR_CMP_FCN_CLEAR      0x10000000
+#define GMC_AUX_CLIP_LEAVE             0x00000000
+#define GMC_AUX_CLIP_CLEAR             0x20000000
+#define GMC_WRITE_MASK_LEAVE           0x00000000
+#define GMC_WRITE_MASK_SET             0x40000000
+#define GMC_CLR_CMP_CNTL_DIS           (1 << 28)
+#define GMC_SRC_DATATYPE_COLOR         (3 << 12)
+#define ROP3_S                         0x00cc0000
+#define ROP3_SRCCOPY                   0x00cc0000
+#define ROP3_P                         0x00f00000
+#define ROP3_PATCOPY                   0x00f00000
+#define DP_SRC_SOURCE_MASK             (7  << 24)
+#define GMC_BRUSH_NONE                 (15 <<  4)
+#define DP_SRC_SOURCE_MEMORY           (2  << 24)
+#define GMC_BRUSH_SOLIDCOLOR           0x000000d0
 
 /* DP_MIX bit constants */
-#define DP_SRC_RECT                                0x00000200
-#define DP_SRC_HOST                                0x00000300
-#define DP_SRC_HOST_BYTEALIGN                      0x00000400
+#define DP_SRC_RECT                    0x00000200
+#define DP_SRC_HOST                    0x00000300
+#define DP_SRC_HOST_BYTEALIGN          0x00000400
 
 /* MPLL_CNTL bit constants */
-#define MPLL_RESET                                 0x00000001
+#define MPLL_RESET                     0x00000001
 
 /* MDLL_CKO bit constants */
-#define MCKOA_SLEEP                                0x00000001
-#define MCKOA_RESET                                0x00000002
-#define MCKOA_REF_SKEW_MASK                        0x00000700
-#define MCKOA_FB_SKEW_MASK                         0x00007000
+#define MCKOA_SLEEP                    0x00000001
+#define MCKOA_RESET                    0x00000002
+#define MCKOA_REF_SKEW_MASK            0x00000700
+#define MCKOA_FB_SKEW_MASK             0x00007000
 
 /* MDLL_RDCKA bit constants */
-#define MRDCKA0_SLEEP                              0x00000001
-#define MRDCKA0_RESET                              0x00000002
-#define MRDCKA1_SLEEP                              0x00010000
-#define MRDCKA1_RESET                              0x00020000
+#define MRDCKA0_SLEEP                  0x00000001
+#define MRDCKA0_RESET                  0x00000002
+#define MRDCKA1_SLEEP                  0x00010000
+#define MRDCKA1_RESET                  0x00020000
 
 /* VCLK_ECP_CNTL constants */
-#define VCLK_SRC_SEL_MASK                          0x03
-#define VCLK_SRC_SEL_CPUCLK                        0x00
-#define VCLK_SRC_SEL_PSCANCLK                      0x01
-#define VCLK_SRC_SEL_BYTECLK                      0x02
-#define VCLK_SRC_SEL_PPLLCLK                      0x03
-#define PIXCLK_ALWAYS_ONb                          0x00000040
-#define PIXCLK_DAC_ALWAYS_ONb                      0x00000080
+#define VCLK_SRC_SEL_MASK              0x03
+#define VCLK_SRC_SEL_CPUCLK            0x00
+#define VCLK_SRC_SEL_PSCANCLK          0x01
+#define VCLK_SRC_SEL_BYTECLK           0x02
+#define VCLK_SRC_SEL_PPLLCLK           0x03
+#define PIXCLK_ALWAYS_ONb              0x00000040
+#define PIXCLK_DAC_ALWAYS_ONb          0x00000080
 
 /* BUS_CNTL1 constants */
-#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK         0x0c000000
-#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT        26
-#define BUS_CNTL1_AGPCLK_VALID                     0x80000000
+#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK     0x0c000000
+#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT    26
+#define BUS_CNTL1_AGPCLK_VALID                 0x80000000
 
 /* PLL_PWRMGT_CNTL constants */
-#define PLL_PWRMGT_CNTL_SPLL_TURNOFF               0x00000002
-#define PLL_PWRMGT_CNTL_PPLL_TURNOFF               0x00000004
-#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF              0x00000008
-#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF              0x00000010
-#define PLL_PWRMGT_CNTL_MOBILE_SU                  0x00010000
-#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK           0x00020000
-#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK           0x00040000
+#define PLL_PWRMGT_CNTL_SPLL_TURNOFF           0x00000002
+#define PLL_PWRMGT_CNTL_PPLL_TURNOFF           0x00000004
+#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF          0x00000008
+#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF          0x00000010
+#define PLL_PWRMGT_CNTL_MOBILE_SU              0x00010000
+#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK       0x00020000
+#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK       0x00040000
 
 /* TV_DAC_CNTL constants */
-#define TV_DAC_CNTL_BGSLEEP                        0x00000040
-#define TV_DAC_CNTL_DETECT                         0x00000010
-#define TV_DAC_CNTL_BGADJ_MASK                     0x000f0000
-#define TV_DAC_CNTL_DACADJ_MASK                    0x00f00000
-#define TV_DAC_CNTL_BGADJ__SHIFT                   16
-#define TV_DAC_CNTL_DACADJ__SHIFT                  20
-#define TV_DAC_CNTL_RDACPD                         0x01000000
-#define TV_DAC_CNTL_GDACPD                         0x02000000
-#define TV_DAC_CNTL_BDACPD                         0x04000000
+#define TV_DAC_CNTL_BGSLEEP                    0x00000040
+#define TV_DAC_CNTL_DETECT                     0x00000010
+#define TV_DAC_CNTL_BGADJ_MASK                 0x000f0000
+#define TV_DAC_CNTL_DACADJ_MASK                        0x00f00000
+#define TV_DAC_CNTL_BGADJ__SHIFT               16
+#define TV_DAC_CNTL_DACADJ__SHIFT              20
+#define TV_DAC_CNTL_RDACPD                     0x01000000
+#define TV_DAC_CNTL_GDACPD                     0x02000000
+#define TV_DAC_CNTL_BDACPD                     0x04000000
 
 /* DISP_MISC_CNTL constants */
-#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP          (1 << 0)
-#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP        (1 << 1)
-#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP           (1 << 2)
-#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK        (1 << 4)
-#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK      (1 << 5)
-#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK         (1 << 6)
-#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP         (1 << 12)
-#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK       (1 << 15)
-#define DISP_MISC_CNTL_SOFT_RESET_LVDS             (1 << 16)
-#define DISP_MISC_CNTL_SOFT_RESET_TMDS             (1 << 17)
-#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS         (1 << 18)
-#define DISP_MISC_CNTL_SOFT_RESET_TV               (1 << 19)
+#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP      (1 << 0)
+#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP    (1 << 1)
+#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP       (1 << 2)
+#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK    (1 << 4)
+#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK  (1 << 5)
+#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK     (1 << 6)
+#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP     (1 << 12)
+#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK   (1 << 15)
+#define DISP_MISC_CNTL_SOFT_RESET_LVDS         (1 << 16)
+#define DISP_MISC_CNTL_SOFT_RESET_TMDS         (1 << 17)
+#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS     (1 << 18)
+#define DISP_MISC_CNTL_SOFT_RESET_TV           (1 << 19)
 
 /* DISP_PWR_MAN constants */
-#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN       (1 << 0)
-#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN     (1 << 4)
-#define DISP_PWR_MAN_DISP_D3_RST                   (1 << 16)
-#define DISP_PWR_MAN_DISP_D3_REG_RST               (1 << 17)
-#define DISP_PWR_MAN_DISP_D3_GRPH_RST              (1 << 18)
-#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST            (1 << 19)
-#define DISP_PWR_MAN_DISP_D3_OV0_RST               (1 << 20)
-#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST            (1 << 21)
-#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST          (1 << 22)
-#define DISP_PWR_MAN_DISP_D1D2_OV0_RST             (1 << 23)
-#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST           (1 << 24)
-#define DISP_PWR_MAN_TV_ENABLE_RST                 (1 << 25)
-#define DISP_PWR_MAN_AUTO_PWRUP_EN                 (1 << 26)
+#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN   (1 << 0)
+#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4)
+#define DISP_PWR_MAN_DISP_D3_RST               (1 << 16)
+#define DISP_PWR_MAN_DISP_D3_REG_RST           (1 << 17)
+#define DISP_PWR_MAN_DISP_D3_GRPH_RST          (1 << 18)
+#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST                (1 << 19)
+#define DISP_PWR_MAN_DISP_D3_OV0_RST           (1 << 20)
+#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST                (1 << 21)
+#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST      (1 << 22)
+#define DISP_PWR_MAN_DISP_D1D2_OV0_RST         (1 << 23)
+#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST       (1 << 24)
+#define DISP_PWR_MAN_TV_ENABLE_RST             (1 << 25)
+#define DISP_PWR_MAN_AUTO_PWRUP_EN             (1 << 26)
 
 /* masks */
 
 #define DST_OFFSET_MASK                        0x003fffff
 #define DST_PITCH_MASK                 0x3fc00000
 #define DEFAULT_TILE_MASK              0xc0000000
-#define        PPLL_DIV_SEL_MASK               0x00000300
-#define        PPLL_RESET                      0x00000001
-#define        PPLL_SLEEP                      0x00000002
+#define PPLL_DIV_SEL_MASK              0x00000300
+#define PPLL_RESET                     0x00000001
+#define PPLL_SLEEP                     0x00000002
 #define PPLL_ATOMIC_UPDATE_EN          0x00010000
 #define PPLL_REF_DIV_MASK              0x000003ff
-#define        PPLL_FB3_DIV_MASK               0x000007ff
-#define        PPLL_POST3_DIV_MASK             0x00070000
+#define PPLL_FB3_DIV_MASK              0x000007ff
+#define PPLL_POST3_DIV_MASK            0x00070000
 #define PPLL_ATOMIC_UPDATE_R           0x00008000
 #define PPLL_ATOMIC_UPDATE_W           0x00008000
-#define        PPLL_VGA_ATOMIC_UPDATE_EN       0x00020000
+#define PPLL_VGA_ATOMIC_UPDATE_EN      0x00020000
 #define R300_PPLL_REF_DIV_ACC_MASK     (0x3ff << 18)
 #define R300_PPLL_REF_DIV_ACC_SHIFT    18
 
 #define GUI_ACTIVE                     0x80000000
 
 
-#define MC_IND_INDEX                           0x01F8
-#define MC_IND_DATA                            0x01FC
+#define MC_IND_INDEX                   0x01F8
+#define MC_IND_DATA                    0x01FC
 
 /* PAD_CTLR_STRENGTH */
 #define PAD_MANUAL_OVERRIDE            0x80000000
 
-// pllCLK_PIN_CNTL
-#define CLK_PIN_CNTL__OSC_EN_MASK                          0x00000001L
-#define CLK_PIN_CNTL__OSC_EN                               0x00000001L
-#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK                    0x00000004L
-#define CLK_PIN_CNTL__XTL_LOW_GAIN                         0x00000004L
-#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK                 0x00000010L
-#define CLK_PIN_CNTL__DONT_USE_XTALIN                      0x00000010L
-#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK               0x00000020L
-#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE                    0x00000020L
-#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK                0x00000800L
-#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN                     0x00000800L
-#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK           0x00001000L
-#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN                0x00001000L
-#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK          0x00002000L
-#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND               0x00002000L
-#define CLK_PIN_CNTL__CG_SPARE_MASK                        0x00004000L
-#define CLK_PIN_CNTL__CG_SPARE                             0x00004000L
-#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK             0x00008000L
-#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL                  0x00008000L
-#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK                  0x00010000L
-#define CLK_PIN_CNTL__CP_CLK_RUNNING                       0x00010000L
-#define CLK_PIN_CNTL__CG_SPARE_RD_MASK                     0x00060000L
-#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK               0x00080000L
-#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb                    0x00080000L
-#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK                    0xff000000L
-
-// pllCLK_PWRMGT_CNTL
-#define        CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT         0x00000000
-#define        CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT         0x00000001
-#define        CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT         0x00000002
-#define        CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT        0x00000003
-#define        CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT            0x00000004
-#define        CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT            0x00000005
-#define        CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT            0x00000006
-#define        CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT           0x00000007
-#define        CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT              0x00000008
-#define        CLK_PWRMGT_CNTL__TEST_MODE__SHIFT               0x00000009
-#define        CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT          0x0000000a
-#define        CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT      0x0000000c
-#define        CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT         0x0000000d
-#define        CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT       0x0000000f
-#define        CLK_PWRMGT_CNTL__MC_BUSY__SHIFT                 0x00000010
-#define        CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT             0x00000011
-#define        CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT               0x00000012
-#define        CLK_PWRMGT_CNTL__DLL_READY__SHIFT               0x00000013
-#define        CLK_PWRMGT_CNTL__DISP_PM__SHIFT                 0x00000014
-#define        CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT           0x00000015
-#define        CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT            0x00000018
-#define        CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT        0x0000001e
-#define        CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT           0x0000001f
-
-// pllP2PLL_CNTL
-#define P2PLL_CNTL__P2PLL_RESET_MASK                       0x00000001L
-#define P2PLL_CNTL__P2PLL_RESET                            0x00000001L
-#define P2PLL_CNTL__P2PLL_SLEEP_MASK                       0x00000002L
-#define P2PLL_CNTL__P2PLL_SLEEP                            0x00000002L
-#define P2PLL_CNTL__P2PLL_TST_EN_MASK                      0x00000004L
-#define P2PLL_CNTL__P2PLL_TST_EN                           0x00000004L
-#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK                  0x00000010L
-#define P2PLL_CNTL__P2PLL_REFCLK_SEL                       0x00000010L
-#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK                   0x00000020L
-#define P2PLL_CNTL__P2PLL_FBCLK_SEL                        0x00000020L
-#define P2PLL_CNTL__P2PLL_TCPOFF_MASK                      0x00000040L
-#define P2PLL_CNTL__P2PLL_TCPOFF                           0x00000040L
-#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK                     0x00000080L
-#define P2PLL_CNTL__P2PLL_TVCOMAX                          0x00000080L
-#define P2PLL_CNTL__P2PLL_PCP_MASK                         0x00000700L
-#define P2PLL_CNTL__P2PLL_PVG_MASK                         0x00003800L
-#define P2PLL_CNTL__P2PLL_PDC_MASK                         0x0000c000L
-#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK            0x00010000L
-#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN                 0x00010000L
-#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK          0x00040000L
-#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC               0x00040000L
-#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK          0x00080000L
-#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET               0x00080000L
-
-// pllPIXCLKS_CNTL
-#define        PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT               0x00000000
-#define        PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT                0x00000004
-#define        PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT            0x00000005
-#define        PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT            0x00000006
-#define        PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT        0x00000007
-#define        PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT             0x00000008
-#define        PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT       0x0000000b
-#define        PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT          0x0000000c
-#define        PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT    0x0000000d
-#define        PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT        0x0000000e
-#define        PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT        0x0000000f
-
-
-// pllPIXCLKS_CNTL
-#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK                 0x00000003L
-#define PIXCLKS_CNTL__PIX2CLK_INVERT                       0x00000010L
-#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT                   0x00000020L
-#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb                   0x00000040L
-#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb               0x00000080L
-#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL                    0x00000100L
-#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb              0x00000800L
-#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb                 0x00001000L
-#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb           0x00002000L
-#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb               0x00004000L
-#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb               0x00008000L
-#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb      (1 << 9)
-#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb               (1 << 10)
-#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb           (1 << 13)
-#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb         (1 << 16)
-#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb           (1 << 17)
-#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb              (1 << 18)
-#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb          (1 << 19)
-#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF  (1 << 23)
-
-
-// pllP2PLL_DIV_0
-#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK                     0x000007ffL
-#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK            0x00008000L
-#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W                 0x00008000L
-#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK            0x00008000L
-#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R                 0x00008000L
-#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK                   0x00070000L
-
-// pllSCLK_CNTL
-#define SCLK_CNTL__SCLK_SRC_SEL_MASK                    0x00000007L
-#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT                  0x00000008L
-#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT                 0x00000010L
-#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT                  0x00000020L
-#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT                  0x00000040L
-#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT                  0x00000080L
-#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT                0x00000100L
-#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT                 0x00000200L
-#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT                  0x00000400L
-#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT                  0x00000800L
-#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT                 0x00001000L
-#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT                 0x00002000L
-#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT                  0x00004000L
-#define SCLK_CNTL__DYN_STOP_LAT_MASK                     0x00007ff8
-#define SCLK_CNTL__FORCE_DISP2                          0x00008000L
-#define SCLK_CNTL__FORCE_CP                             0x00010000L
-#define SCLK_CNTL__FORCE_HDP                            0x00020000L
-#define SCLK_CNTL__FORCE_DISP1                          0x00040000L
-#define SCLK_CNTL__FORCE_TOP                            0x00080000L
-#define SCLK_CNTL__FORCE_E2                             0x00100000L
-#define SCLK_CNTL__FORCE_SE                             0x00200000L
-#define SCLK_CNTL__FORCE_IDCT                           0x00400000L
-#define SCLK_CNTL__FORCE_VIP                            0x00800000L
-#define SCLK_CNTL__FORCE_RE                             0x01000000L
-#define SCLK_CNTL__FORCE_PB                             0x02000000L
-#define SCLK_CNTL__FORCE_TAM                            0x04000000L
-#define SCLK_CNTL__FORCE_TDM                            0x08000000L
-#define SCLK_CNTL__FORCE_RB                             0x10000000L
-#define SCLK_CNTL__FORCE_TV_SCLK                        0x20000000L
-#define SCLK_CNTL__FORCE_SUBPIC                         0x40000000L
-#define SCLK_CNTL__FORCE_OV0                            0x80000000L
-#define SCLK_CNTL__R300_FORCE_VAP                       (1<<21)
-#define SCLK_CNTL__R300_FORCE_SR                        (1<<25)
-#define SCLK_CNTL__R300_FORCE_PX                        (1<<26)
-#define SCLK_CNTL__R300_FORCE_TX                        (1<<27)
-#define SCLK_CNTL__R300_FORCE_US                        (1<<28)
-#define SCLK_CNTL__R300_FORCE_SU                        (1<<30)
-#define SCLK_CNTL__FORCEON_MASK                         0xffff8000L
-
-// pllSCLK_CNTL2
-#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT           (1<<10)
-#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT            (1<<11)
-#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT           (1<<12)
-#define SCLK_CNTL2__R300_FORCE_TCL                      (1<<13)
-#define SCLK_CNTL2__R300_FORCE_CBA                      (1<<14)
-#define SCLK_CNTL2__R300_FORCE_GA                       (1<<15)
-
-// SCLK_MORE_CNTL
-#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT          0x00000001L
-#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT            0x00000002L
-#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT           0x00000004L
-#define SCLK_MORE_CNTL__FORCE_DISPREGS                     0x00000100L
-#define SCLK_MORE_CNTL__FORCE_MC_GUI                       0x00000200L
-#define SCLK_MORE_CNTL__FORCE_MC_HOST                      0x00000400L
-#define SCLK_MORE_CNTL__STOP_SCLK_EN                       0x00001000L
-#define SCLK_MORE_CNTL__STOP_SCLK_A                        0x00002000L
-#define SCLK_MORE_CNTL__STOP_SCLK_B                        0x00004000L
-#define SCLK_MORE_CNTL__STOP_SCLK_C                        0x00008000L
-#define SCLK_MORE_CNTL__HALF_SPEED_SCLK                    0x00010000L
-#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP                 0x00020000L
-#define SCLK_MORE_CNTL__TVFB_SOFT_RESET                    0x00040000L
-#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC                  0x00080000L
-#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK               0x00400000L
-#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK                 0x00800000L
-#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK                 0xff000000L
-#define SCLK_MORE_CNTL__FORCEON                            0x00000700L
-
-// MCLK_CNTL
-#define MCLK_CNTL__MCLKA_SRC_SEL_MASK                   0x00000007L
-#define MCLK_CNTL__YCLKA_SRC_SEL_MASK                   0x00000070L
-#define MCLK_CNTL__MCLKB_SRC_SEL_MASK                   0x00000700L
-#define MCLK_CNTL__YCLKB_SRC_SEL_MASK                   0x00007000L
-#define MCLK_CNTL__FORCE_MCLKA_MASK                     0x00010000L
-#define MCLK_CNTL__FORCE_MCLKA                          0x00010000L
-#define MCLK_CNTL__FORCE_MCLKB_MASK                     0x00020000L
-#define MCLK_CNTL__FORCE_MCLKB                          0x00020000L
-#define MCLK_CNTL__FORCE_YCLKA_MASK                     0x00040000L
-#define MCLK_CNTL__FORCE_YCLKA                          0x00040000L
-#define MCLK_CNTL__FORCE_YCLKB_MASK                     0x00080000L
-#define MCLK_CNTL__FORCE_YCLKB                          0x00080000L
-#define MCLK_CNTL__FORCE_MC_MASK                        0x00100000L
-#define MCLK_CNTL__FORCE_MC                             0x00100000L
-#define MCLK_CNTL__FORCE_AIC_MASK                       0x00200000L
-#define MCLK_CNTL__FORCE_AIC                            0x00200000L
-#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK                 0x03000000L
-#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK                 0x0c000000L
-#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK                 0x30000000L
-#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK                 0xc0000000L
-#define MCLK_CNTL__R300_DISABLE_MC_MCLKA                (1 << 21)
-#define MCLK_CNTL__R300_DISABLE_MC_MCLKB                (1 << 21)
-
-// MCLK_MISC
-#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK         0x00000003L
-#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK             0x00000004L
-#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL                  0x00000004L
-#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK              0x00000008L
-#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL                   0x00000008L
-#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK         0x00000010L
-#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN              0x00000010L
-#define MCLK_MISC__DLL_READY_LAT_MASK                      0x00000100L
-#define MCLK_MISC__DLL_READY_LAT                           0x00000100L
-#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK           0x00001000L
-#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT                0x00001000L
-#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK           0x00002000L
-#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT                0x00002000L
-#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK                 0x00004000L
-#define MCLK_MISC__MC_MCLK_DYN_ENABLE                      0x00004000L
-#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK                 0x00008000L
-#define MCLK_MISC__IO_MCLK_DYN_ENABLE                      0x00008000L
-#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK                  0x00010000L
-#define MCLK_MISC__CGM_CLK_TO_OUTPIN                       0x00010000L
-#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK                   0x00020000L
-#define MCLK_MISC__CLK_OR_COUNT_SEL                        0x00020000L
-#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK        0x00040000L
-#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND             0x00040000L
-#define MCLK_MISC__CGM_SPARE_RD_MASK                       0x00300000L
-#define MCLK_MISC__CGM_SPARE_A_RD_MASK                     0x00c00000L
-#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK                   0x01000000L
-#define MCLK_MISC__TCLK_TO_YCLKB_EN                        0x01000000L
-#define MCLK_MISC__CGM_SPARE_A_MASK                        0x0e000000L
-
-// VCLK_ECP_CNTL
-#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK                   0x00000003L
-#define VCLK_ECP_CNTL__VCLK_INVERT                         0x00000010L
-#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT                   0x00000020L
-#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb                   0x00000040L
-#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb               0x00000080L
-#define VCLK_ECP_CNTL__ECP_DIV_MASK                        0x00000300L
-#define VCLK_ECP_CNTL__ECP_FORCE_ON                        0x00040000L
-#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON                     0x00080000L
+/* pllCLK_PIN_CNTL */
+#define CLK_PIN_CNTL__OSC_EN_MASK                      0x00000001L
+#define CLK_PIN_CNTL__OSC_EN                           0x00000001L
+#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK                        0x00000004L
+#define CLK_PIN_CNTL__XTL_LOW_GAIN                     0x00000004L
+#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK             0x00000010L
+#define CLK_PIN_CNTL__DONT_USE_XTALIN                  0x00000010L
+#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK           0x00000020L
+#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE                        0x00000020L
+#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK            0x00000800L
+#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN                 0x00000800L
+#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK       0x00001000L
+#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN            0x00001000L
+#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK      0x00002000L
+#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND           0x00002000L
+#define CLK_PIN_CNTL__CG_SPARE_MASK                    0x00004000L
+#define CLK_PIN_CNTL__CG_SPARE                         0x00004000L
+#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK         0x00008000L
+#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL              0x00008000L
+#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK              0x00010000L
+#define CLK_PIN_CNTL__CP_CLK_RUNNING                   0x00010000L
+#define CLK_PIN_CNTL__CG_SPARE_RD_MASK                 0x00060000L
+#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK           0x00080000L
+#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb                        0x00080000L
+#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK                        0xff000000L
+
+/* pllCLK_PWRMGT_CNTL */
+#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT                0x00000000
+#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT                0x00000001
+#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT                0x00000002
+#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT       0x00000003
+#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT           0x00000004
+#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT           0x00000005
+#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT           0x00000006
+#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT          0x00000007
+#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT             0x00000008
+#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT              0x00000009
+#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT         0x0000000a
+#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT     0x0000000c
+#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT                0x0000000d
+#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT      0x0000000f
+#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT                        0x00000010
+#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT            0x00000011
+#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT              0x00000012
+#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT              0x00000013
+#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT                        0x00000014
+#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT          0x00000015
+#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT           0x00000018
+#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT       0x0000001e
+#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT          0x0000001f
+
+/* pllP2PLL_CNTL */
+#define P2PLL_CNTL__P2PLL_RESET_MASK                   0x00000001L
+#define P2PLL_CNTL__P2PLL_RESET                                0x00000001L
+#define P2PLL_CNTL__P2PLL_SLEEP_MASK                   0x00000002L
+#define P2PLL_CNTL__P2PLL_SLEEP                                0x00000002L
+#define P2PLL_CNTL__P2PLL_TST_EN_MASK                  0x00000004L
+#define P2PLL_CNTL__P2PLL_TST_EN                       0x00000004L
+#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK              0x00000010L
+#define P2PLL_CNTL__P2PLL_REFCLK_SEL                   0x00000010L
+#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK               0x00000020L
+#define P2PLL_CNTL__P2PLL_FBCLK_SEL                    0x00000020L
+#define P2PLL_CNTL__P2PLL_TCPOFF_MASK                  0x00000040L
+#define P2PLL_CNTL__P2PLL_TCPOFF                       0x00000040L
+#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK                 0x00000080L
+#define P2PLL_CNTL__P2PLL_TVCOMAX                      0x00000080L
+#define P2PLL_CNTL__P2PLL_PCP_MASK                     0x00000700L
+#define P2PLL_CNTL__P2PLL_PVG_MASK                     0x00003800L
+#define P2PLL_CNTL__P2PLL_PDC_MASK                     0x0000c000L
+#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK                0x00010000L
+#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN             0x00010000L
+#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK      0x00040000L
+#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC           0x00040000L
+#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK      0x00080000L
+#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET           0x00080000L
+
+/* pllPIXCLKS_CNTL */
+#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT           0x00000000
+#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT            0x00000004
+#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT                0x00000005
+#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT                0x00000006
+#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT    0x00000007
+#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT         0x00000008
+#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT   0x0000000b
+#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT      0x0000000c
+#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT        0x0000000d
+#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT    0x0000000e
+#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT    0x0000000f
+
+
+/* pllPIXCLKS_CNTL */
+#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK             0x00000003L
+#define PIXCLKS_CNTL__PIX2CLK_INVERT                   0x00000010L
+#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT               0x00000020L
+#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb               0x00000040L
+#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb           0x00000080L
+#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL                        0x00000100L
+#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb          0x00000800L
+#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb             0x00001000L
+#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb       0x00002000L
+#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb           0x00004000L
+#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb           0x00008000L
+#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb  (1 << 9)
+#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb           (1 << 10)
+#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb       (1 << 13)
+#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb     (1 << 16)
+#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb       (1 << 17)
+#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb          (1 << 18)
+#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb      (1 << 19)
+#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
+
+
+/* pllP2PLL_DIV_0 */
+#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK                 0x000007ffL
+#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK                0x00008000L
+#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W             0x00008000L
+#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK                0x00008000L
+#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R             0x00008000L
+#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK               0x00070000L
+
+/* pllSCLK_CNTL */
+#define SCLK_CNTL__SCLK_SRC_SEL_MASK                   0x00000007L
+#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT                 0x00000008L
+#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT                        0x00000010L
+#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT                 0x00000020L
+#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT                 0x00000040L
+#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT                 0x00000080L
+#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT               0x00000100L
+#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT                        0x00000200L
+#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT                 0x00000400L
+#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT                 0x00000800L
+#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT                        0x00001000L
+#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT                        0x00002000L
+#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT                 0x00004000L
+#define SCLK_CNTL__DYN_STOP_LAT_MASK                   0x00007ff8
+#define SCLK_CNTL__FORCE_DISP2                         0x00008000L
+#define SCLK_CNTL__FORCE_CP                            0x00010000L
+#define SCLK_CNTL__FORCE_HDP                           0x00020000L
+#define SCLK_CNTL__FORCE_DISP1                         0x00040000L
+#define SCLK_CNTL__FORCE_TOP                           0x00080000L
+#define SCLK_CNTL__FORCE_E2                            0x00100000L
+#define SCLK_CNTL__FORCE_SE                            0x00200000L
+#define SCLK_CNTL__FORCE_IDCT                          0x00400000L
+#define SCLK_CNTL__FORCE_VIP                           0x00800000L
+#define SCLK_CNTL__FORCE_RE                            0x01000000L
+#define SCLK_CNTL__FORCE_PB                            0x02000000L
+#define SCLK_CNTL__FORCE_TAM                           0x04000000L
+#define SCLK_CNTL__FORCE_TDM                           0x08000000L
+#define SCLK_CNTL__FORCE_RB                            0x10000000L
+#define SCLK_CNTL__FORCE_TV_SCLK                       0x20000000L
+#define SCLK_CNTL__FORCE_SUBPIC                                0x40000000L
+#define SCLK_CNTL__FORCE_OV0                           0x80000000L
+#define SCLK_CNTL__R300_FORCE_VAP                      (1<<21)
+#define SCLK_CNTL__R300_FORCE_SR                       (1<<25)
+#define SCLK_CNTL__R300_FORCE_PX                       (1<<26)
+#define SCLK_CNTL__R300_FORCE_TX                       (1<<27)
+#define SCLK_CNTL__R300_FORCE_US                       (1<<28)
+#define SCLK_CNTL__R300_FORCE_SU                       (1<<30)
+#define SCLK_CNTL__FORCEON_MASK                                0xffff8000L
+
+/* pllSCLK_CNTL2 */
+#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT          (1<<10)
+#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT           (1<<11)
+#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT          (1<<12)
+#define SCLK_CNTL2__R300_FORCE_TCL                     (1<<13)
+#define SCLK_CNTL2__R300_FORCE_CBA                     (1<<14)
+#define SCLK_CNTL2__R300_FORCE_GA                      (1<<15)
+
+/* SCLK_MORE_CNTL */
+#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT      0x00000001L
+#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT                0x00000002L
+#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT       0x00000004L
+#define SCLK_MORE_CNTL__FORCE_DISPREGS                 0x00000100L
+#define SCLK_MORE_CNTL__FORCE_MC_GUI                   0x00000200L
+#define SCLK_MORE_CNTL__FORCE_MC_HOST                  0x00000400L
+#define SCLK_MORE_CNTL__STOP_SCLK_EN                   0x00001000L
+#define SCLK_MORE_CNTL__STOP_SCLK_A                    0x00002000L
+#define SCLK_MORE_CNTL__STOP_SCLK_B                    0x00004000L
+#define SCLK_MORE_CNTL__STOP_SCLK_C                    0x00008000L
+#define SCLK_MORE_CNTL__HALF_SPEED_SCLK                        0x00010000L
+#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP             0x00020000L
+#define SCLK_MORE_CNTL__TVFB_SOFT_RESET                        0x00040000L
+#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC              0x00080000L
+#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK           0x00400000L
+#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK             0x00800000L
+#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK             0xff000000L
+#define SCLK_MORE_CNTL__FORCEON                                0x00000700L
+
+/* MCLK_CNTL */
+#define MCLK_CNTL__MCLKA_SRC_SEL_MASK                  0x00000007L
+#define MCLK_CNTL__YCLKA_SRC_SEL_MASK                  0x00000070L
+#define MCLK_CNTL__MCLKB_SRC_SEL_MASK                  0x00000700L
+#define MCLK_CNTL__YCLKB_SRC_SEL_MASK                  0x00007000L
+#define MCLK_CNTL__FORCE_MCLKA_MASK                    0x00010000L
+#define MCLK_CNTL__FORCE_MCLKA                         0x00010000L
+#define MCLK_CNTL__FORCE_MCLKB_MASK                    0x00020000L
+#define MCLK_CNTL__FORCE_MCLKB                         0x00020000L
+#define MCLK_CNTL__FORCE_YCLKA_MASK                    0x00040000L
+#define MCLK_CNTL__FORCE_YCLKA                         0x00040000L
+#define MCLK_CNTL__FORCE_YCLKB_MASK                    0x00080000L
+#define MCLK_CNTL__FORCE_YCLKB                         0x00080000L
+#define MCLK_CNTL__FORCE_MC_MASK                       0x00100000L
+#define MCLK_CNTL__FORCE_MC                            0x00100000L
+#define MCLK_CNTL__FORCE_AIC_MASK                      0x00200000L
+#define MCLK_CNTL__FORCE_AIC                           0x00200000L
+#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK                        0x03000000L
+#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK                        0x0c000000L
+#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK                        0x30000000L
+#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK                        0xc0000000L
+#define MCLK_CNTL__R300_DISABLE_MC_MCLKA               (1 << 21)
+#define MCLK_CNTL__R300_DISABLE_MC_MCLKB               (1 << 21)
+
+/* MCLK_MISC */
+#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK     0x00000003L
+#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK         0x00000004L
+#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL              0x00000004L
+#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK          0x00000008L
+#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL               0x00000008L
+#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK     0x00000010L
+#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN          0x00000010L
+#define MCLK_MISC__DLL_READY_LAT_MASK                  0x00000100L
+#define MCLK_MISC__DLL_READY_LAT                       0x00000100L
+#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK       0x00001000L
+#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT            0x00001000L
+#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK       0x00002000L
+#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT            0x00002000L
+#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK             0x00004000L
+#define MCLK_MISC__MC_MCLK_DYN_ENABLE                  0x00004000L
+#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK             0x00008000L
+#define MCLK_MISC__IO_MCLK_DYN_ENABLE                  0x00008000L
+#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK              0x00010000L
+#define MCLK_MISC__CGM_CLK_TO_OUTPIN                   0x00010000L
+#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK               0x00020000L
+#define MCLK_MISC__CLK_OR_COUNT_SEL                    0x00020000L
+#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK    0x00040000L
+#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND         0x00040000L
+#define MCLK_MISC__CGM_SPARE_RD_MASK                   0x00300000L
+#define MCLK_MISC__CGM_SPARE_A_RD_MASK                 0x00c00000L
+#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK               0x01000000L
+#define MCLK_MISC__TCLK_TO_YCLKB_EN                    0x01000000L
+#define MCLK_MISC__CGM_SPARE_A_MASK                    0x0e000000L
+
+/* VCLK_ECP_CNTL */
+#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK               0x00000003L
+#define VCLK_ECP_CNTL__VCLK_INVERT                     0x00000010L
+#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT               0x00000020L
+#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb               0x00000040L
+#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb           0x00000080L
+#define VCLK_ECP_CNTL__ECP_DIV_MASK                    0x00000300L
+#define VCLK_ECP_CNTL__ECP_FORCE_ON                    0x00040000L
+#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON                 0x00080000L
 #define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF  (1<<23)
 
-// PLL_PWRMGT_CNTL
-#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK                 0x00000001L
-#define PLL_PWRMGT_CNTL__MPLL_TURNOFF                      0x00000001L
-#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK                 0x00000002L
-#define PLL_PWRMGT_CNTL__SPLL_TURNOFF                      0x00000002L
-#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK                 0x00000004L
-#define PLL_PWRMGT_CNTL__PPLL_TURNOFF                      0x00000004L
-#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK                0x00000008L
-#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF                     0x00000008L
-#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK                0x00000010L
-#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF                     0x00000010L
-#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK          0x000001e0L
-#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK              0x00000600L
-#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK              0x00001800L
-#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK                  0x00002000L
-#define PLL_PWRMGT_CNTL__PM_MODE_SEL                       0x00002000L
-#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK          0x00004000L
-#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND               0x00004000L
-#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK          0x00008000L
-#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND               0x00008000L
-#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK                    0x00010000L
-#define PLL_PWRMGT_CNTL__MOBILE_SU                         0x00010000L
-#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK             0x00020000L
-#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK                  0x00020000L
-#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK             0x00040000L
-#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK                  0x00040000L
-#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK           0x00080000L
-#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE                0x00080000L
-#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK           0x00100000L
-#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE                0x00100000L
-#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK          0x00200000L
-#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD               0x00200000L
-#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK                 0xff000000L
-
-// CLK_PWRMGT_CNTL
-#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK           0x00000001L
-#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF                0x00000001L
-#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK           0x00000002L
-#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF                0x00000002L
-#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK           0x00000004L
-#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF                0x00000004L
-#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK          0x00000008L
-#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF               0x00000008L
-#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK              0x00000010L
-#define CLK_PWRMGT_CNTL__MCLK_TURNOFF                   0x00000010L
-#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK              0x00000020L
-#define CLK_PWRMGT_CNTL__SCLK_TURNOFF                   0x00000020L
-#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK              0x00000040L
-#define CLK_PWRMGT_CNTL__PCLK_TURNOFF                   0x00000040L
-#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK             0x00000080L
-#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF                  0x00000080L
-#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK                0x00000100L
-#define CLK_PWRMGT_CNTL__MC_CH_MODE                     0x00000100L
-#define CLK_PWRMGT_CNTL__TEST_MODE_MASK                 0x00000200L
-#define CLK_PWRMGT_CNTL__TEST_MODE                      0x00000200L
-#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK            0x00000400L
-#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN                 0x00000400L
-#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK        0x00001000L
-#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE             0x00001000L
-#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK           0x00006000L
-#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK         0x00008000L
-#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT              0x00008000L
-#define CLK_PWRMGT_CNTL__MC_BUSY_MASK                   0x00010000L
-#define CLK_PWRMGT_CNTL__MC_BUSY                        0x00010000L
-#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK               0x00020000L
-#define CLK_PWRMGT_CNTL__MC_INT_CNTL                    0x00020000L
-#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK                 0x00040000L
-#define CLK_PWRMGT_CNTL__MC_SWITCH                      0x00040000L
-#define CLK_PWRMGT_CNTL__DLL_READY_MASK                 0x00080000L
-#define CLK_PWRMGT_CNTL__DLL_READY                      0x00080000L
-#define CLK_PWRMGT_CNTL__DISP_PM_MASK                   0x00100000L
-#define CLK_PWRMGT_CNTL__DISP_PM                        0x00100000L
-#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK             0x00e00000L
-#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK              0x3f000000L
-#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK          0x40000000L
-#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF               0x40000000L
-#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK             0x80000000L
-#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF                  0x80000000L
-
-// BUS_CNTL1
-#define BUS_CNTL1__PMI_IO_DISABLE_MASK                     0x00000001L
-#define BUS_CNTL1__PMI_IO_DISABLE                          0x00000001L
-#define BUS_CNTL1__PMI_MEM_DISABLE_MASK                    0x00000002L
-#define BUS_CNTL1__PMI_MEM_DISABLE                         0x00000002L
-#define BUS_CNTL1__PMI_BM_DISABLE_MASK                     0x00000004L
-#define BUS_CNTL1__PMI_BM_DISABLE                          0x00000004L
-#define BUS_CNTL1__PMI_INT_DISABLE_MASK                    0x00000008L
-#define BUS_CNTL1__PMI_INT_DISABLE                         0x00000008L
-#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK         0x00000020L
-#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE              0x00000020L
-#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK         0x00000100L
-#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS              0x00000100L
-#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK         0x00000200L
-#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS              0x00000200L
-#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK         0x00000400L
-#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS              0x00000400L
-#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK   0x00000800L
-#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS        0x00000800L
-#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK                0x0c000000L
-#define BUS_CNTL1__SEND_SBA_LATENCY_MASK                   0x70000000L
-#define BUS_CNTL1__AGPCLK_VALID_MASK                       0x80000000L
-#define BUS_CNTL1__AGPCLK_VALID                            0x80000000L
-
-// BUS_CNTL1
-#define        BUS_CNTL1__PMI_IO_DISABLE__SHIFT                   0x00000000
-#define        BUS_CNTL1__PMI_MEM_DISABLE__SHIFT                  0x00000001
-#define        BUS_CNTL1__PMI_BM_DISABLE__SHIFT                   0x00000002
-#define        BUS_CNTL1__PMI_INT_DISABLE__SHIFT                  0x00000003
-#define        BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT       0x00000005
-#define        BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT       0x00000008
-#define        BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT       0x00000009
-#define        BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT       0x0000000a
-#define        BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b
-#define        BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT              0x0000001a
-#define        BUS_CNTL1__SEND_SBA_LATENCY__SHIFT                 0x0000001c
-#define        BUS_CNTL1__AGPCLK_VALID__SHIFT                     0x0000001f
-
-// CRTC_OFFSET_CNTL
-#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK              0x0000000fL
-#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK        0x000000f0L
-#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK          0x00004000L
-#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT               0x00004000L
-#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK                0x00008000L
-#define CRTC_OFFSET_CNTL__CRTC_TILE_EN                     0x00008000L
-#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK       0x00010000L
-#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL            0x00010000L
-#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK       0x00020000L
-#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN            0x00020000L
-#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK         0x000c0000L
-#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK     0x00100000L
-#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN          0x00100000L
-#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK            0x00200000L
-#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC                 0x00200000L
+/* PLL_PWRMGT_CNTL */
+#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK             0x00000001L
+#define PLL_PWRMGT_CNTL__MPLL_TURNOFF                  0x00000001L
+#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK             0x00000002L
+#define PLL_PWRMGT_CNTL__SPLL_TURNOFF                  0x00000002L
+#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK             0x00000004L
+#define PLL_PWRMGT_CNTL__PPLL_TURNOFF                  0x00000004L
+#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK            0x00000008L
+#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF                 0x00000008L
+#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK            0x00000010L
+#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF                 0x00000010L
+#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK      0x000001e0L
+#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK          0x00000600L
+#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK          0x00001800L
+#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK              0x00002000L
+#define PLL_PWRMGT_CNTL__PM_MODE_SEL                   0x00002000L
+#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK      0x00004000L
+#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND           0x00004000L
+#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK      0x00008000L
+#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND           0x00008000L
+#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK                        0x00010000L
+#define PLL_PWRMGT_CNTL__MOBILE_SU                     0x00010000L
+#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK         0x00020000L
+#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK              0x00020000L
+#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK         0x00040000L
+#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK              0x00040000L
+#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK       0x00080000L
+#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE            0x00080000L
+#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK       0x00100000L
+#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE            0x00100000L
+#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK       0x00200000L
+#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD           0x00200000L
+#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK             0xff000000L
+
+/* CLK_PWRMGT_CNTL */
+#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK          0x00000001L
+#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF               0x00000001L
+#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK          0x00000002L
+#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF               0x00000002L
+#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK          0x00000004L
+#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF               0x00000004L
+#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK         0x00000008L
+#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF              0x00000008L
+#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK             0x00000010L
+#define CLK_PWRMGT_CNTL__MCLK_TURNOFF                  0x00000010L
+#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK             0x00000020L
+#define CLK_PWRMGT_CNTL__SCLK_TURNOFF                  0x00000020L
+#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK             0x00000040L
+#define CLK_PWRMGT_CNTL__PCLK_TURNOFF                  0x00000040L
+#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK            0x00000080L
+#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF                 0x00000080L
+#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK               0x00000100L
+#define CLK_PWRMGT_CNTL__MC_CH_MODE                    0x00000100L
+#define CLK_PWRMGT_CNTL__TEST_MODE_MASK                        0x00000200L
+#define CLK_PWRMGT_CNTL__TEST_MODE                     0x00000200L
+#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK           0x00000400L
+#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN                        0x00000400L
+#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK       0x00001000L
+#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE            0x00001000L
+#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK          0x00006000L
+#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK                0x00008000L
+#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT             0x00008000L
+#define CLK_PWRMGT_CNTL__MC_BUSY_MASK                  0x00010000L
+#define CLK_PWRMGT_CNTL__MC_BUSY                       0x00010000L
+#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK              0x00020000L
+#define CLK_PWRMGT_CNTL__MC_INT_CNTL                   0x00020000L
+#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK                        0x00040000L
+#define CLK_PWRMGT_CNTL__MC_SWITCH                     0x00040000L
+#define CLK_PWRMGT_CNTL__DLL_READY_MASK                        0x00080000L
+#define CLK_PWRMGT_CNTL__DLL_READY                     0x00080000L
+#define CLK_PWRMGT_CNTL__DISP_PM_MASK                  0x00100000L
+#define CLK_PWRMGT_CNTL__DISP_PM                       0x00100000L
+#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK            0x00e00000L
+#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK             0x3f000000L
+#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK         0x40000000L
+#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF              0x40000000L
+#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK            0x80000000L
+#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF                 0x80000000L
+
+/* BUS_CNTL1 */
+#define BUS_CNTL1__PMI_IO_DISABLE_MASK                 0x00000001L
+#define BUS_CNTL1__PMI_IO_DISABLE                      0x00000001L
+#define BUS_CNTL1__PMI_MEM_DISABLE_MASK                        0x00000002L
+#define BUS_CNTL1__PMI_MEM_DISABLE                     0x00000002L
+#define BUS_CNTL1__PMI_BM_DISABLE_MASK                 0x00000004L
+#define BUS_CNTL1__PMI_BM_DISABLE                      0x00000004L
+#define BUS_CNTL1__PMI_INT_DISABLE_MASK                        0x00000008L
+#define BUS_CNTL1__PMI_INT_DISABLE                     0x00000008L
+#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK     0x00000020L
+#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE          0x00000020L
+#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK     0x00000100L
+#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS          0x00000100L
+#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK     0x00000200L
+#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS          0x00000200L
+#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK     0x00000400L
+#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS          0x00000400L
+#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L
+#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS    0x00000800L
+#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK            0x0c000000L
+#define BUS_CNTL1__SEND_SBA_LATENCY_MASK               0x70000000L
+#define BUS_CNTL1__AGPCLK_VALID_MASK                   0x80000000L
+#define BUS_CNTL1__AGPCLK_VALID                                0x80000000L
+
+/* BUS_CNTL1 */
+#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT               0x00000000
+#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT              0x00000001
+#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT               0x00000002
+#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT              0x00000003
+#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT   0x00000005
+#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT   0x00000008
+#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT   0x00000009
+#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT   0x0000000a
+#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b
+#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT          0x0000001a
+#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT             0x0000001c
+#define BUS_CNTL1__AGPCLK_VALID__SHIFT                 0x0000001f
+
+/* CRTC_OFFSET_CNTL */
+#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK          0x0000000fL
+#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK    0x000000f0L
+#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK      0x00004000L
+#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT           0x00004000L
+#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK            0x00008000L
+#define CRTC_OFFSET_CNTL__CRTC_TILE_EN                 0x00008000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK   0x00010000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL                0x00010000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK   0x00020000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN                0x00020000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK     0x000c0000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN      0x00100000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK                0x00200000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC             0x00200000L
 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L
-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN     0x10000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L
 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L
-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN    0x20000000L
-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK        0x40000000L
-#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET             0x40000000L
-#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK            0x80000000L
-#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK                 0x80000000L
-
-// CRTC_GEN_CNTL
-#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK               0x00000001L
-#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN                    0x00000001L
-#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK              0x00000002L
-#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN                   0x00000002L
-#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK                 0x00000010L
-#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN                      0x00000010L
-#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK                 0x00000f00L
-#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK                   0x00008000L
-#define CRTC_GEN_CNTL__CRTC_ICON_EN                        0x00008000L
-#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK                    0x00010000L
-#define CRTC_GEN_CNTL__CRTC_CUR_EN                         0x00010000L
-#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK                0x00060000L
-#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK                  0x00700000L
-#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK               0x01000000L
-#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN                    0x01000000L
-#define CRTC_GEN_CNTL__CRTC_EN_MASK                        0x02000000L
-#define CRTC_GEN_CNTL__CRTC_EN                             0x02000000L
-#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK             0x04000000L
-#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B                  0x04000000L
-
-// CRTC2_GEN_CNTL
-#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK             0x00000001L
-#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN                  0x00000001L
-#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK            0x00000002L
-#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN                 0x00000002L
-#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK           0x00000010L
-#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE                0x00000010L
-#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK          0x00000020L
-#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE               0x00000020L
-#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK          0x00000040L
-#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE               0x00000040L
-#define CRTC2_GEN_CNTL__CRT2_ON_MASK                       0x00000080L
-#define CRTC2_GEN_CNTL__CRT2_ON                            0x00000080L
-#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK               0x00000f00L
-#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK                 0x00008000L
-#define CRTC2_GEN_CNTL__CRTC2_ICON_EN                      0x00008000L
-#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK                  0x00010000L
-#define CRTC2_GEN_CNTL__CRTC2_CUR_EN                       0x00010000L
-#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK                0x00700000L
-#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK             0x00800000L
-#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS                  0x00800000L
-#define CRTC2_GEN_CNTL__CRTC2_EN_MASK                      0x02000000L
-#define CRTC2_GEN_CNTL__CRTC2_EN                           0x02000000L
-#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK           0x04000000L
-#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B                0x04000000L
-#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK               0x08000000L
-#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN                    0x08000000L
-#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK               0x10000000L
-#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS                    0x10000000L
-#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK               0x20000000L
-#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS                    0x20000000L
-
-// AGP_CNTL
-#define AGP_CNTL__MAX_IDLE_CLK_MASK                        0x000000ffL
-#define AGP_CNTL__HOLD_RD_FIFO_MASK                        0x00000100L
-#define AGP_CNTL__HOLD_RD_FIFO                             0x00000100L
-#define AGP_CNTL__HOLD_RQ_FIFO_MASK                        0x00000200L
-#define AGP_CNTL__HOLD_RQ_FIFO                             0x00000200L
-#define AGP_CNTL__EN_2X_STBB_MASK                          0x00000400L
-#define AGP_CNTL__EN_2X_STBB                               0x00000400L
-#define AGP_CNTL__FORCE_FULL_SBA_MASK                      0x00000800L
-#define AGP_CNTL__FORCE_FULL_SBA                           0x00000800L
-#define AGP_CNTL__SBA_DIS_MASK                             0x00001000L
-#define AGP_CNTL__SBA_DIS                                  0x00001000L
-#define AGP_CNTL__AGP_REV_ID_MASK                          0x00002000L
-#define AGP_CNTL__AGP_REV_ID                               0x00002000L
-#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK                   0x00004000L
-#define AGP_CNTL__REG_CRIPPLE_AGP4X                        0x00004000L
-#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK                 0x00008000L
-#define AGP_CNTL__REG_CRIPPLE_AGP2X4X                      0x00008000L
-#define AGP_CNTL__FORCE_INT_VREF_MASK                      0x00010000L
-#define AGP_CNTL__FORCE_INT_VREF                           0x00010000L
-#define AGP_CNTL__PENDING_SLOTS_VAL_MASK                   0x00060000L
-#define AGP_CNTL__PENDING_SLOTS_SEL_MASK                   0x00080000L
-#define AGP_CNTL__PENDING_SLOTS_SEL                        0x00080000L
-#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK               0x00100000L
-#define AGP_CNTL__EN_EXTENDED_AD_STB_2X                    0x00100000L
-#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK                  0x00200000L
-#define AGP_CNTL__DIS_QUEUED_GNT_FIX                       0x00200000L
-#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK             0x00400000L
-#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET                  0x00400000L
-#define AGP_CNTL__EN_RBFCALM_MASK                          0x00800000L
-#define AGP_CNTL__EN_RBFCALM                               0x00800000L
-#define AGP_CNTL__FORCE_EXT_VREF_MASK                      0x01000000L
-#define AGP_CNTL__FORCE_EXT_VREF                           0x01000000L
-#define AGP_CNTL__DIS_RBF_MASK                             0x02000000L
-#define AGP_CNTL__DIS_RBF                                  0x02000000L
-#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK                  0x04000000L
-#define AGP_CNTL__DELAY_FIRST_SBA_EN                       0x04000000L
-#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK                 0x38000000L
-#define AGP_CNTL__AGP_MISC_MASK                            0xc0000000L
-
-// AGP_CNTL
-#define        AGP_CNTL__MAX_IDLE_CLK__SHIFT                      0x00000000
-#define        AGP_CNTL__HOLD_RD_FIFO__SHIFT                      0x00000008
-#define        AGP_CNTL__HOLD_RQ_FIFO__SHIFT                      0x00000009
-#define        AGP_CNTL__EN_2X_STBB__SHIFT                        0x0000000a
-#define        AGP_CNTL__FORCE_FULL_SBA__SHIFT                    0x0000000b
-#define        AGP_CNTL__SBA_DIS__SHIFT                           0x0000000c
-#define        AGP_CNTL__AGP_REV_ID__SHIFT                        0x0000000d
-#define        AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT                 0x0000000e
-#define        AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT               0x0000000f
-#define        AGP_CNTL__FORCE_INT_VREF__SHIFT                    0x00000010
-#define        AGP_CNTL__PENDING_SLOTS_VAL__SHIFT                 0x00000011
-#define        AGP_CNTL__PENDING_SLOTS_SEL__SHIFT                 0x00000013
-#define        AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT             0x00000014
-#define        AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT                0x00000015
-#define        AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT           0x00000016
-#define        AGP_CNTL__EN_RBFCALM__SHIFT                        0x00000017
-#define        AGP_CNTL__FORCE_EXT_VREF__SHIFT                    0x00000018
-#define        AGP_CNTL__DIS_RBF__SHIFT                           0x00000019
-#define        AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT                0x0000001a
-#define        AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT               0x0000001b
-#define        AGP_CNTL__AGP_MISC__SHIFT                          0x0000001e
-
-// DISP_MISC_CNTL
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK            0x00000001L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP                 0x00000001L
-#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK          0x00000002L
-#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP               0x00000002L
-#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK             0x00000004L
-#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP                  0x00000004L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK          0x00000010L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK               0x00000010L
-#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK        0x00000020L
-#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK             0x00000020L
-#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK           0x00000040L
-#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK                0x00000040L
-#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK                 0x00000300L
-#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK              0x00000400L
-#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN                   0x00000400L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK           0x00001000L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP                0x00001000L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK         0x00008000L
-#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK              0x00008000L
-#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK               0x00010000L
-#define DISP_MISC_CNTL__SOFT_RESET_LVDS                    0x00010000L
-#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK               0x00020000L
-#define DISP_MISC_CNTL__SOFT_RESET_TMDS                    0x00020000L
-#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK           0x00040000L
-#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS                0x00040000L
-#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK                 0x00080000L
-#define DISP_MISC_CNTL__SOFT_RESET_TV                      0x00080000L
-#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK        0x00f00000L
-#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK         0x0f000000L
-#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK         0xf0000000L
-
-// DISP_PWR_MAN
-#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK         0x00000001L
-#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN              0x00000001L
-#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK       0x00000010L
-#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN            0x00000010L
-#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK               0x00000300L
-#define DISP_PWR_MAN__DISP_D3_RST_MASK                     0x00010000L
-#define DISP_PWR_MAN__DISP_D3_RST                          0x00010000L
-#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK                 0x00020000L
-#define DISP_PWR_MAN__DISP_D3_REG_RST                      0x00020000L
-#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK                0x00040000L
-#define DISP_PWR_MAN__DISP_D3_GRPH_RST                     0x00040000L
-#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK              0x00080000L
-#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST                   0x00080000L
-#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK                 0x00100000L
-#define DISP_PWR_MAN__DISP_D3_OV0_RST                      0x00100000L
-#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK              0x00200000L
-#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST                   0x00200000L
-#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK            0x00400000L
-#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST                 0x00400000L
-#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK               0x00800000L
-#define DISP_PWR_MAN__DISP_D1D2_OV0_RST                    0x00800000L
-#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK             0x01000000L
-#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST                  0x01000000L
-#define DISP_PWR_MAN__TV_ENABLE_RST_MASK                   0x02000000L
-#define DISP_PWR_MAN__TV_ENABLE_RST                        0x02000000L
-#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK                   0x04000000L
-#define DISP_PWR_MAN__AUTO_PWRUP_EN                        0x04000000L
-
-// MC_IND_INDEX
-#define MC_IND_INDEX__MC_IND_ADDR_MASK                     0x0000001fL
-#define MC_IND_INDEX__MC_IND_WR_EN_MASK                    0x00000100L
-#define MC_IND_INDEX__MC_IND_WR_EN                         0x00000100L
-
-// MC_IND_DATA
-#define MC_IND_DATA__MC_IND_DATA_MASK                      0xffffffffL
-
-// MC_CHP_IO_CNTL_A1
-#define        MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT            0x00000000
-#define        MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT             0x00000001
-#define        MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT           0x00000002
-#define        MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT           0x00000003
-#define        MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT            0x00000004
-#define        MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT             0x00000005
-#define        MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT           0x00000006
-#define        MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT           0x00000007
-#define        MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT            0x00000008
-#define        MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT          0x00000009
-#define        MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT          0x0000000a
-#define        MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT             0x0000000c
-#define        MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT              0x0000000e
-#define        MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT               0x00000010
-#define        MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT             0x00000012
-#define        MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT             0x00000014
-#define        MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT          0x00000016
-#define        MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT         0x00000017
-#define        MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT             0x00000018
-#define        MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT             0x0000001a
-#define        MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT             0x0000001c
-#define        MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT         0x0000001e
-#define        MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT         0x0000001f
-
-// MC_CHP_IO_CNTL_B1
-#define        MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT            0x00000000
-#define        MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT             0x00000001
-#define        MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT           0x00000002
-#define        MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT           0x00000003
-#define        MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT            0x00000004
-#define        MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT             0x00000005
-#define        MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT           0x00000006
-#define        MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT           0x00000007
-#define        MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT            0x00000008
-#define        MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT          0x00000009
-#define        MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT          0x0000000a
-#define        MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT             0x0000000c
-#define        MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT              0x0000000e
-#define        MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT               0x00000010
-#define        MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT             0x00000012
-#define        MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT             0x00000014
-#define        MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT          0x00000016
-#define        MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT         0x00000017
-#define        MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT             0x00000018
-#define        MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT             0x0000001a
-#define        MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT             0x0000001c
-#define        MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT         0x0000001e
-#define        MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT         0x0000001f
-
-// MC_CHP_IO_CNTL_A1
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK              0x00000001L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA                   0x00000001L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK               0x00000002L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA                    0x00000002L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK             0x00000004L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA                  0x00000004L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK             0x00000008L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA                  0x00000008L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK              0x00000010L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA                   0x00000010L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK               0x00000020L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA                    0x00000020L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK             0x00000040L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA                  0x00000040L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK             0x00000080L
-#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA                  0x00000080L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK              0x00000100L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA                   0x00000100L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK            0x00000200L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA                 0x00000200L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK            0x00000400L
-#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA                 0x00000400L
-#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK               0x00003000L
-#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK                0x0000c000L
-#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK                 0x00030000L
-#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK               0x000c0000L
-#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK               0x00300000L
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK            0x00400000L
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA                 0x00400000L
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK           0x00800000L
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA                0x00800000L
-#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK               0x03000000L
-#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK               0x0c000000L
-#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK               0x10000000L
-#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA                    0x10000000L
-#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK           0x40000000L
-#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A                0x40000000L
-#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK           0x80000000L
-#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A                0x80000000L
-
-// MC_CHP_IO_CNTL_B1
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK              0x00000001L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB                   0x00000001L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK               0x00000002L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB                    0x00000002L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK             0x00000004L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB                  0x00000004L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK             0x00000008L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB                  0x00000008L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK              0x00000010L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB                   0x00000010L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK               0x00000020L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB                    0x00000020L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK             0x00000040L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB                  0x00000040L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK             0x00000080L
-#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB                  0x00000080L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK              0x00000100L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB                   0x00000100L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK            0x00000200L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB                 0x00000200L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK            0x00000400L
-#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB                 0x00000400L
-#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK               0x00003000L
-#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK                0x0000c000L
-#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK                 0x00030000L
-#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK               0x000c0000L
-#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK               0x00300000L
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK            0x00400000L
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB                 0x00400000L
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK           0x00800000L
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB                0x00800000L
-#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK               0x03000000L
-#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK               0x0c000000L
-#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK               0x10000000L
-#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB                    0x10000000L
-#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK           0x40000000L
-#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B                0x40000000L
-#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK           0x80000000L
-#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B                0x80000000L
-
-// MEM_SDRAM_MODE_REG
-#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK              0x00007fffL
-#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK            0x000f0000L
-#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK           0x00700000L
-#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK           0x00800000L
-#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY                0x00800000L
-#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK           0x01000000L
-#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY                0x01000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK          0x02000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD               0x02000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK         0x04000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA              0x04000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK          0x08000000L
-#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR               0x08000000L
-#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK          0x10000000L
-#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE               0x10000000L
-#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK               0x20000000L
-#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL                    0x20000000L
-#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK              0x40000000L
-#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE                   0x40000000L
-#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK           0x80000000L
-#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET                0x80000000L
-
-// MEM_SDRAM_MODE_REG
-#define        MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT            0x00000000
-#define        MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT          0x00000010
-#define        MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT         0x00000014
-#define        MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT         0x00000017
-#define        MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT         0x00000018
-#define        MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT        0x00000019
-#define        MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT       0x0000001a
-#define        MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT        0x0000001b
-#define        MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT        0x0000001c
-#define        MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT             0x0000001d
-#define        MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT            0x0000001e
-#define        MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT         0x0000001f
-
-// MEM_REFRESH_CNTL
-#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK            0x000000ffL
-#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK             0x00000100L
-#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS                  0x00000100L
-#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK             0x00000200L
-#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE                  0x00000200L
-#define MEM_REFRESH_CNTL__MEM_TRFC_MASK                    0x0000f000L
-#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK            0x00010000L
-#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE                 0x00010000L
-#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK           0x00020000L
-#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE                0x00020000L
-#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK            0x00040000L
-#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE                 0x00040000L
-#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK           0x00080000L
-#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE                0x00080000L
-#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK           0x00100000L
-#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE                0x00100000L
-#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK             0x00c00000L
-#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK            0x01000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE                 0x01000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK           0x02000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE                0x02000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK            0x04000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE                 0x04000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK           0x08000000L
-#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE                0x08000000L
-#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK           0x10000000L
-#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE                0x10000000L
-#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK             0xc0000000L
-
-// MC_STATUS
-#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK                  0x00000001L
-#define MC_STATUS__MEM_PWRUP_COMPL_A                       0x00000001L
-#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK                  0x00000002L
-#define MC_STATUS__MEM_PWRUP_COMPL_B                       0x00000002L
-#define MC_STATUS__MC_IDLE_MASK                            0x00000004L
-#define MC_STATUS__MC_IDLE                                 0x00000004L
-#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK                 0x00000078L
-#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK                 0x00000780L
-#define MC_STATUS__TEST_OUT_R_BACK_MASK                    0x00000800L
-#define MC_STATUS__TEST_OUT_R_BACK                         0x00000800L
-#define MC_STATUS__DUMMY_OUT_R_BACK_MASK                   0x00001000L
-#define MC_STATUS__DUMMY_OUT_R_BACK                        0x00001000L
-#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK               0x0001e000L
-#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK               0x001e0000L
-#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK              0x01e00000L
-#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK              0x1e000000L
-
-// MDLL_CKO
-#define MDLL_CKO__MCKOA_SLEEP_MASK                         0x00000001L
-#define MDLL_CKO__MCKOA_SLEEP                              0x00000001L
-#define MDLL_CKO__MCKOA_RESET_MASK                         0x00000002L
-#define MDLL_CKO__MCKOA_RESET                              0x00000002L
-#define MDLL_CKO__MCKOA_RANGE_MASK                         0x0000000cL
-#define MDLL_CKO__ERSTA_SOUTSEL_MASK                       0x00000030L
-#define MDLL_CKO__MCKOA_FB_SEL_MASK                        0x000000c0L
-#define MDLL_CKO__MCKOA_REF_SKEW_MASK                      0x00000700L
-#define MDLL_CKO__MCKOA_FB_SKEW_MASK                       0x00007000L
-#define MDLL_CKO__MCKOA_BP_SEL_MASK                        0x00008000L
-#define MDLL_CKO__MCKOA_BP_SEL                             0x00008000L
-#define MDLL_CKO__MCKOB_SLEEP_MASK                         0x00010000L
-#define MDLL_CKO__MCKOB_SLEEP                              0x00010000L
-#define MDLL_CKO__MCKOB_RESET_MASK                         0x00020000L
-#define MDLL_CKO__MCKOB_RESET                              0x00020000L
-#define MDLL_CKO__MCKOB_RANGE_MASK                         0x000c0000L
-#define MDLL_CKO__ERSTB_SOUTSEL_MASK                       0x00300000L
-#define MDLL_CKO__MCKOB_FB_SEL_MASK                        0x00c00000L
-#define MDLL_CKO__MCKOB_REF_SKEW_MASK                      0x07000000L
-#define MDLL_CKO__MCKOB_FB_SKEW_MASK                       0x70000000L
-#define MDLL_CKO__MCKOB_BP_SEL_MASK                        0x80000000L
-#define MDLL_CKO__MCKOB_BP_SEL                             0x80000000L
-
-// MDLL_RDCKA
-#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK                     0x00000001L
-#define MDLL_RDCKA__MRDCKA0_SLEEP                          0x00000001L
-#define MDLL_RDCKA__MRDCKA0_RESET_MASK                     0x00000002L
-#define MDLL_RDCKA__MRDCKA0_RESET                          0x00000002L
-#define MDLL_RDCKA__MRDCKA0_RANGE_MASK                     0x0000000cL
-#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK                   0x00000030L
-#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK                    0x000000c0L
-#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK                  0x00000700L
-#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK                    0x00000800L
-#define MDLL_RDCKA__MRDCKA0_SINSEL                         0x00000800L
-#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK                   0x00007000L
-#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK                    0x00008000L
-#define MDLL_RDCKA__MRDCKA0_BP_SEL                         0x00008000L
-#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK                     0x00010000L
-#define MDLL_RDCKA__MRDCKA1_SLEEP                          0x00010000L
-#define MDLL_RDCKA__MRDCKA1_RESET_MASK                     0x00020000L
-#define MDLL_RDCKA__MRDCKA1_RESET                          0x00020000L
-#define MDLL_RDCKA__MRDCKA1_RANGE_MASK                     0x000c0000L
-#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK                   0x00300000L
-#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK                    0x00c00000L
-#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK                  0x07000000L
-#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK                    0x08000000L
-#define MDLL_RDCKA__MRDCKA1_SINSEL                         0x08000000L
-#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK                   0x70000000L
-#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK                    0x80000000L
-#define MDLL_RDCKA__MRDCKA1_BP_SEL                         0x80000000L
-
-// MDLL_RDCKB
-#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK                     0x00000001L
-#define MDLL_RDCKB__MRDCKB0_SLEEP                          0x00000001L
-#define MDLL_RDCKB__MRDCKB0_RESET_MASK                     0x00000002L
-#define MDLL_RDCKB__MRDCKB0_RESET                          0x00000002L
-#define MDLL_RDCKB__MRDCKB0_RANGE_MASK                     0x0000000cL
-#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK                   0x00000030L
-#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK                    0x000000c0L
-#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK                  0x00000700L
-#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK                    0x00000800L
-#define MDLL_RDCKB__MRDCKB0_SINSEL                         0x00000800L
-#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK                   0x00007000L
-#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK                    0x00008000L
-#define MDLL_RDCKB__MRDCKB0_BP_SEL                         0x00008000L
-#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK                     0x00010000L
-#define MDLL_RDCKB__MRDCKB1_SLEEP                          0x00010000L
-#define MDLL_RDCKB__MRDCKB1_RESET_MASK                     0x00020000L
-#define MDLL_RDCKB__MRDCKB1_RESET                          0x00020000L
-#define MDLL_RDCKB__MRDCKB1_RANGE_MASK                     0x000c0000L
-#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK                   0x00300000L
-#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK                    0x00c00000L
-#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK                  0x07000000L
-#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK                    0x08000000L
-#define MDLL_RDCKB__MRDCKB1_SINSEL                         0x08000000L
-#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK                   0x70000000L
-#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK                    0x80000000L
-#define MDLL_RDCKB__MRDCKB1_BP_SEL                         0x80000000L
-
-#define MDLL_R300_RDCK__MRDCKA_SLEEP                       0x00000001L
-#define MDLL_R300_RDCK__MRDCKA_RESET                       0x00000002L
-#define MDLL_R300_RDCK__MRDCKB_SLEEP                       0x00000004L
-#define MDLL_R300_RDCK__MRDCKB_RESET                       0x00000008L
-#define MDLL_R300_RDCK__MRDCKC_SLEEP                       0x00000010L
-#define MDLL_R300_RDCK__MRDCKC_RESET                       0x00000020L
-#define MDLL_R300_RDCK__MRDCKD_SLEEP                       0x00000040L
-#define MDLL_R300_RDCK__MRDCKD_RESET                       0x00000080L
-
-#define pllCLK_PIN_CNTL                             0x0001
-#define pllPPLL_CNTL                                0x0002
-#define pllPPLL_REF_DIV                             0x0003
-#define pllPPLL_DIV_0                               0x0004
-#define pllPPLL_DIV_1                               0x0005
-#define pllPPLL_DIV_2                               0x0006
-#define pllPPLL_DIV_3                               0x0007
-#define pllVCLK_ECP_CNTL                            0x0008
-#define pllHTOTAL_CNTL                              0x0009
-#define pllM_SPLL_REF_FB_DIV                        0x000A
-#define pllAGP_PLL_CNTL                             0x000B
-#define pllSPLL_CNTL                                0x000C
-#define pllSCLK_CNTL                                0x000D
-#define pllMPLL_CNTL                                0x000E
-#define pllMDLL_CKO                                 0x000F
-#define pllMDLL_RDCKA                               0x0010
-#define pllMDLL_RDCKB                               0x0011
-#define pllMCLK_CNTL                                0x0012
-#define pllPLL_TEST_CNTL                            0x0013
-#define pllCLK_PWRMGT_CNTL                          0x0014
-#define pllPLL_PWRMGT_CNTL                          0x0015
-#define pllCG_TEST_MACRO_RW_WRITE                   0x0016
-#define pllCG_TEST_MACRO_RW_READ                    0x0017
-#define pllCG_TEST_MACRO_RW_DATA                    0x0018
-#define pllCG_TEST_MACRO_RW_CNTL                    0x0019
-#define pllDISP_TEST_MACRO_RW_WRITE                 0x001A
-#define pllDISP_TEST_MACRO_RW_READ                  0x001B
-#define pllDISP_TEST_MACRO_RW_DATA                  0x001C
-#define pllDISP_TEST_MACRO_RW_CNTL                  0x001D
-#define pllSCLK_CNTL2                               0x001E
-#define pllMCLK_MISC                                0x001F
-#define pllTV_PLL_FINE_CNTL                         0x0020
-#define pllTV_PLL_CNTL                              0x0021
-#define pllTV_PLL_CNTL1                             0x0022
-#define pllTV_DTO_INCREMENTS                        0x0023
-#define pllSPLL_AUX_CNTL                            0x0024
-#define pllMPLL_AUX_CNTL                            0x0025
-#define pllP2PLL_CNTL                               0x002A
-#define pllP2PLL_REF_DIV                            0x002B
-#define pllP2PLL_DIV_0                              0x002C
-#define pllPIXCLKS_CNTL                             0x002D
-#define pllHTOTAL2_CNTL                             0x002E
-#define pllSSPLL_CNTL                               0x0030
-#define pllSSPLL_REF_DIV                            0x0031
-#define pllSSPLL_DIV_0                              0x0032
-#define pllSS_INT_CNTL                              0x0033
-#define pllSS_TST_CNTL                              0x0034
-#define pllSCLK_MORE_CNTL                           0x0035
-
-#define ixMC_PERF_CNTL                             0x0000
-#define ixMC_PERF_SEL                              0x0001
-#define ixMC_PERF_REGION_0                         0x0002
-#define ixMC_PERF_REGION_1                         0x0003
-#define ixMC_PERF_COUNT_0                          0x0004
-#define ixMC_PERF_COUNT_1                          0x0005
-#define ixMC_PERF_COUNT_2                          0x0006
-#define ixMC_PERF_COUNT_3                          0x0007
-#define ixMC_PERF_COUNT_MEMCH_A                    0x0008
-#define ixMC_PERF_COUNT_MEMCH_B                    0x0009
-#define ixMC_IMP_CNTL                              0x000A
-#define ixMC_CHP_IO_CNTL_A0                        0x000B
-#define ixMC_CHP_IO_CNTL_A1                        0x000C
-#define ixMC_CHP_IO_CNTL_B0                        0x000D
-#define ixMC_CHP_IO_CNTL_B1                        0x000E
-#define ixMC_IMP_CNTL_0                            0x000F
-#define ixTC_MISMATCH_1                            0x0010
-#define ixTC_MISMATCH_2                            0x0011
-#define ixMC_BIST_CTRL                             0x0012
-#define ixREG_COLLAR_WRITE                         0x0013
-#define ixREG_COLLAR_READ                          0x0014
-#define ixR300_MC_IMP_CNTL                         0x0018
-#define ixR300_MC_CHP_IO_CNTL_A0                   0x0019
-#define ixR300_MC_CHP_IO_CNTL_A1                   0x001a
-#define ixR300_MC_CHP_IO_CNTL_B0                   0x001b
-#define ixR300_MC_CHP_IO_CNTL_B1                   0x001c
-#define ixR300_MC_CHP_IO_CNTL_C0                   0x001d
-#define ixR300_MC_CHP_IO_CNTL_C1                   0x001e
-#define ixR300_MC_CHP_IO_CNTL_D0                   0x001f
-#define ixR300_MC_CHP_IO_CNTL_D1                   0x0020
-#define ixR300_MC_IMP_CNTL_0                       0x0021
-#define ixR300_MC_ELPIDA_CNTL                      0x0022
-#define ixR300_MC_CHP_IO_OE_CNTL_CD                0x0023
-#define ixR300_MC_READ_CNTL_CD                     0x0024
-#define ixR300_MC_MC_INIT_WR_LAT_TIMER             0x0025
-#define ixR300_MC_DEBUG_CNTL                       0x0026
-#define ixR300_MC_BIST_CNTL_0                      0x0028
-#define ixR300_MC_BIST_CNTL_1                      0x0029
-#define ixR300_MC_BIST_CNTL_2                      0x002a
-#define ixR300_MC_BIST_CNTL_3                      0x002b
-#define ixR300_MC_BIST_CNTL_4                      0x002c
-#define ixR300_MC_BIST_CNTL_5                      0x002d
-#define ixR300_MC_IMP_STATUS                       0x002e
-#define ixR300_MC_DLL_CNTL                         0x002f
-#define NB_TOM                                     0x15C
-
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN        0x20000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK    0x40000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET         0x40000000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK                0x80000000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK             0x80000000L
+
+/* CRTC_GEN_CNTL */
+#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK           0x00000001L
+#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN                        0x00000001L
+#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK          0x00000002L
+#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN               0x00000002L
+#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK             0x00000010L
+#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN                  0x00000010L
+#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK             0x00000f00L
+#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK               0x00008000L
+#define CRTC_GEN_CNTL__CRTC_ICON_EN                    0x00008000L
+#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK                        0x00010000L
+#define CRTC_GEN_CNTL__CRTC_CUR_EN                     0x00010000L
+#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK            0x00060000L
+#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK              0x00700000L
+#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK           0x01000000L
+#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN                        0x01000000L
+#define CRTC_GEN_CNTL__CRTC_EN_MASK                    0x02000000L
+#define CRTC_GEN_CNTL__CRTC_EN                         0x02000000L
+#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK         0x04000000L
+#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B              0x04000000L
+
+/* CRTC2_GEN_CNTL */
+#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK         0x00000001L
+#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN              0x00000001L
+#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK                0x00000002L
+#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN             0x00000002L
+#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK       0x00000010L
+#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE            0x00000010L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK      0x00000020L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE           0x00000020L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK      0x00000040L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE           0x00000040L
+#define CRTC2_GEN_CNTL__CRT2_ON_MASK                   0x00000080L
+#define CRTC2_GEN_CNTL__CRT2_ON                                0x00000080L
+#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK           0x00000f00L
+#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK             0x00008000L
+#define CRTC2_GEN_CNTL__CRTC2_ICON_EN                  0x00008000L
+#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK              0x00010000L
+#define CRTC2_GEN_CNTL__CRTC2_CUR_EN                   0x00010000L
+#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK            0x00700000L
+#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK         0x00800000L
+#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS              0x00800000L
+#define CRTC2_GEN_CNTL__CRTC2_EN_MASK                  0x02000000L
+#define CRTC2_GEN_CNTL__CRTC2_EN                       0x02000000L
+#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK       0x04000000L
+#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B            0x04000000L
+#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK           0x08000000L
+#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN                        0x08000000L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK           0x10000000L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS                        0x10000000L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK           0x20000000L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS                        0x20000000L
+
+/* AGP_CNTL */
+#define AGP_CNTL__MAX_IDLE_CLK_MASK                    0x000000ffL
+#define AGP_CNTL__HOLD_RD_FIFO_MASK                    0x00000100L
+#define AGP_CNTL__HOLD_RD_FIFO                         0x00000100L
+#define AGP_CNTL__HOLD_RQ_FIFO_MASK                    0x00000200L
+#define AGP_CNTL__HOLD_RQ_FIFO                         0x00000200L
+#define AGP_CNTL__EN_2X_STBB_MASK                      0x00000400L
+#define AGP_CNTL__EN_2X_STBB                           0x00000400L
+#define AGP_CNTL__FORCE_FULL_SBA_MASK                  0x00000800L
+#define AGP_CNTL__FORCE_FULL_SBA                       0x00000800L
+#define AGP_CNTL__SBA_DIS_MASK                         0x00001000L
+#define AGP_CNTL__SBA_DIS                              0x00001000L
+#define AGP_CNTL__AGP_REV_ID_MASK                      0x00002000L
+#define AGP_CNTL__AGP_REV_ID                           0x00002000L
+#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK               0x00004000L
+#define AGP_CNTL__REG_CRIPPLE_AGP4X                    0x00004000L
+#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK             0x00008000L
+#define AGP_CNTL__REG_CRIPPLE_AGP2X4X                  0x00008000L
+#define AGP_CNTL__FORCE_INT_VREF_MASK                  0x00010000L
+#define AGP_CNTL__FORCE_INT_VREF                       0x00010000L
+#define AGP_CNTL__PENDING_SLOTS_VAL_MASK               0x00060000L
+#define AGP_CNTL__PENDING_SLOTS_SEL_MASK               0x00080000L
+#define AGP_CNTL__PENDING_SLOTS_SEL                    0x00080000L
+#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK           0x00100000L
+#define AGP_CNTL__EN_EXTENDED_AD_STB_2X                        0x00100000L
+#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK              0x00200000L
+#define AGP_CNTL__DIS_QUEUED_GNT_FIX                   0x00200000L
+#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK         0x00400000L
+#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET              0x00400000L
+#define AGP_CNTL__EN_RBFCALM_MASK                      0x00800000L
+#define AGP_CNTL__EN_RBFCALM                           0x00800000L
+#define AGP_CNTL__FORCE_EXT_VREF_MASK                  0x01000000L
+#define AGP_CNTL__FORCE_EXT_VREF                       0x01000000L
+#define AGP_CNTL__DIS_RBF_MASK                         0x02000000L
+#define AGP_CNTL__DIS_RBF                              0x02000000L
+#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK              0x04000000L
+#define AGP_CNTL__DELAY_FIRST_SBA_EN                   0x04000000L
+#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK             0x38000000L
+#define AGP_CNTL__AGP_MISC_MASK                                0xc0000000L
+
+/* AGP_CNTL */
+#define AGP_CNTL__MAX_IDLE_CLK__SHIFT                  0x00000000
+#define AGP_CNTL__HOLD_RD_FIFO__SHIFT                  0x00000008
+#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT                  0x00000009
+#define AGP_CNTL__EN_2X_STBB__SHIFT                    0x0000000a
+#define AGP_CNTL__FORCE_FULL_SBA__SHIFT                        0x0000000b
+#define AGP_CNTL__SBA_DIS__SHIFT                       0x0000000c
+#define AGP_CNTL__AGP_REV_ID__SHIFT                    0x0000000d
+#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT             0x0000000e
+#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT           0x0000000f
+#define AGP_CNTL__FORCE_INT_VREF__SHIFT                        0x00000010
+#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT             0x00000011
+#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT             0x00000013
+#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT         0x00000014
+#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT            0x00000015
+#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT       0x00000016
+#define AGP_CNTL__EN_RBFCALM__SHIFT                    0x00000017
+#define AGP_CNTL__FORCE_EXT_VREF__SHIFT                        0x00000018
+#define AGP_CNTL__DIS_RBF__SHIFT                       0x00000019
+#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT            0x0000001a
+#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT           0x0000001b
+#define AGP_CNTL__AGP_MISC__SHIFT                      0x0000001e
+
+/* DISP_MISC_CNTL */
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK                0x00000001L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP             0x00000001L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK      0x00000002L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP           0x00000002L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK         0x00000004L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP              0x00000004L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK      0x00000010L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK           0x00000010L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK    0x00000020L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK         0x00000020L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK       0x00000040L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK            0x00000040L
+#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK             0x00000300L
+#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK          0x00000400L
+#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN               0x00000400L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK       0x00001000L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP            0x00001000L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK     0x00008000L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK          0x00008000L
+#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK           0x00010000L
+#define DISP_MISC_CNTL__SOFT_RESET_LVDS                        0x00010000L
+#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK           0x00020000L
+#define DISP_MISC_CNTL__SOFT_RESET_TMDS                        0x00020000L
+#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK       0x00040000L
+#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS            0x00040000L
+#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK             0x00080000L
+#define DISP_MISC_CNTL__SOFT_RESET_TV                  0x00080000L
+#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK    0x00f00000L
+#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK     0x0f000000L
+#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK     0xf0000000L
+
+/* DISP_PWR_MAN */
+#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK     0x00000001L
+#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN          0x00000001L
+#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK   0x00000010L
+#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN                0x00000010L
+#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK           0x00000300L
+#define DISP_PWR_MAN__DISP_D3_RST_MASK                 0x00010000L
+#define DISP_PWR_MAN__DISP_D3_RST                      0x00010000L
+#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK             0x00020000L
+#define DISP_PWR_MAN__DISP_D3_REG_RST                  0x00020000L
+#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK            0x00040000L
+#define DISP_PWR_MAN__DISP_D3_GRPH_RST                 0x00040000L
+#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK          0x00080000L
+#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST               0x00080000L
+#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK             0x00100000L
+#define DISP_PWR_MAN__DISP_D3_OV0_RST                  0x00100000L
+#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK          0x00200000L
+#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST               0x00200000L
+#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK                0x00400000L
+#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST             0x00400000L
+#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK           0x00800000L
+#define DISP_PWR_MAN__DISP_D1D2_OV0_RST                        0x00800000L
+#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK         0x01000000L
+#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST              0x01000000L
+#define DISP_PWR_MAN__TV_ENABLE_RST_MASK               0x02000000L
+#define DISP_PWR_MAN__TV_ENABLE_RST                    0x02000000L
+#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK               0x04000000L
+#define DISP_PWR_MAN__AUTO_PWRUP_EN                    0x04000000L
+
+/* MC_IND_INDEX */
+#define MC_IND_INDEX__MC_IND_ADDR_MASK                 0x0000001fL
+#define MC_IND_INDEX__MC_IND_WR_EN_MASK                        0x00000100L
+#define MC_IND_INDEX__MC_IND_WR_EN                     0x00000100L
+
+/* MC_IND_DATA */
+#define MC_IND_DATA__MC_IND_DATA_MASK                  0xffffffffL
+
+/* MC_CHP_IO_CNTL_A1 */
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT                0x00000000
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT         0x00000001
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT       0x00000002
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT       0x00000003
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT                0x00000004
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT         0x00000005
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT       0x00000006
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT       0x00000007
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT                0x00000008
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT      0x00000009
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT      0x0000000a
+#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT         0x0000000c
+#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT          0x0000000e
+#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT           0x00000010
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT         0x00000012
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT         0x00000014
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT      0x00000016
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT     0x00000017
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT         0x00000018
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT         0x0000001a
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT         0x0000001c
+#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT     0x0000001e
+#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT     0x0000001f
+
+/* MC_CHP_IO_CNTL_B1 */
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT                0x00000000
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT         0x00000001
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT       0x00000002
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT       0x00000003
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT                0x00000004
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT         0x00000005
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT       0x00000006
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT       0x00000007
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT                0x00000008
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT      0x00000009
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT      0x0000000a
+#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT         0x0000000c
+#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT          0x0000000e
+#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT           0x00000010
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT         0x00000012
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT         0x00000014
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT      0x00000016
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT     0x00000017
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT         0x00000018
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT         0x0000001a
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT         0x0000001c
+#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT     0x0000001e
+#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT     0x0000001f
+
+/* MC_CHP_IO_CNTL_A1 */
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK          0x00000001L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA               0x00000001L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK           0x00000002L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA                        0x00000002L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK         0x00000004L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA              0x00000004L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK         0x00000008L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA              0x00000008L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK          0x00000010L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA               0x00000010L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK           0x00000020L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA                        0x00000020L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK         0x00000040L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA              0x00000040L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK         0x00000080L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA              0x00000080L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK          0x00000100L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA               0x00000100L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK                0x00000200L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA             0x00000200L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK                0x00000400L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA             0x00000400L
+#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK           0x00003000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK            0x0000c000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK             0x00030000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK           0x000c0000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK           0x00300000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK                0x00400000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA             0x00400000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK       0x00800000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA            0x00800000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK           0x03000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK           0x0c000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK           0x10000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA                        0x10000000L
+#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK       0x40000000L
+#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A            0x40000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK       0x80000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A            0x80000000L
+
+/* MC_CHP_IO_CNTL_B1 */
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK          0x00000001L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB               0x00000001L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK           0x00000002L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB                        0x00000002L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK         0x00000004L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB              0x00000004L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK         0x00000008L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB              0x00000008L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK          0x00000010L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB               0x00000010L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK           0x00000020L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB                        0x00000020L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK         0x00000040L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB              0x00000040L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK         0x00000080L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB              0x00000080L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK          0x00000100L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB               0x00000100L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK                0x00000200L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB             0x00000200L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK                0x00000400L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB             0x00000400L
+#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK           0x00003000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK            0x0000c000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK             0x00030000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK           0x000c0000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK           0x00300000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK                0x00400000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB             0x00400000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK       0x00800000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB            0x00800000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK           0x03000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK           0x0c000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK           0x10000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB                        0x10000000L
+#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK       0x40000000L
+#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B            0x40000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK       0x80000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B            0x80000000L
+
+/* MEM_SDRAM_MODE_REG */
+#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK          0x00007fffL
+#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK                0x000f0000L
+#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK       0x00700000L
+#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK       0x00800000L
+#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY            0x00800000L
+#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK       0x01000000L
+#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY            0x01000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK      0x02000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD           0x02000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK     0x04000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA          0x04000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK      0x08000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR           0x08000000L
+#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK      0x10000000L
+#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE           0x10000000L
+#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK           0x20000000L
+#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL                        0x20000000L
+#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK          0x40000000L
+#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE               0x40000000L
+#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK       0x80000000L
+#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET            0x80000000L
+
+/* MEM_SDRAM_MODE_REG */
+#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT                0x00000000
+#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT      0x00000010
+#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT     0x00000014
+#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT     0x00000017
+#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT     0x00000018
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT    0x00000019
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT   0x0000001a
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT    0x0000001b
+#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT    0x0000001c
+#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT         0x0000001d
+#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT                0x0000001e
+#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT     0x0000001f
+
+/* MEM_REFRESH_CNTL */
+#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK                0x000000ffL
+#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK         0x00000100L
+#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS              0x00000100L
+#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK         0x00000200L
+#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE              0x00000200L
+#define MEM_REFRESH_CNTL__MEM_TRFC_MASK                        0x0000f000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK                0x00010000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE             0x00010000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK       0x00020000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE            0x00020000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK                0x00040000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE             0x00040000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK       0x00080000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE            0x00080000L
+#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK       0x00100000L
+#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE            0x00100000L
+#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK         0x00c00000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK                0x01000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE             0x01000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK       0x02000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE            0x02000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK                0x04000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE             0x04000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK       0x08000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE            0x08000000L
+#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK       0x10000000L
+#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE            0x10000000L
+#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK         0xc0000000L
+
+/* MC_STATUS */
+#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK              0x00000001L
+#define MC_STATUS__MEM_PWRUP_COMPL_A                   0x00000001L
+#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK              0x00000002L
+#define MC_STATUS__MEM_PWRUP_COMPL_B                   0x00000002L
+#define MC_STATUS__MC_IDLE_MASK                                0x00000004L
+#define MC_STATUS__MC_IDLE                             0x00000004L
+#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK             0x00000078L
+#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK             0x00000780L
+#define MC_STATUS__TEST_OUT_R_BACK_MASK                        0x00000800L
+#define MC_STATUS__TEST_OUT_R_BACK                     0x00000800L
+#define MC_STATUS__DUMMY_OUT_R_BACK_MASK               0x00001000L
+#define MC_STATUS__DUMMY_OUT_R_BACK                    0x00001000L
+#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK           0x0001e000L
+#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK           0x001e0000L
+#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK          0x01e00000L
+#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK          0x1e000000L
+
+/* MDLL_CKO */
+#define MDLL_CKO__MCKOA_SLEEP_MASK                     0x00000001L
+#define MDLL_CKO__MCKOA_SLEEP                          0x00000001L
+#define MDLL_CKO__MCKOA_RESET_MASK                     0x00000002L
+#define MDLL_CKO__MCKOA_RESET                          0x00000002L
+#define MDLL_CKO__MCKOA_RANGE_MASK                     0x0000000cL
+#define MDLL_CKO__ERSTA_SOUTSEL_MASK                   0x00000030L
+#define MDLL_CKO__MCKOA_FB_SEL_MASK                    0x000000c0L
+#define MDLL_CKO__MCKOA_REF_SKEW_MASK                  0x00000700L
+#define MDLL_CKO__MCKOA_FB_SKEW_MASK                   0x00007000L
+#define MDLL_CKO__MCKOA_BP_SEL_MASK                    0x00008000L
+#define MDLL_CKO__MCKOA_BP_SEL                         0x00008000L
+#define MDLL_CKO__MCKOB_SLEEP_MASK                     0x00010000L
+#define MDLL_CKO__MCKOB_SLEEP                          0x00010000L
+#define MDLL_CKO__MCKOB_RESET_MASK                     0x00020000L
+#define MDLL_CKO__MCKOB_RESET                          0x00020000L
+#define MDLL_CKO__MCKOB_RANGE_MASK                     0x000c0000L
+#define MDLL_CKO__ERSTB_SOUTSEL_MASK                   0x00300000L
+#define MDLL_CKO__MCKOB_FB_SEL_MASK                    0x00c00000L
+#define MDLL_CKO__MCKOB_REF_SKEW_MASK                  0x07000000L
+#define MDLL_CKO__MCKOB_FB_SKEW_MASK                   0x70000000L
+#define MDLL_CKO__MCKOB_BP_SEL_MASK                    0x80000000L
+#define MDLL_CKO__MCKOB_BP_SEL                         0x80000000L
+
+/* MDLL_RDCKA */
+#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK                 0x00000001L
+#define MDLL_RDCKA__MRDCKA0_SLEEP                      0x00000001L
+#define MDLL_RDCKA__MRDCKA0_RESET_MASK                 0x00000002L
+#define MDLL_RDCKA__MRDCKA0_RESET                      0x00000002L
+#define MDLL_RDCKA__MRDCKA0_RANGE_MASK                 0x0000000cL
+#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK               0x00000030L
+#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK                        0x000000c0L
+#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK              0x00000700L
+#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK                        0x00000800L
+#define MDLL_RDCKA__MRDCKA0_SINSEL                     0x00000800L
+#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK               0x00007000L
+#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK                        0x00008000L
+#define MDLL_RDCKA__MRDCKA0_BP_SEL                     0x00008000L
+#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK                 0x00010000L
+#define MDLL_RDCKA__MRDCKA1_SLEEP                      0x00010000L
+#define MDLL_RDCKA__MRDCKA1_RESET_MASK                 0x00020000L
+#define MDLL_RDCKA__MRDCKA1_RESET                      0x00020000L
+#define MDLL_RDCKA__MRDCKA1_RANGE_MASK                 0x000c0000L
+#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK               0x00300000L
+#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK                        0x00c00000L
+#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK              0x07000000L
+#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK                        0x08000000L
+#define MDLL_RDCKA__MRDCKA1_SINSEL                     0x08000000L
+#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK               0x70000000L
+#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK                        0x80000000L
+#define MDLL_RDCKA__MRDCKA1_BP_SEL                     0x80000000L
+
+/* MDLL_RDCKB */
+#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK                 0x00000001L
+#define MDLL_RDCKB__MRDCKB0_SLEEP                      0x00000001L
+#define MDLL_RDCKB__MRDCKB0_RESET_MASK                 0x00000002L
+#define MDLL_RDCKB__MRDCKB0_RESET                      0x00000002L
+#define MDLL_RDCKB__MRDCKB0_RANGE_MASK                 0x0000000cL
+#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK               0x00000030L
+#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK                        0x000000c0L
+#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK              0x00000700L
+#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK                        0x00000800L
+#define MDLL_RDCKB__MRDCKB0_SINSEL                     0x00000800L
+#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK               0x00007000L
+#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK                        0x00008000L
+#define MDLL_RDCKB__MRDCKB0_BP_SEL                     0x00008000L
+#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK                 0x00010000L
+#define MDLL_RDCKB__MRDCKB1_SLEEP                      0x00010000L
+#define MDLL_RDCKB__MRDCKB1_RESET_MASK                 0x00020000L
+#define MDLL_RDCKB__MRDCKB1_RESET                      0x00020000L
+#define MDLL_RDCKB__MRDCKB1_RANGE_MASK                 0x000c0000L
+#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK               0x00300000L
+#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK                        0x00c00000L
+#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK              0x07000000L
+#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK                        0x08000000L
+#define MDLL_RDCKB__MRDCKB1_SINSEL                     0x08000000L
+#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK               0x70000000L
+#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK                        0x80000000L
+#define MDLL_RDCKB__MRDCKB1_BP_SEL                     0x80000000L
+
+#define MDLL_R300_RDCK__MRDCKA_SLEEP                   0x00000001L
+#define MDLL_R300_RDCK__MRDCKA_RESET                   0x00000002L
+#define MDLL_R300_RDCK__MRDCKB_SLEEP                   0x00000004L
+#define MDLL_R300_RDCK__MRDCKB_RESET                   0x00000008L
+#define MDLL_R300_RDCK__MRDCKC_SLEEP                   0x00000010L
+#define MDLL_R300_RDCK__MRDCKC_RESET                   0x00000020L
+#define MDLL_R300_RDCK__MRDCKD_SLEEP                   0x00000040L
+#define MDLL_R300_RDCK__MRDCKD_RESET                   0x00000080L
+
+#define pllCLK_PIN_CNTL                                0x0001
+#define pllPPLL_CNTL                           0x0002
+#define pllPPLL_REF_DIV                                0x0003
+#define pllPPLL_DIV_0                          0x0004
+#define pllPPLL_DIV_1                          0x0005
+#define pllPPLL_DIV_2                          0x0006
+#define pllPPLL_DIV_3                          0x0007
+#define pllVCLK_ECP_CNTL                       0x0008
+#define pllHTOTAL_CNTL                         0x0009
+#define pllM_SPLL_REF_FB_DIV                   0x000A
+#define pllAGP_PLL_CNTL                                0x000B
+#define pllSPLL_CNTL                           0x000C
+#define pllSCLK_CNTL                           0x000D
+#define pllMPLL_CNTL                           0x000E
+#define pllMDLL_CKO                            0x000F
+#define pllMDLL_RDCKA                          0x0010
+#define pllMDLL_RDCKB                          0x0011
+#define pllMCLK_CNTL                           0x0012
+#define pllPLL_TEST_CNTL                       0x0013
+#define pllCLK_PWRMGT_CNTL                     0x0014
+#define pllPLL_PWRMGT_CNTL                     0x0015
+#define pllCG_TEST_MACRO_RW_WRITE              0x0016
+#define pllCG_TEST_MACRO_RW_READ               0x0017
+#define pllCG_TEST_MACRO_RW_DATA               0x0018
+#define pllCG_TEST_MACRO_RW_CNTL               0x0019
+#define pllDISP_TEST_MACRO_RW_WRITE            0x001A
+#define pllDISP_TEST_MACRO_RW_READ             0x001B
+#define pllDISP_TEST_MACRO_RW_DATA             0x001C
+#define pllDISP_TEST_MACRO_RW_CNTL             0x001D
+#define pllSCLK_CNTL2                          0x001E
+#define pllMCLK_MISC                           0x001F
+#define pllTV_PLL_FINE_CNTL                    0x0020
+#define pllTV_PLL_CNTL                         0x0021
+#define pllTV_PLL_CNTL1                                0x0022
+#define pllTV_DTO_INCREMENTS                   0x0023
+#define pllSPLL_AUX_CNTL                       0x0024
+#define pllMPLL_AUX_CNTL                       0x0025
+#define pllP2PLL_CNTL                          0x002A
+#define pllP2PLL_REF_DIV                       0x002B
+#define pllP2PLL_DIV_0                         0x002C
+#define pllPIXCLKS_CNTL                                0x002D
+#define pllHTOTAL2_CNTL                                0x002E
+#define pllSSPLL_CNTL                          0x0030
+#define pllSSPLL_REF_DIV                       0x0031
+#define pllSSPLL_DIV_0                         0x0032
+#define pllSS_INT_CNTL                         0x0033
+#define pllSS_TST_CNTL                         0x0034
+#define pllSCLK_MORE_CNTL                      0x0035
+
+#define ixMC_PERF_CNTL                         0x0000
+#define ixMC_PERF_SEL                          0x0001
+#define ixMC_PERF_REGION_0                     0x0002
+#define ixMC_PERF_REGION_1                     0x0003
+#define ixMC_PERF_COUNT_0                      0x0004
+#define ixMC_PERF_COUNT_1                      0x0005
+#define ixMC_PERF_COUNT_2                      0x0006
+#define ixMC_PERF_COUNT_3                      0x0007
+#define ixMC_PERF_COUNT_MEMCH_A                        0x0008
+#define ixMC_PERF_COUNT_MEMCH_B                        0x0009
+#define ixMC_IMP_CNTL                          0x000A
+#define ixMC_CHP_IO_CNTL_A0                    0x000B
+#define ixMC_CHP_IO_CNTL_A1                    0x000C
+#define ixMC_CHP_IO_CNTL_B0                    0x000D
+#define ixMC_CHP_IO_CNTL_B1                    0x000E
+#define ixMC_IMP_CNTL_0                                0x000F
+#define ixTC_MISMATCH_1                                0x0010
+#define ixTC_MISMATCH_2                                0x0011
+#define ixMC_BIST_CTRL                         0x0012
+#define ixREG_COLLAR_WRITE                     0x0013
+#define ixREG_COLLAR_READ                      0x0014
+#define ixR300_MC_IMP_CNTL                     0x0018
+#define ixR300_MC_CHP_IO_CNTL_A0               0x0019
+#define ixR300_MC_CHP_IO_CNTL_A1               0x001a
+#define ixR300_MC_CHP_IO_CNTL_B0               0x001b
+#define ixR300_MC_CHP_IO_CNTL_B1               0x001c
+#define ixR300_MC_CHP_IO_CNTL_C0               0x001d
+#define ixR300_MC_CHP_IO_CNTL_C1               0x001e
+#define ixR300_MC_CHP_IO_CNTL_D0               0x001f
+#define ixR300_MC_CHP_IO_CNTL_D1               0x0020
+#define ixR300_MC_IMP_CNTL_0                   0x0021
+#define ixR300_MC_ELPIDA_CNTL                  0x0022
+#define ixR300_MC_CHP_IO_OE_CNTL_CD            0x0023
+#define ixR300_MC_READ_CNTL_CD                 0x0024
+#define ixR300_MC_MC_INIT_WR_LAT_TIMER         0x0025
+#define ixR300_MC_DEBUG_CNTL                   0x0026
+#define ixR300_MC_BIST_CNTL_0                  0x0028
+#define ixR300_MC_BIST_CNTL_1                  0x0029
+#define ixR300_MC_BIST_CNTL_2                  0x002a
+#define ixR300_MC_BIST_CNTL_3                  0x002b
+#define ixR300_MC_BIST_CNTL_4                  0x002c
+#define ixR300_MC_BIST_CNTL_5                  0x002d
+#define ixR300_MC_IMP_STATUS                   0x002e
+#define ixR300_MC_DLL_CNTL                     0x002f
+#define NB_TOM                                 0x15C
 
 #endif /* _RADEON_H */
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