board: atmel: add SAMA5D2 PTC Engineering board
authorWenyou Yang <wenyou.yang@atmel.com>
Fri, 26 Feb 2016 09:20:26 +0000 (17:20 +0800)
committerAndreas Bießmann <andreas@biessmann.org>
Tue, 24 May 2016 06:08:35 +0000 (08:08 +0200)
The board supports following features:
 - Boot media support: NAND Flash/SPI Flash
 - Support ethernet
 - Support USB mass storage

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
arch/arm/mach-at91/Kconfig
board/atmel/sama5d2_ptc/Kconfig [new file with mode: 0644]
board/atmel/sama5d2_ptc/MAINTAINERS [new file with mode: 0644]
board/atmel/sama5d2_ptc/Makefile [new file with mode: 0644]
board/atmel/sama5d2_ptc/sama5d2_ptc.c [new file with mode: 0644]
configs/sama5d2_ptc_nandflash_defconfig [new file with mode: 0644]
configs/sama5d2_ptc_spiflash_defconfig [new file with mode: 0644]
include/configs/sama5d2_ptc.h [new file with mode: 0644]

index 9ce775e0da225b96eda876a73613d2b32596902e..73a9c74512a21a8fcfc261faefd81c9e366e42ed 100644 (file)
@@ -71,6 +71,11 @@ config TARGET_AT91SAM9X5EK
        select CPU_ARM926EJS
        select SUPPORT_SPL
 
+config TARGET_SAMA5D2_PTC
+       bool "SAMA5D2 PTC board"
+       select CPU_V7
+       select SUPPORT_SPL
+
 config TARGET_SAMA5D2_XPLAINED
        bool "SAMA5D2 Xplained board"
        select CPU_V7
@@ -138,6 +143,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig"
 source "board/atmel/at91sam9n12ek/Kconfig"
 source "board/atmel/at91sam9rlek/Kconfig"
 source "board/atmel/at91sam9x5ek/Kconfig"
+source "board/atmel/sama5d2_ptc/Kconfig"
 source "board/atmel/sama5d2_xplained/Kconfig"
 source "board/atmel/sama5d3_xplained/Kconfig"
 source "board/atmel/sama5d3xek/Kconfig"
diff --git a/board/atmel/sama5d2_ptc/Kconfig b/board/atmel/sama5d2_ptc/Kconfig
new file mode 100644 (file)
index 0000000..d2661c6
--- /dev/null
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D2_PTC
+
+config SYS_BOARD
+       default "sama5d2_ptc"
+
+config SYS_VENDOR
+       default "atmel"
+
+config SYS_SOC
+       default "at91"
+
+config SYS_CONFIG_NAME
+       default "sama5d2_ptc"
+
+endif
diff --git a/board/atmel/sama5d2_ptc/MAINTAINERS b/board/atmel/sama5d2_ptc/MAINTAINERS
new file mode 100644 (file)
index 0000000..7ab03d6
--- /dev/null
@@ -0,0 +1,7 @@
+SAMA5D2 PTC Engineering BOARD
+M:     Wenyou Yang <wenyou.yang@atmel.com>
+S:     Maintained
+F:     board/atmel/sama5d2_ptc/
+F:     include/configs/sama5d2_ptc.h
+F:     configs/sama5d2_ptc_spiflash_defconfig
+F:     configs/sama5d2_ptc_nandflash_defconfig
diff --git a/board/atmel/sama5d2_ptc/Makefile b/board/atmel/sama5d2_ptc/Makefile
new file mode 100644 (file)
index 0000000..1fe0392
--- /dev/null
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2016 Atmel
+#                   Wenyou Yang <wenyou.yang@atmel.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += sama5d2_ptc.o
diff --git a/board/atmel/sama5d2_ptc/sama5d2_ptc.c b/board/atmel/sama5d2_ptc/sama5d2_ptc.c
new file mode 100644 (file)
index 0000000..9e6544b
--- /dev/null
@@ -0,0 +1,285 @@
+/*
+ * Copyright (C) 2016 Atmel
+ *                   Wenyou.Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <atmel_hlcdc.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_usba_udc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5_sfr.h>
+#include <asm/arch/sama5d2.h>
+#include <asm/arch/sama5d3_smc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+       return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+       atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+       atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+}
+
+static void board_spi0_hw_init(void)
+{
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
+       atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);
+
+       atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+
+       at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+
+static void board_nand_hw_init(void)
+{
+       struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+       struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+
+       at91_periph_clk_enable(ATMEL_ID_HSMC);
+
+       writel(AT91_SFR_EBICFG_DRIVE0_HIGH |
+              AT91_SFR_EBICFG_PULL0_NONE |
+              AT91_SFR_EBICFG_DRIVE1_HIGH |
+              AT91_SFR_EBICFG_PULL1_NONE, &sfr->ebicfg);
+
+       /* Configure SMC CS3 for NAND */
+       writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+              AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+              &smc->cs[3].setup);
+       writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
+              AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
+              &smc->cs[3].pulse);
+       writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+              &smc->cs[3].cycle);
+       writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
+              AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
+              AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3) |
+              AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+       writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+              AT91_SMC_MODE_EXNW_DISABLE |
+              AT91_SMC_MODE_DBW_8 |
+              AT91_SMC_MODE_TDF_CYCLE(3),
+              &smc->cs[3].mode);
+
+       atmel_pio4_set_f_periph(AT91_PIO_PORTA, 0, 0);  /* D0 */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTA, 1, 0);  /* D1 */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTA, 2, 0);  /* D2 */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTA, 3, 0);  /* D3 */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTA, 4, 0);  /* D4 */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTA, 5, 0);  /* D5 */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTA, 6, 0);  /* D6 */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTA, 7, 0);  /* D7 */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTA, 12, 0); /* RE */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTA, 8, 0);  /* WE */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTA, 9, 1);  /* NCS */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTA, 21, 1); /* RDY */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTA, 10, 1); /* ALE */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTA, 11, 1); /* CLE */
+}
+
+static void board_usb_hw_init(void)
+{
+       atmel_pio4_set_pio_output(AT91_PIO_PORTA, 28, 1);
+}
+
+static void board_gmac_hw_init(void)
+{
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */
+       atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */
+
+       at91_periph_clk_enable(ATMEL_ID_GMAC);
+}
+
+static void board_uart0_hw_init(void)
+{
+       atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1); /* URXD0 */
+       atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
+
+       at91_periph_clk_enable(CONFIG_USART_ID);
+}
+
+int board_early_init_f(void)
+{
+       at91_periph_clk_enable(ATMEL_ID_PIOA);
+       at91_periph_clk_enable(ATMEL_ID_PIOB);
+       at91_periph_clk_enable(ATMEL_ID_PIOC);
+       at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+       board_uart0_hw_init();
+
+       return 0;
+}
+
+int board_init(void)
+{
+       /* address of boot parameters */
+       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_ATMEL_SPI
+       board_spi0_hw_init();
+#endif
+#ifdef CONFIG_NAND_ATMEL
+       board_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+       board_gmac_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+       board_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+       at91_udp_hw_init();
+#endif
+
+       return 0;
+}
+
+int dram_init(void)
+{
+       gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+                                   CONFIG_SYS_SDRAM_SIZE);
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+
+#ifdef CONFIG_MACB
+       rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+       if (rc)
+               printf("GMAC register failed\n");
+#endif
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+       usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+       usb_eth_initialize(bis);
+#endif
+#endif
+
+       return rc;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_SERIALFLASH
+       board_spi0_hw_init();
+#endif
+
+#ifdef CONFIG_SYS_USE_NANDFLASH
+       board_nand_hw_init();
+#endif
+}
+
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
+{
+       ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
+
+       ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+                   ATMEL_MPDDRC_CR_NR_ROW_14 |
+                   ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
+                   ATMEL_MPDDRC_CR_DIC_DS |
+                   ATMEL_MPDDRC_CR_DIS_DLL |
+                   ATMEL_MPDDRC_CR_NB_8BANKS |
+                   ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+                   ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+       ddrc->rtr = 0x511;
+
+       ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
+                     (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
+                     (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
+                     (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
+                     (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
+                     (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
+                     (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
+                     (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
+
+       ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
+                     (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
+                     (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
+                     (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
+
+       ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
+                     (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
+                     (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
+                     (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
+                     (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
+}
+
+void mem_init(void)
+{
+       struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+       struct atmel_mpddrc_config ddrc_config;
+       u32 reg;
+
+       ddrc_conf(&ddrc_config);
+
+       at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+       at91_system_clk_enable(AT91_PMC_DDR);
+
+       reg = readl(&mpddrc->io_calibr);
+       reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
+       reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
+       reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
+       reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
+       writel(reg, &mpddrc->io_calibr);
+
+       writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
+              &mpddrc->rd_data_path);
+
+       ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
+
+       writel(0x3, &mpddrc->cal_mr4);
+       writel(64, &mpddrc->tim_cal);
+}
+
+void at91_pmc_init(void)
+{
+       at91_plla_init(AT91_PMC_PLLAR_29 |
+                      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+                      AT91_PMC_PLLXR_MUL(82) |
+                      AT91_PMC_PLLXR_DIV(1));
+
+       at91_pllicpr_init(0);
+
+       at91_mck_init(AT91_PMC_MCKR_H32MXDIV |
+                     AT91_PMC_MCKR_PLLADIV_2 |
+                     AT91_PMC_MCKR_MDIV_3 |
+                     AT91_PMC_MCKR_CSS_PLLA);
+}
+#endif
diff --git a/configs/sama5d2_ptc_nandflash_defconfig b/configs/sama5d2_ptc_nandflash_defconfig
new file mode 100644 (file)
index 0000000..7425184
--- /dev/null
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_PTC=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
diff --git a/configs/sama5d2_ptc_spiflash_defconfig b/configs/sama5d2_ptc_spiflash_defconfig
new file mode 100644 (file)
index 0000000..27fc394
--- /dev/null
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_PTC=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
diff --git a/include/configs/sama5d2_ptc.h b/include/configs/sama5d2_ptc.h
new file mode 100644 (file)
index 0000000..d91d75e
--- /dev/null
@@ -0,0 +1,155 @@
+/*
+ * Configuration settings for the SAMA5D2 PTC Engineering board.
+ *
+ * Copyright (C) 2016 Atmel
+ *                   Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* No NOR flash, this definition should put before common header */
+#define CONFIG_SYS_NO_FLASH
+
+#include "at91-sama5_common.h"
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE              ATMEL_BASE_UART0
+#define CONFIG_USART_ID                        ATMEL_ID_UART0
+
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE          0x20000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR                0x210000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+       (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR           0x22000000 /* load address */
+
+#undef CONFIG_AT91_GPIO
+#define CONFIG_ATMEL_PIO4
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS           1
+
+/* SerialFlash */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SF_DEFAULT_BUS          0
+#define CONFIG_SF_DEFAULT_CS           0
+#define CONFIG_SF_DEFAULT_SPEED                30000000
+#endif
+
+/* NAND flash */
+#define CONFIG_CMD_NAND
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE       (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE       (1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_CMD_NAND_TRIMFFS
+#endif
+
+/* USB */
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS     3
+#define CONFIG_USB_STORAGE
+#endif
+
+/* USB device */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_ATMEL_USBA
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D2_PTC"
+
+#if defined(CONFIG_CMD_USB)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Ethernet Hardware */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT         20
+#define CONFIG_MACB_SEARCH_PHY
+
+#ifdef CONFIG_SYS_USE_NANDFLASH
+#undef CONFIG_ENV_OFFSET
+#undef CONFIG_ENV_OFFSET_REDUND
+#undef CONFIG_BOOTCOMMAND
+/* u-boot env in nand flash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET              0x200000
+#define CONFIG_ENV_OFFSET_REDUND       0x400000
+#define CONFIG_BOOTCOMMAND             "nand read 0x21000000 0xb80000 0x80000;"        \
+                                       "nand read 0x22000000 0x600000 0x600000;"       \
+                                       "bootz 0x22000000 - 0x21000000"
+#endif
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTARGS                                                        \
+       "console=ttyS0,57600 earlyprintk "                              \
+       "mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) "  \
+       "rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs"
+
+/* SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE           0x200000
+#define CONFIG_SPL_MAX_SIZE            0x10000
+#define CONFIG_SPL_BSS_START_ADDR      0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE                0x80000
+#define CONFIG_SYS_SPL_MALLOC_START    0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x80000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MONITOR_LEN         (512 << 10)
+
+#ifdef CONFIG_SYS_USE_SERIALFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x8000
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_PMECC_CAP               8
+#define CONFIG_PMECC_SECTOR_SIZE       512
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE      0x1000
+#define CONFIG_SYS_NAND_PAGE_COUNT     64
+#define CONFIG_SYS_NAND_OOBSIZE                224
+#define CONFIG_SYS_NAND_BLOCK_SIZE     0x40000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS  0x0
+#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
+#endif
+
+#endif