This patch changes the return type of initdram() from long int to phys_size_t.
This is required for a couple of reasons: long int limits the amount of dram
to 2GB, and u-boot in general is moving over to phys_size_t to represent the
size of physical memory. phys_size_t is defined as an unsigned long on almost
all current platforms.
This patch *only* changes the return type of the initdram function (in
include/common.h, as well as in each board's implementation of initdram). It
does not actually modify the code inside the function on any of the platforms;
platforms which wish to support more than 2GB of DRAM will need to modify
their initdram() function code.
Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc
MPC8641HPCN.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
int size,i;
** ------
** int board_early_init_f(void)
** int checkboard(void)
-** long int initdram(int board_type)
+** phys_size_t initdram(int board_type)
** called from 'board_init_f()' into 'common/board.c'
**
** void reset_phy(void)
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
return 0;
}
-long initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return articiaS_ram_init ();
}
/* ppcboot interface function to SDRAM init - this is where all the
* controlling logic happens */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
int s0 = 0, s1 = 0;
int checkbank[4] = {[0 ... 3] = 0 };
/* ppcboot interface function to SDRAM init - this is where all the
* controlling logic happens */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
int s0 = 0, s1 = 0;
int checkbank[4] = {[0 ... 3] = 0 };
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long size;
long new_bank0_end;
0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
};
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long int msize;
volatile immap_t *immap = (volatile immap_t *)CFG_IMMR;
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
u32 msize = 0;
mtspr (DBAT7U, batu);
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong size;
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return (0);
}
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return (0);
}
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return (0);
}
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return (0);
}
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return (0);
}
}
#endif
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
#if defined(CONFIG_NAND_SPL)
u32 reg;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
long dram_size;
initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
------------------------------------------------------------------------- */
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
long int ret;
* I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
* code.
*/
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
return CFG_MBYTES_SDRAM << 20;
}
return (0);
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
long dram_size = 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long dram_size = 0;
* initdram -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
#if !defined(CONFIG_NAND_SPL)
}
/*************************************************************************
- * long int initdram
+ * phys_size_t initdram
*
************************************************************************/
-long int initdram(int board)
+phys_size_t initdram(int board)
{
return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */
}
* initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
* the necessary info for SDRAM controller configuration
*/
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
return spd_sdram();
}
*tr1_value = (first_good + last_bad) / 2;
}
-long int initdram(int board)
+phys_size_t initdram(int board)
{
register uint reg;
int tr1_bank1, tr1_bank2;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
char *s = getenv ("dramsize");
return (0);
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
return 0;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
unsigned long expected_size;
unsigned long actual_size;
return 0;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
unsigned long expected_size;
unsigned long actual_size;
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
-long int
+phys_size_t
initdram(int board_type)
{
long dram_size = 0;
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long size;
long new_bank0_end;
/* barcohydra.c */
int checkboard(void);
-long int initdram(int board_type);
+phys_size_t initdram(int board_type);
void pci_init_board(void);
void check_flash(void);
int write_flash(char *addr, char value);
*/
#if defined(CONFIG_MPC5200)
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
#elif defined(CONFIG_MGT5100)
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
return 0;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
#ifdef DEBUG
int brate;
return 0;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
#ifdef DEBUG
printf("SDRAM attributes:\n");
}
#endif /* CONFIG_BFIN_IDE */
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
#ifdef DEBUG
int brate;
return 0;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
#ifdef DEBUG
int brate;
return 0;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
return 64*1024*1024;
}
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
*/
#if defined(CONFIG_MPC5200)
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
#elif defined(CONFIG_MGT5100)
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
/*
* Initalize SDRAM - configure SDRAM controller, detect memory size.
*/
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
/*
* Get RAM size.
*/
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
return (SRAM_SIZE); /* We currently have a static size adapted for cmi board. */
}
return 0;
};
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
#ifdef CONFIG_CMA111
return (32L * 1024L * 1024L);
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
int m, row, col, bank, i, ref;
unsigned long start, end;
return (size);
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
return (size);
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
}
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return (L1_MEMSIZE);
}
* configured by initialization code
*
*/
-long initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong tot_size;
ulong bank_size;
* configured by initialization code
*
*/
-long initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong tot_size;
ulong bank_size;
return 0;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
long size;
long new_bank0_end;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long val;
#include <asm/mipsregs.h>
#include <asm/io.h>
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
return (0);
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
int i, cnt;
volatile uchar *base = CFG_SDRAM_BASE;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return dram_size (board_type);
}
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return dram_size (board_type);
}
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
* initialize SDRAM/DDRAM controller.
* TBD: get data from I2C EEPROM
*****************************************************************************/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
/*****************************************************************************
* Initialize DRAM controller
*****************************************************************************/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
return 0;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
vu_char *bcsr = (vu_char *)CFG_BCSR;
long int msize = 16L << (bcsr[2] & 3);
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
return 0;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
/* Size in MB of SDRAM populated on board*/
long int msize = 256;
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long int msize;
volatile immap_t *immap = (volatile immap_t *)CFG_IMMR;
*/
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
#ifndef CONFIG_ERIC
int i;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return (16 * 1024 * 1024);
}
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long val;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long val;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long val;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long val;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long val;
* is something else than 0x00000000.
*/
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
ulong dramsize = 0;
ulong test1, test2;
/* ppcboot interface function to SDRAM init - this is where all the
* controlling logic happens */
-long int
+phys_size_t
initdram(int board_type)
{
int s0 = 0, s1 = 0;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return (16 * 1024 * 1024);
}
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return (16 * 1024 * 1024);
}
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long val;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return (16 * 1024 * 1024);
}
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long val;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long val;
* is something else than 0x00000000.
*/
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
ulong dramsize = 0;
ulong test1, test2;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long val;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long val;
* is something else than 0x00000000.
*/
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
ulong dramsize = 0;
ulong test1, test2;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long val;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long val;
* initdram -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
#if !defined(CONFIG_NAND_SPL)
};
-long int initdram (int board_type) {
+phys_size_t initdram (int board_type) {
unsigned long junk = 0xa5a59696;
/*
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long val;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long val;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long val;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
}
#endif
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
int m, row, col, bank, i;
unsigned long start, end;
return (1 << (col + row + 3) ) * bank * m;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
unsigned int msr;
long int size = 0;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* U-Boot interface function to SDRAM init - this is where all the
* controlling logic happens */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong checkbank[4] = {[0 ... 3] = 0 };
int bank_no;
}
/* ************************************************************************ */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
/* ------------------------------------------------------------------------ --
* Purpose : Determines size of mounted DRAM.
* Remarks : Size is determined by reading SDRAM configuration registers as
/* ========================================================================= */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
uint sdramsz = 0; /* size of sdram in Mbytes */
uint base = 0; /* base of dram in bytes */
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
return 0;
};
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
u32 dramsize, i;
return 0;
};
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
};
-long int initdram (int board_type) {
+phys_size_t initdram (int board_type) {
unsigned long junk = 0xa5a59696;
/*
return 0;
};
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
int i;
return 0;
};
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
return 0;
};
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
return 0;
};
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
return 0;
};
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
return 0;
};
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile siu_t *siu = (siu_t *) (MMAP_SIU);
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
return 0;
};
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile siu_t *siu = (siu_t *) (MMAP_SIU);
volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
return 0x20000000; /* 256M bytes */
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return dram_size (board_type);
}
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
#if CONFIG_ADSTYPE == CFG_PQ2FADS
long int msize = 32;
return 0;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
/* Autoinit part stolen from board/sacsng/sacsng.c */
volatile immap_t *immap = (immap_t *)CFG_IMMR;
return msize;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
volatile lbus83xx_t *lbc = &im->lbus;
return msize;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
u32 msize;
int fixed_sdram(void);
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
u32 msize = 0;
int fixed_sdram(void);
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
u32 msize = 0;
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *im = (immap_t *)CFG_IMMR;
u32 msize = 0;
};
#endif /* CONFIG_PCI */
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
u32 msize = 0;
int fixed_sdram(void);
void sdram_init(void);
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
u32 msize = 0;
return msize;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
int fixed_sdram(void);
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
u32 msize = 0;
#endif
int fixed_sdram(void);
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
immap_t *im = (immap_t *) CFG_IMMR;
u32 msize = 0;
}
-long int
+phys_size_t
initdram(int board_type)
{
long dram_size = 0;
return 0;
}
-long int
+phys_size_t
initdram(int board_type)
{
long dram_size = 0;
return 0;
}
-long int
+phys_size_t
initdram(int board_type)
{
long dram_size = 0;
return 0;
}
-long int
+phys_size_t
initdram(int board_type)
{
long dram_size = 0;
return 0;
}
-long int
+phys_size_t
initdram(int board_type)
{
long dram_size = 0;
}
-long int
+phys_size_t
initdram(int board_type)
{
long dram_size = 0;
return 0;
}
-long int
+phys_size_t
initdram(int board_type)
{
long dram_size = 0;
}
-long int
+phys_size_t
initdram(int board_type)
{
long dram_size = 0;
}
-long int
+phys_size_t
initdram(int board_type)
{
long dram_size = 0;
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
#ifndef CFG_RAMBOOT
volatile immap_t *immap;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long int ret;
#include <config.h>
#include <asm/leon.h>
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
return 1;
}
#include <config.h>
#include <asm/leon.h>
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
return 1;
}
#include <config.h>
#include <asm/leon.h>
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
return 1;
}
#include <common.h>
#include <asm/leon.h>
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
return 1;
}
#include <common.h>
#include <asm/leon.h>
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
return 1;
}
/*
* Initialize SDRAM
*/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &im->im_memctl;
#endif
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
u32 *i;
u32 j;
}
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
/* */
/* */
/*********************************************************************/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long size;
long new_bank0_end;
* is something else than 0x00000000.
*/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
/* ------------------------------------------------------------------------- */
-long
+phys_size_t
initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
*/
#if defined(CONFIG_MPC5200)
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
#elif defined(CONFIG_MGT5100)
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
return 0;
};
-long int initdram (int board_type) {
+phys_size_t initdram (int board_type) {
int i;
/*
return (size);
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
return size;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
int rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0;
ulong size, max_size = 0;
* is something else than 0x00000000.
*/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
}
};
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
return id;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long maxsize = hwc_main_sdram_size();
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
* in lib_ppc/board.c to initialize the memory and return what I
* found.
*/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
/* Configure the SDRAMS */
* is something else than 0x00000000.
*/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return (get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE));
}
}
/***********************************************************************
-F* Function: long int initdram (int board_type) P*A*Z*
+F* Function: phys_size_t initdram (int board_type) P*A*Z*
*
P* Parameters: int board_type
P* - Usually type of the board - ignored here.
C* Coding: wd@denx.de
V* Verification: dzu@denx.de
***********************************************************************/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
* initdram -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
/* CL=3 */
return 0;
};
-long int initdram (int board_type) {
+phys_size_t initdram (int board_type) {
int i;
return 0;
};
-long int initdram (int board_type) {
+phys_size_t initdram (int board_type) {
volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
sdp->sdram_sdtr = 0xf539;
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
u32 dramsize, i, dramclk;
return size;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
* is something else than 0x00000000.
*/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
return (size);
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
return (0);
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return 32 * 1024 * 1024;
}
/*
* Initalize SDRAM - configure SDRAM controller, detect memory size.
*/
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return CFG_RAM_SIZE;
}
return (0);
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long dram_size = 0;
/* ------------------------------------------------------------------------- */
static int test_dram (unsigned long ramsize);
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long bank_reg[4], tmp, bank_size;
/*
* Get RAM size.
*/
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
unsigned char board_rev;
unsigned long reg;
/* ------------------------------------------------------------------------- */
static int test_dram (unsigned long ramsize);
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long bank_reg[4], tmp, bank_size;
int i, ds;
* is something else than 0x00000000.
*/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
}
#endif
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long size;
long new_bank0_end;
return CFG_DDR_SIZE;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
u32 msize = 0;
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long size;
long new_bank0_end;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
}
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
return 0;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
long dram_size = 0;
u16 boardVersReg = in_be16((u16 *)HCU_MACH_VERSIONS_REGISTER);
* initdram -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned int dram_size = 0;
return 0;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
unsigned int dram_size = 64*1024*1024;
init_ppc405_sdram(dram_size);
}
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
}
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
#define MCR_MCLF(x) ((unsigned long)((x) & 15) << (31 - 23))
#define MCR_MCLF_MASK MCR_MCLF(15)
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
* is something else than 0x00000000.
*/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
#ifndef CFG_RAMBOOT
long size;
#include <asm/mipsregs.h>
#include <asm/io.h>
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
return in32 (REG (CPC0, RGBAN1));
}
-long initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return cpc710_ram_init ();
}
}
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long dram_size = 0;
*/
#if defined(CONFIG_MPC5200)
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
#elif defined(CONFIG_MGT5100)
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
}
-long int
+phys_size_t
initdram(int board_type)
{
long dram_size = 0;
}
-long int
+phys_size_t
initdram(int board_type)
{
long dram_size = 0;
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long size;
long new_bank0_end;
* the SDRAM was already initialised by board_asm_init (see init.S) so we just
* return the size of RAM.
*/
-long initdram( int board_type )
+phys_size_t initdram( int board_type )
{
return CFG_SDRAM_SIZE;
}
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
#define SDRAM_NOP 0x5
#define SDRAM_SELF_REFRESH 0x7
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
int tmp;
int start;
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return (0);
}
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return (0);
}
}
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
/* The only supported number of SDRAM banks is 4.
*/
#include <asm/mipsregs.h>
#include <asm/io.h>
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
return 0;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
return CFG_SDRAM_SIZE;
}
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
}
};
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
long int msize = CFG_SDRAM_SIZE;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
* Initialize sdram
*
************************************************************************/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long dram_size = 0;
}
#endif
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long size;
long new_bank0_end;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return spd_sdram ();
}
return 0;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
long size;
long new_bank0_end;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *im = (immap_t *)CFG_IMMR;
u32 msize = 0;
return 0;
}
-long int
+phys_size_t
initdram(int board_type)
{
long dram_size = 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long dram_size = 0;
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long dram_size = 0;
static unsigned int mbcf[] = {mem_mb0cf, mem_mb1cf, mem_mb2cf, mem_mb3cf};
#endif
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned int mems=0;
unsigned long ul1;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
return gd->reset_status & RSR_CSRS ? 0 : 1;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
#ifndef CFG_RAMBOOT
long size;
#define REFRESH_INIT_LOOPS (0)
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
}
#endif
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
#include <asm/mmu.h>
#include <pci.h>
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong size;
_NOT_USED_, _NOT_USED_, _NOT_USED_,
};
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return (0);
}
next_led_update += (get_tbclk() / 4);
}
-long int
+phys_size_t
initdram (int board_type)
{
long dram_size = 0;
next_led_update += (get_tbclk() / 4);
}
-long int
+phys_size_t
initdram (int board_type)
{
long dram_size = 0;
#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0)
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
}
#endif
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
return get_ram_size (CFG_SDRAM_BASE, 0x8000000);
}
#include "mt48lc16m16a2-75.h"
#endif
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
sdram_conf_t sdram_conf;
* is something else than 0x00000000.
*/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
return (size);
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
return (size);
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
/**************************************************************************
* DRAM initalization and size detection
*/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long bank_size;
long size;
}
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long dram_size = 0;
int casl;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/*
* Initialize SDRAM
*/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
* is something else than 0x00000000.
*/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
long size;
long new_bank0_end;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
#endif /* !CFG_RAMBOOT */
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
return (0);
}
-long int
+phys_size_t
initdram(int board_type)
{
return 128 * 1024 * 1024;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long dram_size = 0;
return size;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
return detect_sdram_size();
}
}
#endif /* CFG_NVRAM_ACCESS_ROUTINE */
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
vu_char *bcsr = (vu_char *)CFG_BCSR;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
* banks appropriately. If Auto Memory Configuration is
* not used, it is assumed that no DIMM is plugged
*-----------------------------------------------------------------------------*/
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
unsigned char spd0[MAX_SPD_BYTES];
* banks. The configuration is performed using static, compile-
* time parameters.
*---------------------------------------------------------------------------*/
-long initdram(int board_type)
+phys_size_t initdram(int board_type)
{
/*
* Only run this SDRAM init code once. For NAND booting
* banks appropriately. If Auto Memory Configuration is
* not used, it is assumed that no DIMM is plugged
*-----------------------------------------------------------------------------*/
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
unsigned long dimm_ranks[MAXDIMMS];
/*
* Autodetect onboard SDRAM on 405 platforms
*/
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
ulong speed;
ulong sdtr1;
* so this should be extended for other future boards
* using this routine!
*/
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
int i;
int tr1_bank1;
void hang (void) __attribute__ ((noreturn));
/* */
-long int initdram (int);
+phys_size_t initdram (int);
int display_options (void);
void print_size (phys_size_t, const char *);
int print_buffer (ulong addr, void* data, uint width, uint count, uint linelen);
}
/*
- * long int initdram(int board_type)
+ * phys_size_t initdram(int board_type)
*
* As the name already indicates, this function is called very early
* from start.S and configures the SDRAM with fixed values. This is needed,
* modules are still plugged in. So it is recommended to remove the DIMM
* modules while using the NAND booting code with the fixed SDRAM setup!
*/
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
/*
* Soft-reset SDRAM controller.
} while (!(val & 0x80000000));
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
/*
* Reset the DDR-SDRAM controller.
projects / oweals / u-boot.git / commitdiff