driver/ddr/fsl: Add workaround for A008336

Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space
for 64-bit DDR controllers.

Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index d4f688b330522294d70c7f1b612a789b7bf4d3de..256adb0a42d5c9376820e2d6fdea778ee7ac28e0 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -30,6 +30,11 @@
 #define CONFIG_SYS_FSL_PMU_CLTBENR             (CONFIG_SYS_FSL_PMU_ADDR + \
                                                 0x18A0)
 
+#define CONFIG_SYS_FSL_DCSR_DDR_ADDR           0x70012c000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR          0x70012d000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR          0x700132000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR          0x700133000ULL
+
 #define I2C1_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01000000)
 #define I2C2_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01010000)
 #define I2C3_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01020000)

diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 4eef0473439a98028395d7403fa8980eb21e8ed0..5c2579ed61e6e8f96f6e28c28734403976b13531 100644 (file)
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -32,24 +32,39 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        u32 temp_sdram_cfg;
        u32 total_gb_size_per_controller;
        int timeout;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
+       u32 *eddrtqcr1;
+#endif
 
        switch (ctrl_num) {
        case 0:
                ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
+               eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
+#endif
                break;
 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
        case 1:
                ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
+               eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
+#endif
                break;
 #endif
 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
        case 2:
                ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
+               eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
+#endif
                break;
 #endif
 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
        case 3:
                ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
+               eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800;
+#endif
                break;
 #endif
        default:
@@ -60,6 +75,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        if (step == 2)
                goto step2;
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
+#ifdef CONFIG_LS2085A
+       /* A008336 only applies to general DDR controllers */
+       if ((ctrl_num == 0) || (ctrl_num == 1))
+#endif
+               ddr_out32(eddrtqcr1, 0x63b30002);
+#endif
        if (regs->ddr_eor)
                ddr_out32(&ddr->eor, regs->ddr_eor);