powerpc: dts: add QorIQ DPAA 1 FMan to P2041RDB

Introduce the QorIQ DPAA 1 Frame Manager nodes in the P2041RDB
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

diff --git a/arch/powerpc/dts/p2041rdb.dts b/arch/powerpc/dts/p2041rdb.dts
index 6e9d9c058aca17983f0f90cab7a379a0a9f69d33..9d59f9c83313c6daeae7e895934840dd88e7f247 100644 (file)
--- a/arch/powerpc/dts/p2041rdb.dts
+++ b/arch/powerpc/dts/p2041rdb.dts
@@ -3,7 +3,7 @@
  * P2041RDB Device Tree Source
  *
  * Copyright 2011 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  */
 
 /include/ "p2041.dtsi"
@@ -15,4 +15,100 @@
        #size-cells = <2>;
        interrupt-parent = <&mpic>;
 
+       aliases {
+               phy_rgmii_0 = &phy_rgmii_0;
+               phy_rgmii_1 = &phy_rgmii_1;
+               phy_sgmii_2 = &phy_sgmii_2;
+               phy_sgmii_3 = &phy_sgmii_3;
+               phy_sgmii_4 = &phy_sgmii_4;
+               phy_sgmii_1c = &phy_sgmii_1c;
+               phy_sgmii_1d = &phy_sgmii_1d;
+               phy_sgmii_1e = &phy_sgmii_1e;
+               phy_sgmii_1f = &phy_sgmii_1f;
+               phy_xgmii_2 = &phy_xgmii_2;
+       };
+
+       soc: soc@ffe000000 {
+               ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+               reg = <0xf 0xfe000000 0 0x00001000>;
+
+               fman@400000 {
+                       ethernet@e0000 {
+                               phy-handle = <&phy_sgmii_2>;
+                               phy-connection-type = "sgmii";
+                       };
+
+                       mdio@e1120 {
+                               phy_rgmii_0: ethernet-phy@0 {
+                                       reg = <0x0>;
+                               };
+
+                               phy_rgmii_1: ethernet-phy@1 {
+                                       reg = <0x1>;
+                               };
+
+                               phy_sgmii_2: ethernet-phy@2 {
+                                       reg = <0x2>;
+                               };
+
+                               phy_sgmii_3: ethernet-phy@3 {
+                                       reg = <0x3>;
+                               };
+
+                               phy_sgmii_4: ethernet-phy@4 {
+                                       reg = <0x4>;
+                               };
+
+                               phy_sgmii_1c: ethernet-phy@1c {
+                                       reg = <0x1c>;
+                               };
+
+                               phy_sgmii_1d: ethernet-phy@1d {
+                                       reg = <0x1d>;
+                               };
+
+                               phy_sgmii_1e: ethernet-phy@1e {
+                                       reg = <0x1e>;
+                               };
+
+                               phy_sgmii_1f: ethernet-phy@1f {
+                                       reg = <0x1f>;
+                               };
+                       };
+
+                       ethernet@e2000 {
+                               phy-handle = <&phy_sgmii_3>;
+                               phy-connection-type = "sgmii";
+                       };
+
+                       ethernet@e4000 {
+                               phy-handle = <&phy_sgmii_4>;
+                               phy-connection-type = "sgmii";
+                       };
+
+                       ethernet@e6000 {
+                               phy-handle = <&phy_rgmii_1>;
+                               phy-connection-type = "rgmii";
+                       };
+
+                       ethernet@e8000 {
+                               phy-handle = <&phy_rgmii_0>;
+                               phy-connection-type = "rgmii";
+                       };
+
+                       ethernet@f0000 {
+                               phy-handle = <&phy_xgmii_2>;
+                               phy-connection-type = "xgmii";
+                       };
+
+                       mdio@f1000 {
+                               phy_xgmii_2: ethernet-phy@0 {
+                                       compatible = "ethernet-phy-ieee802.3-c45";
+                                       reg = <0x0>;
+                               };
+                       };
+               };
+       };
 };
+
+/include/ "p2041si-post.dtsi"