powerpc/t4240qds: Update IFC timing for NOR flash
authorYork Sun <yorksun@freescale.com>
Wed, 19 Dec 2012 17:23:05 +0000 (17:23 +0000)
committerAndy Fleming <afleming@freescale.com>
Wed, 30 Jan 2013 17:25:09 +0000 (11:25 -0600)
Relax parameters to give address latching more time to setup.
Tighten parameters to make it overall faster.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
include/configs/t4qds.h

index d93e0263f95ae059a6c7c1070487a853b2887b59..2c665b8a9dd656ea78e3707362d3268e6a58cce4 100644 (file)
@@ -213,14 +213,14 @@ unsigned long get_board_ddr_clk(void);
 /* NOR Flash Timing Params */
 #define CONFIG_SYS_NOR_CSOR    CSOR_NAND_TRHZ_80
 
-#define CONFIG_SYS_NOR_FTIM0   (FTIM0_NOR_TACSE(0x01) | \
-                               FTIM0_NOR_TEADC(0x01) | \
-                               FTIM0_NOR_TEAHC(0x20))
+#define CONFIG_SYS_NOR_FTIM0   (FTIM0_NOR_TACSE(0x4) | \
+                               FTIM0_NOR_TEADC(0x5) | \
+                               FTIM0_NOR_TEAHC(0x5))
 #define CONFIG_SYS_NOR_FTIM1   (FTIM1_NOR_TACO(0x35) | \
                                FTIM1_NOR_TRAD_NOR(0x1A) |\
                                FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2   (FTIM2_NOR_TCS(0x01) | \
-                               FTIM2_NOR_TCH(0x0E) | \
+#define CONFIG_SYS_NOR_FTIM2   (FTIM2_NOR_TCS(0x4) | \
+                               FTIM2_NOR_TCH(0x4) | \
                                FTIM2_NOR_TWPH(0x0E) | \
                                FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3   0x0