i.MX7ULP: Change clock rate calculation for NIC1 BUS and EXT

On i.MX7ULP B0, there is change in NIC clock dividers architecture.
On A0, the NIC1 BUS and EXT dividers were in a chain with NIC1 DIV, but
on B0 they are parallel with NIC1 DIV. So now the dividers are independent.
This patch modifies the scg_nic_get_rate function according to this change.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c
index 0d31352c77b6f8e0221e59b072d273282d7098d4..819c90af6ce97aed9fbae1bac39493545e94b1a2 100644 (file)
--- a/arch/arm/mach-imx/mx7ulp/scg.c
+++ b/arch/arm/mach-imx/mx7ulp/scg.c
@@ -352,7 +352,7 @@ static u32 scg_ddr_get_rate(void)
 
 static u32 scg_nic_get_rate(enum scg_clk clk)
 {
-       u32 reg, val, rate;
+       u32 reg, val, rate, nic0_rate;
        u32 shift, mask;
 
        reg = readl(&scg1_regs->niccsr);
@@ -370,6 +370,7 @@ static u32 scg_nic_get_rate(enum scg_clk clk)
        val = (reg & SCG_NICCSR_NIC0DIV_MASK) >> SCG_NICCSR_NIC0DIV_SHIFT;
 
        rate = rate / (val + 1);
+       nic0_rate = rate;
 
        clk_debug("scg_nic_get_rate NIC0 rate %u\n", rate);
 
@@ -411,6 +412,13 @@ static u32 scg_nic_get_rate(enum scg_clk clk)
                return 0;
        }
 
+       /*
+        * On RevB, the nic_bus and nic_ext dividers are parallel
+        * not chained with nic div
+        */
+       if (soc_rev() >= CHIP_REV_2_0)
+               rate = nic0_rate;
+
        val = (reg & mask) >> shift;
        rate = rate / (val + 1);