FSL_QUADSPI_VYBRID,
FSL_QUADSPI_IMX6SX,
FSL_QUADSPI_IMX6UL_7D,
+ FSL_QUADSPI_IMX7ULP,
};
struct fsl_qspi_devtype_data {
.driver_data = 0,
};
+static const struct fsl_qspi_devtype_data imx7ulp_data = {
+ .devtype = FSL_QUADSPI_IMX7ULP,
+ .rxfifo = 64,
+ .txfifo = 64,
+ .ahb_buf_size = 128,
+ .driver_data = 0,
+};
+
static u32 qspi_read32(u32 flags, u32 *addr)
{
return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
{ .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data },
{ .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_7d_data },
{ .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx6ul_7d_data },
+ { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data },
{ }
};