ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
- elftosb -zdf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
+ elftosb -zf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
-o $(obj)u-boot.sb
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
}
#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-const iomux_cfg_t iomux_boot[] = {
+static const iomux_cfg_t iomux_boot[] = {
MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
};
-uint8_t mxs_get_bootmode_index(void)
+static uint8_t mxs_get_bootmode_index(void)
{
uint8_t bootmode = 0;
int i;
#include "mxs_init.h"
-static uint32_t mx28_dram_vals[] = {
+static uint32_t dram_vals[] = {
+/*
+ * i.MX28 DDR2 at 200MHz
+ */
+#if defined(CONFIG_MX28)
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x06120612, 0x04320432, 0x04320432, 0x00040004,
0x00040004, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00010001
+#else
+#error Unsupported memory initialization
+#endif
};
void __mxs_adjust_memory_params(uint32_t *dram_vals)
void mxs_adjust_memory_params(uint32_t *dram_vals)
__attribute__((weak, alias("__mxs_adjust_memory_params")));
-void init_mx28_200mhz_ddr2(void)
+static void initialize_dram_values(void)
{
int i;
- mxs_adjust_memory_params(mx28_dram_vals);
+ mxs_adjust_memory_params(dram_vals);
- for (i = 0; i < ARRAY_SIZE(mx28_dram_vals); i++)
- writel(mx28_dram_vals[i], MXS_DRAM_BASE + (4 * i));
+ for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
+ writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
-void mxs_mem_init_clock(void)
+static void mxs_mem_init_clock(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
early_delay(10000);
}
-void mxs_mem_setup_cpu_and_hbus(void)
+static void mxs_mem_setup_cpu_and_hbus(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
early_delay(15000);
}
-void mxs_mem_setup_vdda(void)
+static void mxs_mem_setup_vdda(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
&power_regs->hw_power_vddactrl);
}
-void mxs_mem_setup_vddd(void)
-{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
- writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
- (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |
- POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW,
- &power_regs->hw_power_vdddctrl);
-}
-
uint32_t mxs_mem_get_size(void)
{
uint32_t sz, da;
/* Clear START bit from DRAM_CTL16 */
clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
- init_mx28_200mhz_ddr2();
+ initialize_dram_values();
/* Clear SREFRESH bit from DRAM_CTL17 */
clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
;
- mxs_mem_setup_vddd();
-
early_delay(10000);
mxs_mem_setup_cpu_and_hbus();
#include "mxs_init.h"
-void mxs_power_clock2xtal(void)
+static void mxs_power_clock2xtal(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
&clkctrl_regs->hw_clkctrl_clkseq_set);
}
-void mxs_power_clock2pll(void)
+static void mxs_power_clock2pll(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
CLKCTRL_CLKSEQ_BYPASS_CPU);
}
-void mxs_power_clear_auto_restart(void)
+static void mxs_power_clear_auto_restart(void)
{
struct mxs_rtc_regs *rtc_regs =
(struct mxs_rtc_regs *)MXS_RTC_BASE;
;
}
-void mxs_power_set_linreg(void)
+static void mxs_power_set_linreg(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
}
-int mxs_get_batt_volt(void)
+static int mxs_get_batt_volt(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
return volt;
}
-int mxs_is_batt_ready(void)
+static int mxs_is_batt_ready(void)
{
return (mxs_get_batt_volt() >= 3600);
}
-int mxs_is_batt_good(void)
+static int mxs_is_batt_good(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
return 0;
}
-void mxs_power_setup_5v_detect(void)
+static void mxs_power_setup_5v_detect(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_5VCTRL_PWRUP_VBUS_CMPS);
}
-void mxs_src_power_init(void)
+static void mxs_src_power_init(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
}
-void mxs_power_init_4p2_params(void)
+static void mxs_power_init_4p2_params(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
}
-void mxs_enable_4p2_dcdc_input(int xfer)
+static void mxs_enable_4p2_dcdc_input(int xfer)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_CTRL_ENIRQ_VDD5V_DROOP);
}
-void mxs_power_init_4p2_regulator(void)
+static void mxs_power_init_4p2_regulator(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
}
-void mxs_power_init_dcdc_4p2_source(void)
+static void mxs_power_init_dcdc_4p2_source(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
}
}
-void mxs_power_enable_4p2(void)
+static void mxs_power_enable_4p2(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
&power_regs->hw_power_charge_clr);
}
-void mxs_boot_valid_5v(void)
+static void mxs_boot_valid_5v(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
mxs_power_enable_4p2();
}
-void mxs_powerdown(void)
+static void mxs_powerdown(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
&power_regs->hw_power_reset);
}
-void mxs_batt_boot(void)
+static void mxs_batt_boot(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
}
-void mxs_handle_5v_conflict(void)
+static void mxs_handle_5v_conflict(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
}
}
-void mxs_5v_boot(void)
+static void mxs_5v_boot(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
mxs_handle_5v_conflict();
}
-void mxs_init_batt_bo(void)
+static void mxs_init_batt_bo(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
}
-void mxs_switch_vddd_to_dcdc_source(void)
+static void mxs_switch_vddd_to_dcdc_source(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_VDDDCTRL_DISABLE_STEPPING);
}
-void mxs_power_configure_power_source(void)
+static void mxs_power_configure_power_source(void)
{
int batt_ready, batt_good;
struct mxs_power_regs *power_regs =
mxs_switch_vddd_to_dcdc_source();
}
-void mxs_enable_output_rail_protection(void)
+static void mxs_enable_output_rail_protection(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_VDDIOCTRL_PWDN_BRNOUT);
}
-int mxs_get_vddio_power_source_off(void)
+static int mxs_get_vddio_power_source_off(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
}
-int mxs_get_vddd_power_source_off(void)
+static int mxs_get_vddd_power_source_off(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
return 0;
}
-void mxs_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
+struct mxs_vddx_cfg {
+ uint32_t *reg;
+ uint8_t step_mV;
+ uint16_t lowest_mV;
+ int (*powered_by_linreg)(void);
+ uint32_t trg_mask;
+ uint32_t bo_irq;
+ uint32_t bo_enirq;
+ uint32_t bo_offset_mask;
+ uint32_t bo_offset_offset;
+};
+
+static const struct mxs_vddx_cfg mxs_vddio_cfg = {
+ .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
+ hw_power_vddioctrl),
+ .step_mV = 50,
+ .lowest_mV = 2800,
+ .powered_by_linreg = mxs_get_vddio_power_source_off,
+ .trg_mask = POWER_VDDIOCTRL_TRG_MASK,
+ .bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
+ .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO,
+ .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK,
+ .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
+};
+
+static const struct mxs_vddx_cfg mxs_vddd_cfg = {
+ .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
+ hw_power_vdddctrl),
+ .step_mV = 25,
+ .lowest_mV = 800,
+ .powered_by_linreg = mxs_get_vddd_power_source_off,
+ .trg_mask = POWER_VDDDCTRL_TRG_MASK,
+ .bo_irq = POWER_CTRL_VDDD_BO_IRQ,
+ .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO,
+ .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK,
+ .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
+};
+
+static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
+ uint32_t new_target, uint32_t new_brownout)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t cur_target, diff, bo_int = 0;
uint32_t powered_by_linreg = 0;
+ int adjust_up, tmp;
- new_brownout = (new_target - new_brownout + 25) / 50;
+ new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
- cur_target = readl(&power_regs->hw_power_vddioctrl);
- cur_target &= POWER_VDDIOCTRL_TRG_MASK;
- cur_target *= 50; /* 50 mV step*/
- cur_target += 2800; /* 2800 mV lowest */
+ cur_target = readl(cfg->reg);
+ cur_target &= cfg->trg_mask;
+ cur_target *= cfg->step_mV;
+ cur_target += cfg->lowest_mV;
- powered_by_linreg = mxs_get_vddio_power_source_off();
- if (new_target > cur_target) {
+ adjust_up = new_target > cur_target;
+ powered_by_linreg = cfg->powered_by_linreg();
+ if (adjust_up) {
if (powered_by_linreg) {
- bo_int = readl(&power_regs->hw_power_vddioctrl);
- clrbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_CTRL_ENIRQ_VDDIO_BO);
+ bo_int = readl(cfg->reg);
+ clrbits_le32(cfg->reg, cfg->bo_enirq);
}
+ setbits_le32(cfg->reg, cfg->bo_offset_mask);
+ }
- setbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_VDDIOCTRL_BO_OFFSET_MASK);
- do {
- if (new_target - cur_target > 100)
+ do {
+ if (abs(new_target - cur_target) > 100) {
+ if (adjust_up)
diff = cur_target + 100;
else
- diff = new_target;
-
- diff -= 2800;
- diff /= 50;
-
- clrsetbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_VDDIOCTRL_TRG_MASK, diff);
-
- if (powered_by_linreg ||
- (readl(&power_regs->hw_power_sts) &
- POWER_STS_VDD5V_GT_VDDIO))
- early_delay(500);
- else {
- while (!(readl(&power_regs->hw_power_sts) &
- POWER_STS_DC_OK))
- ;
-
- }
-
- cur_target = readl(&power_regs->hw_power_vddioctrl);
- cur_target &= POWER_VDDIOCTRL_TRG_MASK;
- cur_target *= 50; /* 50 mV step*/
- cur_target += 2800; /* 2800 mV lowest */
- } while (new_target > cur_target);
-
- if (powered_by_linreg) {
- writel(POWER_CTRL_VDDIO_BO_IRQ,
- &power_regs->hw_power_ctrl_clr);
- if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO)
- setbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_CTRL_ENIRQ_VDDIO_BO);
- }
- } else {
- do {
- if (cur_target - new_target > 100)
diff = cur_target - 100;
- else
- diff = new_target;
-
- diff -= 2800;
- diff /= 50;
-
- clrsetbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_VDDIOCTRL_TRG_MASK, diff);
-
- if (powered_by_linreg ||
- (readl(&power_regs->hw_power_sts) &
- POWER_STS_VDD5V_GT_VDDIO))
- early_delay(500);
- else {
- while (!(readl(&power_regs->hw_power_sts) &
- POWER_STS_DC_OK))
- ;
-
- }
-
- cur_target = readl(&power_regs->hw_power_vddioctrl);
- cur_target &= POWER_VDDIOCTRL_TRG_MASK;
- cur_target *= 50; /* 50 mV step*/
- cur_target += 2800; /* 2800 mV lowest */
- } while (new_target < cur_target);
- }
-
- clrsetbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_VDDIOCTRL_BO_OFFSET_MASK,
- new_brownout << POWER_VDDIOCTRL_BO_OFFSET_OFFSET);
-}
-
-void mxs_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
-{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
- uint32_t cur_target, diff, bo_int = 0;
- uint32_t powered_by_linreg = 0;
-
- new_brownout = (new_target - new_brownout + 12) / 25;
-
- cur_target = readl(&power_regs->hw_power_vdddctrl);
- cur_target &= POWER_VDDDCTRL_TRG_MASK;
- cur_target *= 25; /* 25 mV step*/
- cur_target += 800; /* 800 mV lowest */
-
- powered_by_linreg = mxs_get_vddd_power_source_off();
- if (new_target > cur_target) {
- if (powered_by_linreg) {
- bo_int = readl(&power_regs->hw_power_vdddctrl);
- clrbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_CTRL_ENIRQ_VDDD_BO);
+ } else {
+ diff = new_target;
}
- setbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_VDDDCTRL_BO_OFFSET_MASK);
-
- do {
- if (new_target - cur_target > 100)
- diff = cur_target + 100;
- else
- diff = new_target;
-
- diff -= 800;
- diff /= 25;
-
- clrsetbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_VDDDCTRL_TRG_MASK, diff);
+ diff -= cfg->lowest_mV;
+ diff /= cfg->step_mV;
- if (powered_by_linreg ||
- (readl(&power_regs->hw_power_sts) &
- POWER_STS_VDD5V_GT_VDDIO))
- early_delay(500);
- else {
- while (!(readl(&power_regs->hw_power_sts) &
- POWER_STS_DC_OK))
- ;
+ clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
+ if (powered_by_linreg ||
+ (readl(&power_regs->hw_power_sts) &
+ POWER_STS_VDD5V_GT_VDDIO))
+ early_delay(500);
+ else {
+ for (;;) {
+ tmp = readl(&power_regs->hw_power_sts);
+ if (tmp & POWER_STS_DC_OK)
+ break;
}
-
- cur_target = readl(&power_regs->hw_power_vdddctrl);
- cur_target &= POWER_VDDDCTRL_TRG_MASK;
- cur_target *= 25; /* 25 mV step*/
- cur_target += 800; /* 800 mV lowest */
- } while (new_target > cur_target);
-
- if (powered_by_linreg) {
- writel(POWER_CTRL_VDDD_BO_IRQ,
- &power_regs->hw_power_ctrl_clr);
- if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO)
- setbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_CTRL_ENIRQ_VDDD_BO);
}
- } else {
- do {
- if (cur_target - new_target > 100)
- diff = cur_target - 100;
- else
- diff = new_target;
- diff -= 800;
- diff /= 25;
+ cur_target = readl(cfg->reg);
+ cur_target &= cfg->trg_mask;
+ cur_target *= cfg->step_mV;
+ cur_target += cfg->lowest_mV;
+ } while (new_target > cur_target);
- clrsetbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_VDDDCTRL_TRG_MASK, diff);
-
- if (powered_by_linreg ||
- (readl(&power_regs->hw_power_sts) &
- POWER_STS_VDD5V_GT_VDDIO))
- early_delay(500);
- else {
- while (!(readl(&power_regs->hw_power_sts) &
- POWER_STS_DC_OK))
- ;
-
- }
-
- cur_target = readl(&power_regs->hw_power_vdddctrl);
- cur_target &= POWER_VDDDCTRL_TRG_MASK;
- cur_target *= 25; /* 25 mV step*/
- cur_target += 800; /* 800 mV lowest */
- } while (new_target < cur_target);
+ if (adjust_up && powered_by_linreg) {
+ writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
+ if (bo_int & cfg->bo_enirq)
+ setbits_le32(cfg->reg, cfg->bo_enirq);
}
- clrsetbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_VDDDCTRL_BO_OFFSET_MASK,
- new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
+ clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
+ new_brownout << cfg->bo_offset_offset);
}
-void mxs_setup_batt_detect(void)
+static void mxs_setup_batt_detect(void)
{
mxs_lradc_init();
mxs_lradc_enable_batt_measurement();
mxs_power_configure_power_source();
mxs_enable_output_rail_protection();
- mxs_power_set_vddio(3300, 3150);
-
- mxs_power_set_vddd(1350, 1200);
+ mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
+ mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
return 0;
+}
static unsigned long exynos4_get_i2c_clk(void)
{
return 0;
}
-static int exynos4_mmc_config(int peripheral, int flags)
-{
- struct exynos4_gpio_part2 *gpio2 =
- (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
- struct s5p_gpio_bank *bank, *bank_ext;
- int i;
-
- switch (peripheral) {
- case PERIPH_ID_SDMMC0:
- bank = &gpio2->k0;
- bank_ext = &gpio2->k1;
- break;
- case PERIPH_ID_SDMMC2:
- bank = &gpio2->k2;
- bank_ext = &gpio2->k3;
- break;
- default:
- return -1;
- }
- for (i = 0; i < 7; i++) {
- if (i == 2)
- continue;
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
- s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
- s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
- }
- if (flags & PINMUX_FLAG_8BIT_MODE) {
- for (i = 3; i < 7; i++) {
- s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
- s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
- s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
- }
- }
-
- return 0;
-}
-
-static int exynos4_pinmux_config(int peripheral, int flags)
-{
- switch (peripheral) {
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC2:
- return exynos4_mmc_config(peripheral, flags);
- case PERIPH_ID_SDMMC1:
- case PERIPH_ID_SDMMC3:
- case PERIPH_ID_SDMMC4:
- printf("SDMMC device %d not implemented\n", peripheral);
- return -1;
- default:
- debug("%s: invalid peripheral %d", __func__, peripheral);
- return -1;
- }
-
- return 0;
-}
-
static void exynos4_i2c_config(int peripheral, int flags)
{
struct exynos4_gpio_part1 *gpio1 =
#include <asm/arch/regs-apbh.h>
#include <asm/arch/regs-base.h>
#include <asm/arch/regs-bch.h>
-#include <asm/arch/regs-clkctrl-mx28.h>
#include <asm/arch/regs-digctl.h>
#include <asm/arch/regs-gpmi.h>
#include <asm/arch/regs-i2c.h>
#include <asm/arch/regs-lradc.h>
#include <asm/arch/regs-ocotp.h>
#include <asm/arch/regs-pinctrl.h>
-#include <asm/arch/regs-power.h>
#include <asm/arch/regs-rtc.h>
#include <asm/arch/regs-ssp.h>
#include <asm/arch/regs-timrot.h>
+#ifdef CONFIG_MX28
+#include <asm/arch/regs-clkctrl-mx28.h>
+#include <asm/arch/regs-power-mx28.h>
+#endif
+
#endif /* __IMX_REGS_H__ */
#ifndef __ASSEMBLY__
struct mxs_clkctrl_regs {
mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
- mxs_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */
+ uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */
+ uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */
mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */
- mxs_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */
+ uint32_t hw_clkctrl_pll1ctrl1; /* 0x30 */
+ uint32_t reserved_pll1ctrl1[3]; /* 0x34-0x3c */
mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */
mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */
mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */
--- /dev/null
+/*
+ * Freescale i.MX28 Power Controller Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_POWER_H__
+#define __MX28_REGS_POWER_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mxs_power_regs {
+ mxs_reg_32(hw_power_ctrl)
+ mxs_reg_32(hw_power_5vctrl)
+ mxs_reg_32(hw_power_minpwr)
+ mxs_reg_32(hw_power_charge)
+ uint32_t hw_power_vdddctrl;
+ uint32_t reserved_vddd[3];
+ uint32_t hw_power_vddactrl;
+ uint32_t reserved_vdda[3];
+ uint32_t hw_power_vddioctrl;
+ uint32_t reserved_vddio[3];
+ uint32_t hw_power_vddmemctrl;
+ uint32_t reserved_vddmem[3];
+ uint32_t hw_power_dcdc4p2;
+ uint32_t reserved_dcdc4p2[3];
+ uint32_t hw_power_misc;
+ uint32_t reserved_misc[3];
+ uint32_t hw_power_dclimits;
+ uint32_t reserved_dclimits[3];
+ mxs_reg_32(hw_power_loopctrl)
+ uint32_t hw_power_sts;
+ uint32_t reserved_sts[3];
+ mxs_reg_32(hw_power_speed)
+ uint32_t hw_power_battmonitor;
+ uint32_t reserved_battmonitor[3];
+
+ uint32_t reserved[4];
+
+ mxs_reg_32(hw_power_reset)
+ mxs_reg_32(hw_power_debug)
+ mxs_reg_32(hw_power_thermal)
+ mxs_reg_32(hw_power_usb1ctrl)
+ mxs_reg_32(hw_power_special)
+ mxs_reg_32(hw_power_version)
+ mxs_reg_32(hw_power_anaclkctrl)
+ mxs_reg_32(hw_power_refctrl)
+};
+#endif
+
+#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27)
+#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24)
+#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23)
+#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22)
+#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21)
+#define POWER_CTRL_PSWITCH_IRQ (1 << 20)
+#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19)
+#define POWER_CTRL_POLARITY_PSWITCH (1 << 18)
+#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17)
+#define POWER_CTRL_POLARITY_DC_OK (1 << 16)
+#define POWER_CTRL_DC_OK_IRQ (1 << 15)
+#define POWER_CTRL_ENIRQ_DC_OK (1 << 14)
+#define POWER_CTRL_BATT_BO_IRQ (1 << 13)
+#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12)
+#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11)
+#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10)
+#define POWER_CTRL_VDDA_BO_IRQ (1 << 9)
+#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8)
+#define POWER_CTRL_VDDD_BO_IRQ (1 << 7)
+#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6)
+#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5)
+#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4)
+#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3)
+#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2)
+#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1)
+#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0)
+
+#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30)
+#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30
+#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30)
+#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30)
+#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30)
+#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30)
+#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24)
+#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24
+#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20)
+#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20
+#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12)
+#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12
+#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8
+#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8)
+#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7)
+#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6)
+#define POWER_5VCTRL_DCDC_XFER (1 << 5)
+#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4)
+#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3)
+#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2)
+#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1)
+#define POWER_5VCTRL_ENABLE_DCDC (1 << 0)
+
+#define POWER_MINPWR_LOWPWR_4P2 (1 << 14)
+#define POWER_MINPWR_PWD_BO (1 << 12)
+#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11)
+#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10)
+#define POWER_MINPWR_ENABLE_OSC (1 << 9)
+#define POWER_MINPWR_SELECT_OSC (1 << 8)
+#define POWER_MINPWR_VBG_OFF (1 << 7)
+#define POWER_MINPWR_DOUBLE_FETS (1 << 6)
+#define POWER_MINPWR_HALFFETS (1 << 5)
+#define POWER_MINPWR_LESSANA_I (1 << 4)
+#define POWER_MINPWR_PWD_XTAL24 (1 << 3)
+#define POWER_MINPWR_DC_STOPCLK (1 << 2)
+#define POWER_MINPWR_EN_DC_PFM (1 << 1)
+#define POWER_MINPWR_DC_HALFCLK (1 << 0)
+
+#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24)
+#define POWER_CHARGE_ADJ_VOLT_OFFSET 24
+#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24)
+#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24)
+#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24)
+#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24)
+#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24)
+#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24)
+#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24)
+#define POWER_CHARGE_ENABLE_LOAD (1 << 22)
+#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20)
+#define POWER_CHARGE_CHRG_STS_OFF (1 << 19)
+#define POWER_CHARGE_LIION_4P1 (1 << 18)
+#define POWER_CHARGE_PWD_BATTCHRG (1 << 16)
+#define POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13)
+#define POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12)
+#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8)
+#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8
+#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8)
+#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8)
+#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8)
+#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8)
+#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f
+#define POWER_CHARGE_BATTCHRG_I_OFFSET 0
+#define POWER_CHARGE_BATTCHRG_I_10MA 0x01
+#define POWER_CHARGE_BATTCHRG_I_20MA 0x02
+#define POWER_CHARGE_BATTCHRG_I_50MA 0x04
+#define POWER_CHARGE_BATTCHRG_I_100MA 0x08
+#define POWER_CHARGE_BATTCHRG_I_200MA 0x10
+#define POWER_CHARGE_BATTCHRG_I_400MA 0x20
+
+#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28)
+#define POWER_VDDDCTRL_ADJTN_OFFSET 28
+#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23)
+#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22)
+#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21)
+#define POWER_VDDDCTRL_DISABLE_FET (1 << 20)
+#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16)
+#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16
+#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16)
+#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16)
+#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16)
+#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16)
+#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8)
+#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8
+#define POWER_VDDDCTRL_TRG_MASK 0x1f
+#define POWER_VDDDCTRL_TRG_OFFSET 0
+
+#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19)
+#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18)
+#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17)
+#define POWER_VDDACTRL_DISABLE_FET (1 << 16)
+#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12)
+#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12
+#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
+#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
+#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
+#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
+#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8)
+#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8
+#define POWER_VDDACTRL_TRG_MASK 0x1f
+#define POWER_VDDACTRL_TRG_OFFSET 0
+
+#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20)
+#define POWER_VDDIOCTRL_ADJTN_OFFSET 20
+#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18)
+#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17)
+#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16)
+#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12)
+#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12
+#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
+#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
+#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
+#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
+#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8)
+#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8
+#define POWER_VDDIOCTRL_TRG_MASK 0x1f
+#define POWER_VDDIOCTRL_TRG_OFFSET 0
+
+#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10)
+#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9)
+#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8)
+#define POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5)
+#define POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5
+#define POWER_VDDMEMCTRL_TRG_MASK 0x1f
+#define POWER_VDDMEMCTRL_TRG_OFFSET 0
+
+#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28)
+#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28
+#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30)
+#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30)
+#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30)
+#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30)
+#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28)
+#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28)
+#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28)
+#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24)
+#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24
+#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23)
+#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22)
+#define POWER_DCDC4P2_HYST_DIR (1 << 21)
+#define POWER_DCDC4P2_HYST_THRESH (1 << 20)
+#define POWER_DCDC4P2_TRG_MASK (0x7 << 16)
+#define POWER_DCDC4P2_TRG_OFFSET 16
+#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16)
+#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16)
+#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16)
+#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16)
+#define POWER_DCDC4P2_TRG_BATT (0x4 << 16)
+#define POWER_DCDC4P2_BO_MASK (0x1f << 8)
+#define POWER_DCDC4P2_BO_OFFSET 8
+#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f
+#define POWER_DCDC4P2_CMPTRIP_OFFSET 0
+
+#define POWER_MISC_FREQSEL_MASK (0x7 << 4)
+#define POWER_MISC_FREQSEL_OFFSET 4
+#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4)
+#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4)
+#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4)
+#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4)
+#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4)
+#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4)
+#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4)
+#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3)
+#define POWER_MISC_DELAY_TIMING (1 << 2)
+#define POWER_MISC_TEST (1 << 1)
+#define POWER_MISC_SEL_PLLCLK (1 << 0)
+
+#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8)
+#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8
+#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f
+#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0
+
+#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20)
+#define POWER_LOOPCTRL_HYST_SIGN (1 << 19)
+#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18)
+#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17)
+#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16)
+#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15)
+#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14)
+#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12)
+#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12
+#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12)
+#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12)
+#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12)
+#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12)
+#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8)
+#define POWER_LOOPCTRL_DC_FF_OFFSET 8
+#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4)
+#define POWER_LOOPCTRL_DC_R_OFFSET 4
+#define POWER_LOOPCTRL_DC_C_MASK 0x3
+#define POWER_LOOPCTRL_DC_C_OFFSET 0
+#define POWER_LOOPCTRL_DC_C_MAX 0x0
+#define POWER_LOOPCTRL_DC_C_2X 0x1
+#define POWER_LOOPCTRL_DC_C_4X 0x2
+#define POWER_LOOPCTRL_DC_C_MIN 0x3
+
+#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24)
+#define POWER_STS_PWRUP_SOURCE_OFFSET 24
+#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24)
+#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24)
+#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24)
+#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24)
+#define POWER_STS_PSWITCH_MASK (0x3 << 20)
+#define POWER_STS_PSWITCH_OFFSET 20
+#define POWER_STS_THERMAL_WARNING (1 << 19)
+#define POWER_STS_VDDMEM_BO (1 << 18)
+#define POWER_STS_AVALID0_STATUS (1 << 17)
+#define POWER_STS_BVALID0_STATUS (1 << 16)
+#define POWER_STS_VBUSVALID0_STATUS (1 << 15)
+#define POWER_STS_SESSEND0_STATUS (1 << 14)
+#define POWER_STS_BATT_BO (1 << 13)
+#define POWER_STS_VDD5V_FAULT (1 << 12)
+#define POWER_STS_CHRGSTS (1 << 11)
+#define POWER_STS_DCDC_4P2_BO (1 << 10)
+#define POWER_STS_DC_OK (1 << 9)
+#define POWER_STS_VDDIO_BO (1 << 8)
+#define POWER_STS_VDDA_BO (1 << 7)
+#define POWER_STS_VDDD_BO (1 << 6)
+#define POWER_STS_VDD5V_GT_VDDIO (1 << 5)
+#define POWER_STS_VDD5V_DROOP (1 << 4)
+#define POWER_STS_AVALID0 (1 << 3)
+#define POWER_STS_BVALID0 (1 << 2)
+#define POWER_STS_VBUSVALID0 (1 << 1)
+#define POWER_STS_SESSEND0 (1 << 0)
+
+#define POWER_SPEED_STATUS_MASK (0xffff << 8)
+#define POWER_SPEED_STATUS_OFFSET 8
+#define POWER_SPEED_STATUS_SEL_MASK (0x3 << 6)
+#define POWER_SPEED_STATUS_SEL_OFFSET 6
+#define POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6)
+#define POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6)
+#define POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6)
+#define POWER_SPEED_CTRL_MASK 0x3
+#define POWER_SPEED_CTRL_OFFSET 0
+#define POWER_SPEED_CTRL_SS_OFF 0x0
+#define POWER_SPEED_CTRL_SS_ON 0x1
+#define POWER_SPEED_CTRL_SS_ENABLE 0x3
+
+#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16)
+#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16
+#define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11)
+#define POWER_BATTMONITOR_EN_BATADJ (1 << 10)
+#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9)
+#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8)
+#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f
+#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0
+
+#define POWER_RESET_UNLOCK_MASK (0xffff << 16)
+#define POWER_RESET_UNLOCK_OFFSET 16
+#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16)
+#define POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2)
+#define POWER_RESET_PWD_OFF (1 << 1)
+#define POWER_RESET_PWD (1 << 0)
+
+#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3)
+#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2)
+#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1)
+#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0)
+
+#define POWER_THERMAL_TEST (1 << 8)
+#define POWER_THERMAL_PWD (1 << 7)
+#define POWER_THERMAL_LOW_POWER (1 << 6)
+#define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4)
+#define POWER_THERMAL_OFFSET_ADJ_OFFSET 4
+#define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3)
+#define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7
+#define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0
+
+#define POWER_USB1CTRL_AVALID1 (1 << 3)
+#define POWER_USB1CTRL_BVALID1 (1 << 2)
+#define POWER_USB1CTRL_VBUSVALID1 (1 << 1)
+#define POWER_USB1CTRL_SESSEND1 (1 << 0)
+
+#define POWER_SPECIAL_TEST_MASK 0xffffffff
+#define POWER_SPECIAL_TEST_OFFSET 0
+
+#define POWER_VERSION_MAJOR_MASK (0xff << 24)
+#define POWER_VERSION_MAJOR_OFFSET 24
+#define POWER_VERSION_MINOR_MASK (0xff << 16)
+#define POWER_VERSION_MINOR_OFFSET 16
+#define POWER_VERSION_STEP_MASK 0xffff
+#define POWER_VERSION_STEP_OFFSET 0
+
+#define POWER_ANACLKCTRL_CLKGATE_0 (1 << 31)
+#define POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28)
+#define POWER_ANACLKCTRL_OUTDIV_OFFSET 28
+#define POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27)
+#define POWER_ANACLKCTRL_CLKGATE_I (1 << 26)
+#define POWER_ANACLKCTRL_DITHER_OFF (1 << 10)
+#define POWER_ANACLKCTRL_SLOW_DITHER (1 << 9)
+#define POWER_ANACLKCTRL_INVERT_INCLK (1 << 8)
+#define POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4)
+#define POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4
+#define POWER_ANACLKCTRL_INDIV_MASK 0x7
+#define POWER_ANACLKCTRL_INDIV_OFFSET 0
+
+#define POWER_REFCTRL_FASTSETTLING (1 << 26)
+#define POWER_REFCTRL_RAISE_REF (1 << 25)
+#define POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24)
+#define POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20)
+#define POWER_REFCTRL_VBG_ADJ_OFFSET 20
+#define POWER_REFCTRL_LOW_PWR (1 << 19)
+#define POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16)
+#define POWER_REFCTRL_BIAS_CTRL_OFFSET 16
+#define POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14)
+#define POWER_REFCTRL_ADJ_ANA (1 << 13)
+#define POWER_REFCTRL_ADJ_VAG (1 << 12)
+#define POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8)
+#define POWER_REFCTRL_ANA_REFVAL_OFFSET 8
+#define POWER_REFCTRL_VAG_VAL_MASK (0xf << 4)
+#define POWER_REFCTRL_VAG_VAL_OFFSET 4
+
+#endif /* __MX28_REGS_POWER_H__ */
+++ /dev/null
-/*
- * Freescale i.MX28 Power Controller Register Definitions
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#ifndef __MX28_REGS_POWER_H__
-#define __MX28_REGS_POWER_H__
-
-#include <asm/arch/regs-common.h>
-
-#ifndef __ASSEMBLY__
-struct mxs_power_regs {
- mxs_reg_32(hw_power_ctrl)
- mxs_reg_32(hw_power_5vctrl)
- mxs_reg_32(hw_power_minpwr)
- mxs_reg_32(hw_power_charge)
- uint32_t hw_power_vdddctrl;
- uint32_t reserved_vddd[3];
- uint32_t hw_power_vddactrl;
- uint32_t reserved_vdda[3];
- uint32_t hw_power_vddioctrl;
- uint32_t reserved_vddio[3];
- uint32_t hw_power_vddmemctrl;
- uint32_t reserved_vddmem[3];
- uint32_t hw_power_dcdc4p2;
- uint32_t reserved_dcdc4p2[3];
- uint32_t hw_power_misc;
- uint32_t reserved_misc[3];
- uint32_t hw_power_dclimits;
- uint32_t reserved_dclimits[3];
- mxs_reg_32(hw_power_loopctrl)
- uint32_t hw_power_sts;
- uint32_t reserved_sts[3];
- mxs_reg_32(hw_power_speed)
- uint32_t hw_power_battmonitor;
- uint32_t reserved_battmonitor[3];
-
- uint32_t reserved[4];
-
- mxs_reg_32(hw_power_reset)
- mxs_reg_32(hw_power_debug)
- mxs_reg_32(hw_power_thermal)
- mxs_reg_32(hw_power_usb1ctrl)
- mxs_reg_32(hw_power_special)
- mxs_reg_32(hw_power_version)
- mxs_reg_32(hw_power_anaclkctrl)
- mxs_reg_32(hw_power_refctrl)
-};
-#endif
-
-#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27)
-#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24)
-#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23)
-#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22)
-#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21)
-#define POWER_CTRL_PSWITCH_IRQ (1 << 20)
-#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19)
-#define POWER_CTRL_POLARITY_PSWITCH (1 << 18)
-#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17)
-#define POWER_CTRL_POLARITY_DC_OK (1 << 16)
-#define POWER_CTRL_DC_OK_IRQ (1 << 15)
-#define POWER_CTRL_ENIRQ_DC_OK (1 << 14)
-#define POWER_CTRL_BATT_BO_IRQ (1 << 13)
-#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12)
-#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11)
-#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10)
-#define POWER_CTRL_VDDA_BO_IRQ (1 << 9)
-#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8)
-#define POWER_CTRL_VDDD_BO_IRQ (1 << 7)
-#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6)
-#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5)
-#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4)
-#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3)
-#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2)
-#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1)
-#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0)
-
-#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30)
-#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30
-#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30)
-#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30)
-#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30)
-#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30)
-#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24)
-#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24
-#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20)
-#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20
-#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12)
-#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12
-#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8)
-#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8
-#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8)
-#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8)
-#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8)
-#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8)
-#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8)
-#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8)
-#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8)
-#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8)
-#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7)
-#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6)
-#define POWER_5VCTRL_DCDC_XFER (1 << 5)
-#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4)
-#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3)
-#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2)
-#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1)
-#define POWER_5VCTRL_ENABLE_DCDC (1 << 0)
-
-#define POWER_MINPWR_LOWPWR_4P2 (1 << 14)
-#define POWER_MINPWR_PWD_BO (1 << 12)
-#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11)
-#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10)
-#define POWER_MINPWR_ENABLE_OSC (1 << 9)
-#define POWER_MINPWR_SELECT_OSC (1 << 8)
-#define POWER_MINPWR_VBG_OFF (1 << 7)
-#define POWER_MINPWR_DOUBLE_FETS (1 << 6)
-#define POWER_MINPWR_HALFFETS (1 << 5)
-#define POWER_MINPWR_LESSANA_I (1 << 4)
-#define POWER_MINPWR_PWD_XTAL24 (1 << 3)
-#define POWER_MINPWR_DC_STOPCLK (1 << 2)
-#define POWER_MINPWR_EN_DC_PFM (1 << 1)
-#define POWER_MINPWR_DC_HALFCLK (1 << 0)
-
-#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24)
-#define POWER_CHARGE_ADJ_VOLT_OFFSET 24
-#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24)
-#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24)
-#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24)
-#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24)
-#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24)
-#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24)
-#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24)
-#define POWER_CHARGE_ENABLE_LOAD (1 << 22)
-#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20)
-#define POWER_CHARGE_CHRG_STS_OFF (1 << 19)
-#define POWER_CHARGE_LIION_4P1 (1 << 18)
-#define POWER_CHARGE_PWD_BATTCHRG (1 << 16)
-#define POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13)
-#define POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12)
-#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8)
-#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8
-#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8)
-#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8)
-#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8)
-#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8)
-#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f
-#define POWER_CHARGE_BATTCHRG_I_OFFSET 0
-#define POWER_CHARGE_BATTCHRG_I_10MA 0x01
-#define POWER_CHARGE_BATTCHRG_I_20MA 0x02
-#define POWER_CHARGE_BATTCHRG_I_50MA 0x04
-#define POWER_CHARGE_BATTCHRG_I_100MA 0x08
-#define POWER_CHARGE_BATTCHRG_I_200MA 0x10
-#define POWER_CHARGE_BATTCHRG_I_400MA 0x20
-
-#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28)
-#define POWER_VDDDCTRL_ADJTN_OFFSET 28
-#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23)
-#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22)
-#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21)
-#define POWER_VDDDCTRL_DISABLE_FET (1 << 20)
-#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16)
-#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16
-#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16)
-#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16)
-#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16)
-#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16)
-#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8)
-#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8
-#define POWER_VDDDCTRL_TRG_MASK 0x1f
-#define POWER_VDDDCTRL_TRG_OFFSET 0
-
-#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19)
-#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18)
-#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17)
-#define POWER_VDDACTRL_DISABLE_FET (1 << 16)
-#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12)
-#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12
-#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
-#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
-#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
-#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
-#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8)
-#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8
-#define POWER_VDDACTRL_TRG_MASK 0x1f
-#define POWER_VDDACTRL_TRG_OFFSET 0
-
-#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20)
-#define POWER_VDDIOCTRL_ADJTN_OFFSET 20
-#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18)
-#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17)
-#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16)
-#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12)
-#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12
-#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
-#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
-#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
-#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
-#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8)
-#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8
-#define POWER_VDDIOCTRL_TRG_MASK 0x1f
-#define POWER_VDDIOCTRL_TRG_OFFSET 0
-
-#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10)
-#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9)
-#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8)
-#define POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5)
-#define POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5
-#define POWER_VDDMEMCTRL_TRG_MASK 0x1f
-#define POWER_VDDMEMCTRL_TRG_OFFSET 0
-
-#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28)
-#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28
-#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30)
-#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30)
-#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30)
-#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30)
-#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28)
-#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28)
-#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28)
-#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24)
-#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24
-#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23)
-#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22)
-#define POWER_DCDC4P2_HYST_DIR (1 << 21)
-#define POWER_DCDC4P2_HYST_THRESH (1 << 20)
-#define POWER_DCDC4P2_TRG_MASK (0x7 << 16)
-#define POWER_DCDC4P2_TRG_OFFSET 16
-#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16)
-#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16)
-#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16)
-#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16)
-#define POWER_DCDC4P2_TRG_BATT (0x4 << 16)
-#define POWER_DCDC4P2_BO_MASK (0x1f << 8)
-#define POWER_DCDC4P2_BO_OFFSET 8
-#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f
-#define POWER_DCDC4P2_CMPTRIP_OFFSET 0
-
-#define POWER_MISC_FREQSEL_MASK (0x7 << 4)
-#define POWER_MISC_FREQSEL_OFFSET 4
-#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4)
-#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4)
-#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4)
-#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4)
-#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4)
-#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4)
-#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4)
-#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3)
-#define POWER_MISC_DELAY_TIMING (1 << 2)
-#define POWER_MISC_TEST (1 << 1)
-#define POWER_MISC_SEL_PLLCLK (1 << 0)
-
-#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8)
-#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8
-#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f
-#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0
-
-#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20)
-#define POWER_LOOPCTRL_HYST_SIGN (1 << 19)
-#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18)
-#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17)
-#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16)
-#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15)
-#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14)
-#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12)
-#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12
-#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12)
-#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12)
-#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12)
-#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12)
-#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8)
-#define POWER_LOOPCTRL_DC_FF_OFFSET 8
-#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4)
-#define POWER_LOOPCTRL_DC_R_OFFSET 4
-#define POWER_LOOPCTRL_DC_C_MASK 0x3
-#define POWER_LOOPCTRL_DC_C_OFFSET 0
-#define POWER_LOOPCTRL_DC_C_MAX 0x0
-#define POWER_LOOPCTRL_DC_C_2X 0x1
-#define POWER_LOOPCTRL_DC_C_4X 0x2
-#define POWER_LOOPCTRL_DC_C_MIN 0x3
-
-#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24)
-#define POWER_STS_PWRUP_SOURCE_OFFSET 24
-#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24)
-#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24)
-#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24)
-#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24)
-#define POWER_STS_PSWITCH_MASK (0x3 << 20)
-#define POWER_STS_PSWITCH_OFFSET 20
-#define POWER_STS_THERMAL_WARNING (1 << 19)
-#define POWER_STS_VDDMEM_BO (1 << 18)
-#define POWER_STS_AVALID0_STATUS (1 << 17)
-#define POWER_STS_BVALID0_STATUS (1 << 16)
-#define POWER_STS_VBUSVALID0_STATUS (1 << 15)
-#define POWER_STS_SESSEND0_STATUS (1 << 14)
-#define POWER_STS_BATT_BO (1 << 13)
-#define POWER_STS_VDD5V_FAULT (1 << 12)
-#define POWER_STS_CHRGSTS (1 << 11)
-#define POWER_STS_DCDC_4P2_BO (1 << 10)
-#define POWER_STS_DC_OK (1 << 9)
-#define POWER_STS_VDDIO_BO (1 << 8)
-#define POWER_STS_VDDA_BO (1 << 7)
-#define POWER_STS_VDDD_BO (1 << 6)
-#define POWER_STS_VDD5V_GT_VDDIO (1 << 5)
-#define POWER_STS_VDD5V_DROOP (1 << 4)
-#define POWER_STS_AVALID0 (1 << 3)
-#define POWER_STS_BVALID0 (1 << 2)
-#define POWER_STS_VBUSVALID0 (1 << 1)
-#define POWER_STS_SESSEND0 (1 << 0)
-
-#define POWER_SPEED_STATUS_MASK (0xffff << 8)
-#define POWER_SPEED_STATUS_OFFSET 8
-#define POWER_SPEED_STATUS_SEL_MASK (0x3 << 6)
-#define POWER_SPEED_STATUS_SEL_OFFSET 6
-#define POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6)
-#define POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6)
-#define POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6)
-#define POWER_SPEED_CTRL_MASK 0x3
-#define POWER_SPEED_CTRL_OFFSET 0
-#define POWER_SPEED_CTRL_SS_OFF 0x0
-#define POWER_SPEED_CTRL_SS_ON 0x1
-#define POWER_SPEED_CTRL_SS_ENABLE 0x3
-
-#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16)
-#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16
-#define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11)
-#define POWER_BATTMONITOR_EN_BATADJ (1 << 10)
-#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9)
-#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8)
-#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f
-#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0
-
-#define POWER_RESET_UNLOCK_MASK (0xffff << 16)
-#define POWER_RESET_UNLOCK_OFFSET 16
-#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16)
-#define POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2)
-#define POWER_RESET_PWD_OFF (1 << 1)
-#define POWER_RESET_PWD (1 << 0)
-
-#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3)
-#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2)
-#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1)
-#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0)
-
-#define POWER_THERMAL_TEST (1 << 8)
-#define POWER_THERMAL_PWD (1 << 7)
-#define POWER_THERMAL_LOW_POWER (1 << 6)
-#define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4)
-#define POWER_THERMAL_OFFSET_ADJ_OFFSET 4
-#define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3)
-#define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7
-#define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0
-
-#define POWER_USB1CTRL_AVALID1 (1 << 3)
-#define POWER_USB1CTRL_BVALID1 (1 << 2)
-#define POWER_USB1CTRL_VBUSVALID1 (1 << 1)
-#define POWER_USB1CTRL_SESSEND1 (1 << 0)
-
-#define POWER_SPECIAL_TEST_MASK 0xffffffff
-#define POWER_SPECIAL_TEST_OFFSET 0
-
-#define POWER_VERSION_MAJOR_MASK (0xff << 24)
-#define POWER_VERSION_MAJOR_OFFSET 24
-#define POWER_VERSION_MINOR_MASK (0xff << 16)
-#define POWER_VERSION_MINOR_OFFSET 16
-#define POWER_VERSION_STEP_MASK 0xffff
-#define POWER_VERSION_STEP_OFFSET 0
-
-#define POWER_ANACLKCTRL_CLKGATE_0 (1 << 31)
-#define POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28)
-#define POWER_ANACLKCTRL_OUTDIV_OFFSET 28
-#define POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27)
-#define POWER_ANACLKCTRL_CLKGATE_I (1 << 26)
-#define POWER_ANACLKCTRL_DITHER_OFF (1 << 10)
-#define POWER_ANACLKCTRL_SLOW_DITHER (1 << 9)
-#define POWER_ANACLKCTRL_INVERT_INCLK (1 << 8)
-#define POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4)
-#define POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4
-#define POWER_ANACLKCTRL_INDIV_MASK 0x7
-#define POWER_ANACLKCTRL_INDIV_OFFSET 0
-
-#define POWER_REFCTRL_FASTSETTLING (1 << 26)
-#define POWER_REFCTRL_RAISE_REF (1 << 25)
-#define POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24)
-#define POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20)
-#define POWER_REFCTRL_VBG_ADJ_OFFSET 20
-#define POWER_REFCTRL_LOW_PWR (1 << 19)
-#define POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16)
-#define POWER_REFCTRL_BIAS_CTRL_OFFSET 16
-#define POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14)
-#define POWER_REFCTRL_ADJ_ANA (1 << 13)
-#define POWER_REFCTRL_ADJ_VAG (1 << 12)
-#define POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8)
-#define POWER_REFCTRL_ANA_REFVAL_OFFSET 8
-#define POWER_REFCTRL_VAG_VAL_MASK (0xf << 4)
-#define POWER_REFCTRL_VAG_VAL_OFFSET 4
-
-#endif /* __MX28_REGS_POWER_H__ */
#include <mmc.h>
#include <fsl_esdhc.h>
#include <i2c.h>
-#include <pmic.h>
+#include <power/pmic.h>
#include <fsl_pmic.h>
#include <mc34704.h>
int board_late_init(void)
{
struct pmic *p;
+ int ret;
mx25pdk_fec_init();
- pmic_init();
- p = get_pmic();
+ ret = pmic_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get("FSL_PMIC");
+ if (!p)
+ return -ENODEV;
+
/* Turn on Ethernet PHY supply */
pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE);
if (retval)
return retval;
- p = pmic_get("DIALOG_PMIC");
+ p = pmic_get("FSL_PMIC");
if (!p)
return -ENODEV;
#include <asm/arch/mmc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/sromc.h>
-#include <pmic.h>
+#include <power/pmic.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
-#if defined(CONFIG_PMIC)
- pmic_init();
-#endif
#ifdef CONFIG_EXYNOS_SPI
spi_init();
#endif
return 0;
}
+#if defined(CONFIG_POWER)
+int power_init_board(void)
+{
+ if (pmic_init(I2C_PMIC))
+ return -1;
+ else
+ return 0;
+}
+#endif
+
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/pinmux.h>
-#include <pmic.h>
-#include <usb/s3c_udc.h>
-#include <asm/arch/cpu.h>
-#include <max8998_pmic.h>
#include <asm/arch/watchdog.h>
#include <libtizen.h>
#include <ld9040.h>
return board_rev & 0xFF;
}
-static void check_hw_revision(void);
-
-int board_init(void)
-{
- gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
- gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
-
- gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- check_hw_revision();
- printf("HW Revision:\t0x%x\n", board_rev);
-
- return 0;
-}
+static void init_pmic_lcd(void);
int power_init_board(void)
{
if (ret)
return ret;
+ init_pmic_lcd();
+
return 0;
}
unsigned char val;
int ret = 0;
- struct pmic *p = get_pmic();
+ struct pmic *p = pmic_get("MAX8998_PMIC");
+
+ if (!p)
+ return;
if (pmic_probe(p))
return;
static void lcd_power_on(void)
{
- struct pmic *p = get_pmic();
+ struct pmic *p = pmic_get("MAX8998_PMIC");
+
+ if (!p)
+ return;
if (pmic_probe(p))
return;
gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-#if defined(CONFIG_PMIC)
- pmic_init();
- init_pmic_lcd();
-#endif
#ifdef CONFIG_SOFT_SPI
soft_spi_init();
#endif
#include <asm/arch/mx35_pins.h>
#include <asm/arch/iomux.h>
#include <i2c.h>
-#include <pmic.h>
+#include <power/pmic.h>
#include <fsl_pmic.h>
#include <mc13892.h>
#include <mmc.h>
mxc_request_iomux(MX35_PIN_SCKR, MUX_CONFIG_ALT5);
gpio_direction_output(4, 1);
mxc_request_iomux(MX35_PIN_HCKT, MUX_CONFIG_ALT5);
- gpio_direction_output(9, 0);
- gpio_set_value(9, 1);
+ gpio_direction_output(9, 1);
return 0;
}
{
struct pmic *p;
u32 val;
+ int ret;
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
- pmic_init();
- p = get_pmic();
+ ret = pmic_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get("FSL_PMIC");
/*
* Set switchers in Auto in NORMAL mode & STANDBY mode
COBJS-$(CONFIG_PDSP188x) += pdsp188x.o
COBJS-$(CONFIG_STATUS_LED) += status_led.o
COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o
-COBJS-$(CONFIG_PMIC) += pmic_core.o
-COBJS-$(CONFIG_DIALOG_PMIC) += pmic_dialog.o
-COBJS-$(CONFIG_PMIC_FSL) += pmic_fsl.o
-COBJS-$(CONFIG_PMIC_I2C) += pmic_i2c.o
-COBJS-$(CONFIG_PMIC_SPI) += pmic_spi.o
-COBJS-$(CONFIG_PMIC_MAX77686) += pmic_max77686.o
-COBJS-$(CONFIG_PMIC_MAX8998) += pmic_max8998.o
-COBJS-$(CONFIG_PMIC_MAX8997) += pmic_max8997.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- * Rajeshwari Shinde <rajeshwari.s@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pmic.h>
-#include <max77686_pmic.h>
-
-int pmic_init(void)
-{
- struct pmic *p = get_pmic();
- static const char name[] = "MAX77686_PMIC";
-
- puts("Board PMIC init\n");
- p->name = name;
- p->interface = PMIC_I2C;
- p->number_of_regs = PMIC_NUM_OF_REGS;
- p->hw.i2c.addr = MAX77686_I2C_ADDR;
- p->hw.i2c.tx_num = 1;
- p->bus = I2C_PMIC;
-
- return 0;
-}
COBJS-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
+COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <power/pmic.h>
+#include <power/max77686_pmic.h>
+#include <errno.h>
+
+int pmic_init(unsigned char bus)
+{
+ static const char name[] = "MAX77686_PMIC";
+ struct pmic *p = pmic_alloc();
+
+ if (!p) {
+ printf("%s: POWER allocation error!\n", __func__);
+ return -ENOMEM;
+ }
+
+ puts("Board PMIC init\n");
+ p->name = name;
+ p->interface = PMIC_I2C;
+ p->number_of_regs = PMIC_NUM_OF_REGS;
+ p->hw.i2c.addr = MAX77686_I2C_ADDR;
+ p->hw.i2c.tx_num = 1;
+ p->bus = bus;
+
+ return 0;
+}
p->interface = PMIC_I2C;
p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR;
p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH;
- p->bus = I2C_PMIC;
+ p->bus = bus;
#else
#error "You must select CONFIG_POWER_SPI or CONFIG_PMIC_I2C"
#endif
/* U-Boot commands */
#include <config_cmd_default.h>
+#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_MMC
#define CONFIG_SYS_FSL_ESDHC_NUM 1
/* PMIC Configs */
-#define CONFIG_PMIC
-#define CONFIG_PMIC_I2C
-#define CONFIG_PMIC_FSL
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_FSL
#define CONFIG_PMIC_FSL_MC34704
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x54
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
+#define CONFIG_PMIC_FSL_MC13892
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
#define CONFIG_RTC_MC13XXX
#define CONFIG_POWER_I2C
#define CONFIG_DIALOG_POWER
#define CONFIG_POWER_FSL
+#define CONFIG_PMIC_FSL_MC13892
#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
#define INFORM1_OFFSET 0x804
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
/* select serial console configuration */
#define CONFIG_SERIAL3 /* use SERIAL 3 */
#define CONFIG_ENV_SPI_MAX_HZ 50000000
#endif
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_MAX77686
+
+/* SPI */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SPI_FLASH
+
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_EXYNOS_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED 50000000
+#define EXYNOS5_SPI_NUM_CONTROLLERS 5
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MODE SPI_MODE_0
+#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
+#define CONFIG_ENV_SPI_BUS 1
+#define CONFIG_ENV_SPI_MAX_HZ 50000000
+#endif
+
/* Ethernet Controllor Driver */
#ifdef CONFIG_CMD_NET
#define CONFIG_SMC911X
#define CONFIG_MXC_GPIO
/* PMIC Controller */
-#define CONFIG_PMIC
-#define CONFIG_PMIC_I2C
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_FSL
#define CONFIG_PMIC_FSL_MC13892
-#define CONFIG_PMIC_FSL
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
#define CONFIG_RTC_MC13XXX
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- * Rajeshwari Shinde <rajeshwari.s@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __MAX77686_H_
-#define __MAX77686_H_
-
-enum {
- MAX77686_REG_PMIC_ID = 0x0,
- MAX77686_REG_PMIC_INTSRC,
- MAX77686_REG_PMIC_INT1,
- MAX77686_REG_PMIC_INT2,
- MAX77686_REG_PMIC_INT1MSK,
- MAX77686_REG_PMIC_INT2MSK,
-
- MAX77686_REG_PMIC_STATUS1,
- MAX77686_REG_PMIC_STATUS2,
-
- MAX77686_REG_PMIC_PWRON,
- MAX77686_REG_PMIC_ONOFFDELAY,
- MAX77686_REG_PMIC_MRSTB,
-
- MAX77686_REG_PMIC_BUCK1CRTL = 0x10,
- MAX77686_REG_PMIC_BUCK1OUT,
- MAX77686_REG_PMIC_BUCK2CTRL1,
- MAX77686_REG_PMIC_BUCK234FREQ,
- MAX77686_REG_PMIC_BUCK2DVS1,
- MAX77686_REG_PMIC_BUCK2DVS2,
- MAX77686_REG_PMIC_BUCK2DVS3,
- MAX77686_REG_PMIC_BUCK2DVS4,
- MAX77686_REG_PMIC_BUCK2DVS5,
- MAX77686_REG_PMIC_BUCK2DVS6,
- MAX77686_REG_PMIC_BUCK2DVS7,
- MAX77686_REG_PMIC_BUCK2DVS8,
- MAX77686_REG_PMIC_BUCK3CTRL,
- MAX77686_REG_PMIC_BUCK3DVS1,
- MAX77686_REG_PMIC_BUCK3DVS2,
- MAX77686_REG_PMIC_BUCK3DVS3,
- MAX77686_REG_PMIC_BUCK3DVS4,
- MAX77686_REG_PMIC_BUCK3DVS5,
- MAX77686_REG_PMIC_BUCK3DVS6,
- MAX77686_REG_PMIC_BUCK3DVS7,
- MAX77686_REG_PMIC_BUCK3DVS8,
- MAX77686_REG_PMIC_BUCK4CTRL1,
- MAX77686_REG_PMIC_BUCK4DVS1 = 0x28,
- MAX77686_REG_PMIC_BUCK4DVS2,
- MAX77686_REG_PMIC_BUCK4DVS3,
- MAX77686_REG_PMIC_BUCK4DVS4,
- MAX77686_REG_PMIC_BUCK4DVS5,
- MAX77686_REG_PMIC_BUCK4DVS6,
- MAX77686_REG_PMIC_BUCK4DVS7,
- MAX77686_REG_PMIC_BUCK4DVS8,
- MAX77686_REG_PMIC_BUCK5CTRL,
- MAX77686_REG_PMIC_BUCK5OUT,
- MAX77686_REG_PMIC_BUCK6CRTL,
- MAX77686_REG_PMIC_BUCK6OUT,
- MAX77686_REG_PMIC_BUCK7CRTL,
- MAX77686_REG_PMIC_BUCK7OUT,
- MAX77686_REG_PMIC_BUCK8CRTL,
- MAX77686_REG_PMIC_BUCK8OUT,
- MAX77686_REG_PMIC_BUCK9CRTL,
- MAX77686_REG_PMIC_BUCK9OUT,
-
- MAX77686_REG_PMIC_LDO1CTRL1 = 0x40,
- MAX77686_REG_PMIC_LDO2CTRL1,
- MAX77686_REG_PMIC_LDO3CTRL1,
- MAX77686_REG_PMIC_LDO4CTRL1,
- MAX77686_REG_PMIC_LDO5CTRL1,
- MAX77686_REG_PMIC_LDO6CTRL1,
- MAX77686_REG_PMIC_LDO7CTRL1,
- MAX77686_REG_PMIC_LDO8CTRL1,
- MAX77686_REG_PMIC_LDO9CTRL1,
- MAX77686_REG_PMIC_LDO10CTRL1,
- MAX77686_REG_PMIC_LDO11CTRL1,
- MAX77686_REG_PMIC_LDO12CTRL1,
- MAX77686_REG_PMIC_LDO13CTRL1,
- MAX77686_REG_PMIC_LDO14CTRL1,
- MAX77686_REG_PMIC_LDO15CTRL1,
- MAX77686_REG_PMIC_LDO16CTRL1,
- MAX77686_REG_PMIC_LDO17CTRL1,
- MAX77686_REG_PMIC_LDO18CTRL1,
- MAX77686_REG_PMIC_LDO19CTRL1,
- MAX77686_REG_PMIC_LDO20CTRL1,
- MAX77686_REG_PMIC_LDO21CTRL1,
- MAX77686_REG_PMIC_LDO22CTRL1,
- MAX77686_REG_PMIC_LDO23CTRL1,
- MAX77686_REG_PMIC_LDO24CTRL1,
- MAX77686_REG_PMIC_LDO25CTRL1,
- MAX77686_REG_PMIC_LDO26CTRL1,
- MAX77686_REG_PMIC_LDO1CTRL2,
- MAX77686_REG_PMIC_LDO2CTRL2,
- MAX77686_REG_PMIC_LDO3CTRL2,
- MAX77686_REG_PMIC_LDO4CTRL2,
- MAX77686_REG_PMIC_LDO5CTRL2,
- MAX77686_REG_PMIC_LDO6CTRL2,
- MAX77686_REG_PMIC_LDO7CTRL2,
- MAX77686_REG_PMIC_LDO8CTRL2,
- MAX77686_REG_PMIC_LDO9CTRL2,
- MAX77686_REG_PMIC_LDO10CTRL2,
- MAX77686_REG_PMIC_LDO11CTRL2,
- MAX77686_REG_PMIC_LDO12CTRL2,
- MAX77686_REG_PMIC_LDO13CTRL2,
- MAX77686_REG_PMIC_LDO14CTRL2,
- MAX77686_REG_PMIC_LDO15CTRL2,
- MAX77686_REG_PMIC_LDO16CTRL2,
- MAX77686_REG_PMIC_LDO17CTRL2,
- MAX77686_REG_PMIC_LDO18CTRL2,
- MAX77686_REG_PMIC_LDO19CTRL2,
- MAX77686_REG_PMIC_LDO20CTRL2,
- MAX77686_REG_PMIC_LDO21CTRL2,
- MAX77686_REG_PMIC_LDO22CTRL2,
- MAX77686_REG_PMIC_LDO23CTRL2,
- MAX77686_REG_PMIC_LDO24CTRL2,
- MAX77686_REG_PMIC_LDO25CTRL2,
- MAX77686_REG_PMIC_LDO26CTRL2,
-
- MAX77686_REG_PMIC_BBAT = 0x7e,
- MAX77686_REG_PMIC_32KHZ,
-
- PMIC_NUM_OF_REGS,
-};
-
-/* I2C device address for pmic max77686 */
-#define MAX77686_I2C_ADDR (0x12 >> 1)
-
-enum {
- REG_DISABLE = 0,
- REG_ENABLE
-};
-
-enum {
- LDO_OFF = 0,
- LDO_ON,
-
- DIS_LDO = (0x00 << 6),
- EN_LDO = (0x3 << 6),
-};
-
-#endif /* __MAX77686_PMIC_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MAX77686_H_
+#define __MAX77686_H_
+
+enum {
+ MAX77686_REG_PMIC_ID = 0x0,
+ MAX77686_REG_PMIC_INTSRC,
+ MAX77686_REG_PMIC_INT1,
+ MAX77686_REG_PMIC_INT2,
+ MAX77686_REG_PMIC_INT1MSK,
+ MAX77686_REG_PMIC_INT2MSK,
+
+ MAX77686_REG_PMIC_STATUS1,
+ MAX77686_REG_PMIC_STATUS2,
+
+ MAX77686_REG_PMIC_PWRON,
+ MAX77686_REG_PMIC_ONOFFDELAY,
+ MAX77686_REG_PMIC_MRSTB,
+
+ MAX77686_REG_PMIC_BUCK1CRTL = 0x10,
+ MAX77686_REG_PMIC_BUCK1OUT,
+ MAX77686_REG_PMIC_BUCK2CTRL1,
+ MAX77686_REG_PMIC_BUCK234FREQ,
+ MAX77686_REG_PMIC_BUCK2DVS1,
+ MAX77686_REG_PMIC_BUCK2DVS2,
+ MAX77686_REG_PMIC_BUCK2DVS3,
+ MAX77686_REG_PMIC_BUCK2DVS4,
+ MAX77686_REG_PMIC_BUCK2DVS5,
+ MAX77686_REG_PMIC_BUCK2DVS6,
+ MAX77686_REG_PMIC_BUCK2DVS7,
+ MAX77686_REG_PMIC_BUCK2DVS8,
+ MAX77686_REG_PMIC_BUCK3CTRL,
+ MAX77686_REG_PMIC_BUCK3DVS1,
+ MAX77686_REG_PMIC_BUCK3DVS2,
+ MAX77686_REG_PMIC_BUCK3DVS3,
+ MAX77686_REG_PMIC_BUCK3DVS4,
+ MAX77686_REG_PMIC_BUCK3DVS5,
+ MAX77686_REG_PMIC_BUCK3DVS6,
+ MAX77686_REG_PMIC_BUCK3DVS7,
+ MAX77686_REG_PMIC_BUCK3DVS8,
+ MAX77686_REG_PMIC_BUCK4CTRL1,
+ MAX77686_REG_PMIC_BUCK4DVS1 = 0x28,
+ MAX77686_REG_PMIC_BUCK4DVS2,
+ MAX77686_REG_PMIC_BUCK4DVS3,
+ MAX77686_REG_PMIC_BUCK4DVS4,
+ MAX77686_REG_PMIC_BUCK4DVS5,
+ MAX77686_REG_PMIC_BUCK4DVS6,
+ MAX77686_REG_PMIC_BUCK4DVS7,
+ MAX77686_REG_PMIC_BUCK4DVS8,
+ MAX77686_REG_PMIC_BUCK5CTRL,
+ MAX77686_REG_PMIC_BUCK5OUT,
+ MAX77686_REG_PMIC_BUCK6CRTL,
+ MAX77686_REG_PMIC_BUCK6OUT,
+ MAX77686_REG_PMIC_BUCK7CRTL,
+ MAX77686_REG_PMIC_BUCK7OUT,
+ MAX77686_REG_PMIC_BUCK8CRTL,
+ MAX77686_REG_PMIC_BUCK8OUT,
+ MAX77686_REG_PMIC_BUCK9CRTL,
+ MAX77686_REG_PMIC_BUCK9OUT,
+
+ MAX77686_REG_PMIC_LDO1CTRL1 = 0x40,
+ MAX77686_REG_PMIC_LDO2CTRL1,
+ MAX77686_REG_PMIC_LDO3CTRL1,
+ MAX77686_REG_PMIC_LDO4CTRL1,
+ MAX77686_REG_PMIC_LDO5CTRL1,
+ MAX77686_REG_PMIC_LDO6CTRL1,
+ MAX77686_REG_PMIC_LDO7CTRL1,
+ MAX77686_REG_PMIC_LDO8CTRL1,
+ MAX77686_REG_PMIC_LDO9CTRL1,
+ MAX77686_REG_PMIC_LDO10CTRL1,
+ MAX77686_REG_PMIC_LDO11CTRL1,
+ MAX77686_REG_PMIC_LDO12CTRL1,
+ MAX77686_REG_PMIC_LDO13CTRL1,
+ MAX77686_REG_PMIC_LDO14CTRL1,
+ MAX77686_REG_PMIC_LDO15CTRL1,
+ MAX77686_REG_PMIC_LDO16CTRL1,
+ MAX77686_REG_PMIC_LDO17CTRL1,
+ MAX77686_REG_PMIC_LDO18CTRL1,
+ MAX77686_REG_PMIC_LDO19CTRL1,
+ MAX77686_REG_PMIC_LDO20CTRL1,
+ MAX77686_REG_PMIC_LDO21CTRL1,
+ MAX77686_REG_PMIC_LDO22CTRL1,
+ MAX77686_REG_PMIC_LDO23CTRL1,
+ MAX77686_REG_PMIC_LDO24CTRL1,
+ MAX77686_REG_PMIC_LDO25CTRL1,
+ MAX77686_REG_PMIC_LDO26CTRL1,
+ MAX77686_REG_PMIC_LDO1CTRL2,
+ MAX77686_REG_PMIC_LDO2CTRL2,
+ MAX77686_REG_PMIC_LDO3CTRL2,
+ MAX77686_REG_PMIC_LDO4CTRL2,
+ MAX77686_REG_PMIC_LDO5CTRL2,
+ MAX77686_REG_PMIC_LDO6CTRL2,
+ MAX77686_REG_PMIC_LDO7CTRL2,
+ MAX77686_REG_PMIC_LDO8CTRL2,
+ MAX77686_REG_PMIC_LDO9CTRL2,
+ MAX77686_REG_PMIC_LDO10CTRL2,
+ MAX77686_REG_PMIC_LDO11CTRL2,
+ MAX77686_REG_PMIC_LDO12CTRL2,
+ MAX77686_REG_PMIC_LDO13CTRL2,
+ MAX77686_REG_PMIC_LDO14CTRL2,
+ MAX77686_REG_PMIC_LDO15CTRL2,
+ MAX77686_REG_PMIC_LDO16CTRL2,
+ MAX77686_REG_PMIC_LDO17CTRL2,
+ MAX77686_REG_PMIC_LDO18CTRL2,
+ MAX77686_REG_PMIC_LDO19CTRL2,
+ MAX77686_REG_PMIC_LDO20CTRL2,
+ MAX77686_REG_PMIC_LDO21CTRL2,
+ MAX77686_REG_PMIC_LDO22CTRL2,
+ MAX77686_REG_PMIC_LDO23CTRL2,
+ MAX77686_REG_PMIC_LDO24CTRL2,
+ MAX77686_REG_PMIC_LDO25CTRL2,
+ MAX77686_REG_PMIC_LDO26CTRL2,
+
+ MAX77686_REG_PMIC_BBAT = 0x7e,
+ MAX77686_REG_PMIC_32KHZ,
+
+ PMIC_NUM_OF_REGS,
+};
+
+/* I2C device address for pmic max77686 */
+#define MAX77686_I2C_ADDR (0x12 >> 1)
+
+enum {
+ REG_DISABLE = 0,
+ REG_ENABLE
+};
+
+enum {
+ LDO_OFF = 0,
+ LDO_ON,
+
+ DIS_LDO = (0x00 << 6),
+ EN_LDO = (0x3 << 6),
+};
+
+#endif /* __MAX77686_PMIC_H_ */
projects / oweals / u-boot.git / commitdiff